Initial import of NFC GNSS SDK project
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chenjintao
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/******************************************************************************
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*
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* (C)Copyright 2005 - 2011 Marvell. All Rights Reserved.
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*
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* THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MARVELL.
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* The copyright notice above does not evidence any actual or intended
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* publication of such source code.
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* This Module contains Proprietary Information of Marvell and should be
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* treated as Confidential.
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* The information in this file is provided for the exclusive use of the
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* licensees of Marvell.
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* Such users have the right to use, modify, and incorporate this code into
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* products for purposes authorized by the license agreement provided they
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* include this notice and the associated copyright notice with any such
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* product.
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* The information in this file is provided "AS IS" without warranty.
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******************************************************************************
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**
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** FILENAME: PlatformConfig.h
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**
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** PURPOSE: Platform specific header to set parameters
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**
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**
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******************************************************************************/
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#ifndef __platform_config_h
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#define __platform_config_h
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#include "common.h"
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#include "cpu.h"
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#include "guilin.h"
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#define QUEC_INSTRUCTION_MODE 1
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#define QUECTEL_PROJECT_CUST
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#define __REG(x) (*((volatile unsigned int *)(x)))
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//some simple defines to clean up code a touch
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#define reg_read(reg) *(volatile unsigned int *)(reg)
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#define reg_write(reg, val) *(volatile unsigned int *)reg = val; *(volatile unsigned int *)reg;
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#define reg_bit_set(reg, val) *(volatile unsigned int *)reg |= val; *(volatile unsigned int *)reg;
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#define reg_bit_clr(reg, val) *(volatile unsigned int *)reg &= ~val; *(volatile unsigned int *)reg;
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/*
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*
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* THE BASE ADDRESSES
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*
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*/
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#define GPIO0_BASE 0xD4019000
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#define GPIO1_BASE 0xD4019004
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#define GPIO2_BASE 0xD4019008
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#define GPIO3_BASE 0xD4019100
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/*
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*
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* THE REGISTER DEFINES
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*
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*/
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#define GPIO_PLR (0x0000) /* 32 bit GPIO Pin-Level Register */
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#define GPIO_PDR (0x000C) /* 32 bit GPIO Pin Direction Register */
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#define GPIO_PSR (0x0018) /* 32 bit GPIO Pin Output Set Register */
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#define GPIO_PCR (0x0024) /* 32 bit GPIO Pin Output Clear
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* Register
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*/
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#define GPIO_RER (0x0030) /* 32 bit GPIO Rising-Edge Detect
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* Enable Register
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*/
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#define GPIO_FERX (0x003C) /* 32 bit GPIO Falling-Edge Detect
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* Enable Register
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*/
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#define GPIO_EDR (0x0048) /* 32 bit GPIO Edge Detect Status
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* Register
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*/
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#define GPIO_SDR (0x0054) /* 32 bit Bit-wise Set of GPIO
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* Direction Register
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*/
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#define GPIO_CDR (0x0060) /* 32 bit Bit-wise Clear of GPIO
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* Direction Register
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*/
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#define GPIO_SRERX (0x006c) /* 32 bit Bit-wise Set of GPIO Rising
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* Edge Detect Enable
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* Register
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*/
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#define GPIO_CRERX (0x0078) /* 32 bit Bit-wise Clear of GPIO
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* Rising Edge Detect Enable
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* Register
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*/
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#define GPIO_SFER (0x0084) /* 32 bit Bit-wise Set of GPIO
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* Falling Edge Detect
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* Enable Register
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*/
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#define GPIO_CFER (0x0090) /* 32 bit Bit-wise Clear of GPIO
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* Falling Edge Detect
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* Enable Register
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*/
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#define APMASK (0x009c) /* 32 bit AP Bit-wise Mask of GPIO
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* Edge Detect Register
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*/
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#define CPMASK (0x00a8) /* 32 bit CP Bit-wise Mask of GPIO
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* Edge Detect Register
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*/
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#define APPS_PAD_BASE 0xd401e000
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#define NET_MODE_GPIO (2)
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#define SLEEP_IND_GPIO (5)
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#define NET_STATUS_GPIO (6)
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#define OFFSET_NET_MODE_GPIO (0x0E4)
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#define OFFSET_SLEEP_IND_GPIO (0x0F0)
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#define OFFSET_NET_STATUS_GPIO (0x0F4)
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#define CP_UART_BASE 0xd4017000
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//const int quec_gpio_map_pin_table_size = sizeof(quec_gpio_map_pin_table)/sizeof(quec_gpio_map_pin_s);
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#define SerialDATA __REG(CP_UART_BASE+0x00) /* Receive Buffer Register (read only) */
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#define SerialFIFO __REG(CP_UART_BASE+0x08) /* FIFO Control Register (write only) */
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#define SerialLCR __REG(CP_UART_BASE+0x0c) /* Line Control Register (read/write) */
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#define SerialMCR __REG(CP_UART_BASE+0x10) /* Modem Control Register (read/write) */
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#define SerialLSR __REG(CP_UART_BASE+0x14) /* Line Status Register (read only) */
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#define SerialMSR __REG(CP_UART_BASE+0x18) /* Modem Status Register (read only) */
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#define SerialSCR __REG(CP_UART_BASE+0x1c) /* Scratchpad Register*/
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#define SerialIER __REG(CP_UART_BASE+0x04) /* Interrupt Enable Register (read/write) */
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#define SerialABR __REG(CP_UART_BASE+0x28)
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#define GPIO_MFPR_BASE1 0xD401E0DC
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#define GPIO_MFPR_BASE2 0xD401E1A0
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#define GPIO_MFPR_BASE3 0xD401E304
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#define GPIO_MFPR_BASE4 0xD401E1B8
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#ifdef QUECTEL_PROJECT_CUST //Chaim 20191113 base addr is error,fixd it
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#define GPIO_MFPR_BASE5 0xD401E1E0
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#else
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#define GPIO_MFPR_BASE5 0xD401E1F0
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#endif
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#define GPIO_MFPR_BASE6 0xD401E0D0
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#define GPIO_MFPR_BASE7 0xD401E2EC
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#define GPIO_MFPR_BASE8 0xD401E2E4
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#define GPIO_MFPR_BASE9 0xD401E2BC
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#define GPIO_MFPR_BASE10 0xD401E32C
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#define INVALID_GPIO_MFPR_ADDR 0xFFFFFFFF
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#ifdef QUECTEL_PROJECT_CUST
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#define GPIO_MFPR_BASE11 0xD401E0C8
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#define GPIO_MFPR_ADDR(n) ( n <= 36 ? GPIO_MFPR_BASE1 + (n << 2): \
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((n <= 54) &&(n >=49)) ? GPIO_MFPR_BASE2 + ((n-49) << 2): \
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((n <= 66)&&(n >=60) ) ? GPIO_MFPR_BASE3 + ((n-60) << 2): \
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((n <= 78)&&(n>=71)) ? GPIO_MFPR_BASE4 + ((n-71)<<2): \
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((n <= 86)&&(n>=81) ) ? GPIO_MFPR_BASE5 + ((n-81) << 2): \
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(n == 124)? GPIO_MFPR_BASE6 : \
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(n == 122)? GPIO_MFPR_BASE11 : \
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(n == 48 )? GPIO_MFPR_BASE7 : \
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(n == 121 )? GPIO_MFPR_BASE10 : \
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((n <= 80)&&(n >=79)) ? GPIO_MFPR_BASE8 + ((n-79)<<2) : \
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((n <= 70)&&(n >=69)) ? GPIO_MFPR_BASE9 + ((n-69)<<2) :INVALID_GPIO_MFPR_ADDR)
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#else
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#define GPIO_MFPR_ADDR(n) ( n <= 36 ? GPIO_MFPR_BASE1 + (n << 2): \
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((n <= 54) &&(n >=49)) ? GPIO_MFPR_BASE2 + ((n-49) << 2): \
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((n <= 66)&&(n >=60) ) ? GPIO_MFPR_BASE3 + ((n-60) << 2): \
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((n <= 78)&&(n>=71)) ? GPIO_MFPR_BASE4 + ((n-71)<<2): \
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((n <= 86)&&(n>=81) ) ? GPIO_MFPR_BASE5 + ((n-81) << 2): \
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((n == 124)|| (n == 122))? GPIO_MFPR_BASE6 : \
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(n == 48 )? GPIO_MFPR_BASE7 : \
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(n == 121 )? GPIO_MFPR_BASE10 : \
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((n <= 80)&&(n >=79)) ? GPIO_MFPR_BASE8 + ((n-79)<<2) : \
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((n <= 70)&&(n >=69)) ? GPIO_MFPR_BASE9 + ((n-69)<<2) :INVALID_GPIO_MFPR_ADDR)
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#endif
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typedef struct
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{
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volatile int * registerAddr;
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unsigned int regValue;
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unsigned int defaultValue;
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}CS_REGISTER_PAIR_S, *P_CS_REGISTER_PAIR_S;
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typedef struct
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{
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int pin;
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int gpio;
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CS_REGISTER_PAIR_S reg_config;
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}quec_gpio_map_pin_s;
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void quec_instruction_mode(void);
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int serial_read_byte(void);
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void timerDelay_us(UINT32 us);
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extern void cp_uart_putc(const char ch);
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extern int GuilinWrite( Guilin_Reg_Type guilin_reg_type, unsigned char reg, unsigned char value );
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#endif
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