Initial import of NFC GNSS SDK project
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chenjintao
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#ifndef _SPI_FLASH_H
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#define _SPI_FLASH_H
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#define false 0
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#define true 1
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#ifndef min
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#define min(a, b) ((a) < (b) ? (a) : (b))
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#endif
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#ifndef max
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#define max(a, b) ((a) > (b) ? (a) : (b))
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#endif
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/* Vendor Manufacture ID */
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#define SPIFLASH_MFR_MICRON 0x2C
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#define SPIFLASH_MFR_GIGADEVICE 0xC8
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#define SPIFLASH_MFR_WINBOND 0xEF
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#define SPIFLASH_MFR_MXIC 0xC2
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#define SPIFLASH_MFR_DOSILICON 0xE5
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#define SPIFLASH_MFR_ZETTADEVICE 0xBA
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#define SPIFLASH_MFR_DOUQI 0x54
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#define SPIFLASH_MFR_DOSILICON_NOR 0xF8
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#define SPIFLASH_MFR_PUYA 0x85
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#define SPIFLASH_MFR_XM 0x20
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#define SPIFLASH_MFR_ZBIT 0x5E
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#define SPIFLASH_MFR_FMSH 0xA1
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struct spi_flash_chip;
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struct spi_flash_ops {
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int (*reset)(struct spi_flash_chip *chip);
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int (*read_id)(struct spi_flash_chip *chip, uint8_t *buf);
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int (*read_uid)(struct spi_flash_chip *chip, uint8_t *buf);
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int (*read)(struct spi_flash_chip *chip, int addr, int size, uint8_t *rbuf);
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int (*write)(struct spi_flash_chip *chip, int addr, int size, uint8_t *wbuf);
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int (*erase)(struct spi_flash_chip *chip, uint32_t addr, uint32_t len);
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int (*erase_sector)(struct spi_flash_chip *chip, uint32_t addr); //hsy
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};
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#define ONFI_CRC_BASE 0x4F4E
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/**
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* struct spi_flash_chip - SPI-NAND Private Flash Chip Data
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* @name: name of the chip
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* @spi: [INTERN] point to spi device structure
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* @mfr_id: [BOARDSPECIFIC] manufacture id
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* @dev_id: [BOARDSPECIFIC] device id
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* @read_cache_op: [REPLACEABLE] Opcode of read from cache
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* @write_cache_op: [REPLACEABLE] Opcode of program load
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* @write_cache_rdm_op: [REPLACEABLE] Opcode of program load random
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* @oobbuf: [INTERN] buffer for read/write oob
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* @size: [INTERN] the size of chip
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* @block_size: [INTERN] the size of eraseblock
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* @page_size: [INTERN] the size of page
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* @oob_size: [INTERN] the size of page oob size
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* @block_shift: [INTERN] number of address bits in a eraseblock
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* @page_shift: [INTERN] number of address bits in a page (column
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* address bits).
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* @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
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* @options: [BOARDSPECIFIC] various chip options. They can partly
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* be set to inform nand_scan about special functionality.
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* @ecc_strength: [INTERN] ECC correctability
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* @refresh_threshold: [INTERN] Bitflip threshold to return -EUCLEAN
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* @ecclayout: [BOARDSPECIFIC] ECC layout control structure
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* See the defines for further explanation.
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* @onfi_params: [INTERN] holds the ONFI page parameter
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*/
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struct spi_flash_chip {
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char *name;
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struct spi_flash_cmd_cfg *table;
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struct spi_flash_ops *ops;
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struct qspi_host *host;
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uint8_t cs;
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uint8_t mfr_id;
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uint16_t dev_id;
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uint32_t tx_max_len;
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uint8_t read_op;
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uint8_t read_cache_op;
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uint8_t write_op;
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uint8_t write_cache_op;
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uint8_t write_cache_rdm_op;
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uint8_t en_addr_4byte;
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uint8_t qpi_enabled;
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uint8_t qpi_dummy;
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uint8_t *oobbuf;
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uint64_t size;
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uint32_t block_size;
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uint16_t page_size;
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uint16_t oob_size;
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uint8_t lun_shift;
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uint8_t block_shift;
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uint8_t page_shift;
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uint16_t page_mask;
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uint32_t options;
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uint32_t ecc_strength;
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uint8_t refresh_threshold;
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uint8_t lun;
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uint32_t max_mhz;
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uint8_t enable_sw_xip;
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//struct nand_ecclayout *ecclayout;
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};
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#define SPINAND_MAX_ADDR_LEN 4
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enum {
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CMD_W_NO_DATA = 0,
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CMD_W_RX_DATA = 1,
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CMD_W_TX_DATA = 2
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};
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struct spi_flash_cmd_cfg {
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uint8_t opcode;
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uint8_t addr_bytes;
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uint8_t addr_pins;
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uint8_t mode_bits;
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uint8_t mode_pins;
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uint8_t dummy_cycles;
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uint8_t dummy_pins;
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uint8_t data_pins;
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char seq_id;
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char type;
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};
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#define SPI_CMD_ENTRY(_opcode,_addr_bytes,_addr_pins,_mode_bits, \
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_mode_pins,_dummy_cycles,_dummy_pins,_data_pins, \
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_seq_id, _type) \
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{ \
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.opcode = _opcode, \
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.addr_bytes = _addr_bytes, \
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.addr_pins = _addr_pins, \
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.mode_bits = _mode_bits, \
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.mode_pins = _mode_pins, \
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.dummy_cycles = _dummy_cycles, \
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.dummy_pins = _dummy_pins, \
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.data_pins = _data_pins, \
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.seq_id = _seq_id, \
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.type = _type, \
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}
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struct test_config
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{
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int rx_mode;
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int tx_mode;
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int pattern;
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int len;
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};
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#define QSPI_TEST_ITEM(_rx_mode, _tx_mode, _pattern, _len) \
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{ \
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.rx_mode = _rx_mode, \
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.tx_mode = _tx_mode, \
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.pattern = _pattern, \
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.len = _len, \
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}
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enum {
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RST_AHB_DOMAIN = 1,
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SW_PROG_ERASE = 2
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};
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struct spi_flash_cmd {
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struct spi_flash_cmd_cfg *cmd_cfg;
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uint8_t n_addr; /* Number of address */
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uint8_t addr[SPINAND_MAX_ADDR_LEN]; /* Reg Offset */
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uint32_t n_tx; /* Number of tx bytes */
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const uint8_t *tx_buf; /* Tx buf */
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uint32_t n_rx; /* Number of rx bytes */
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uint8_t *rx_buf; /* Rx buf */
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uint8_t mode;
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uint8_t flag;
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};
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/* feature registers */
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#define REG_BLOCK_LOCK 0xa0
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#define REG_CFG 0xb0
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#define REG_STATUS 0xc0
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#define REG_DIE_SELECT 0xd0
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/* status */
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#define STATUS_OIP_MASK 0x01
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#define STATUS_CRBSY_MASK 0x80
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#define STATUS_READY (0 << 0)
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#define STATUS_BUSY (1 << 0)
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#define STATUS_E_FAIL_MASK 0x04
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#define STATUS_E_FAIL (1 << 2)
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#define STATUS_P_FAIL_MASK 0x08
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#define STATUS_P_FAIL (1 << 3)
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enum {
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NORMAL_MODE,
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OTP_MODE,
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OTP_PROTECT_MODE,
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SNOR_READ_ENABLE_MODE
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};
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struct qspi_mode
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{
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int mode;
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char *name;
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};
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/* Ability of SPI Controllers */
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#define SPI_OPM_RX_QUAD 1 << 2 /* Support 4 pin RX */
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#define SPI_OPM_RX_DUAL 1 << 1 /* Support 2 pin RX */
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#define SPI_OPM_RX 1 << 0 /* Support 1 pin RX */
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#define SPI_OPM_TX_QUAD 1 << 2 /* Support 4 pin TX */
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#define SPI_OPM_TX 1 << 0 /* Support 1 pin TX */
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extern struct qspi_mode qspi_tx_mode[];
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extern struct qspi_mode qspi_rx_mode[];
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char *qspi_tx_mode_name(int mode);
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char *qspi_rx_mode_name(int mode);
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#endif
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