Initial import of NFC GNSS SDK project
This commit is contained in:
chenjintao
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#include <stdio.h>
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#include <string.h>
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#include <stdbool.h>
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#include "psram.h"
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#include "pmic.h"
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#include "cpu.h"
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#include "secureboot.h"
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#include "aboot.h"
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#include "reg.h"
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#include "smux.h"
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#include "property.h"
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#include "efuse.h"
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#include "syscall-arom.h"
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#include "pmu.h"
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#if defined(CPU_MODEL_CRANE)
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#include "freq.h"
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#include "mpu.h"
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#endif
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#define NOT_MCU_CR5 ((AROM_VERSION != AROM_VER_2022_08_08_CRANEW_CR5))
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#define SUPPORT_DDR_MEMORY (AROM_VERSION == AROM_VER_2022_11_11_CRANEG_CR5)
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#define SUPPORT_PSRAM_MEMORY (AROM_VERSION != AROM_VER_2022_11_11_CRANEG_CR5 && \
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AROM_VERSION != AROM_VER_2024_04_30_LAPWING_CR5 && \
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AROM_VERSION != AROM_VER_2022_08_08_CRANEW_CR5)
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#if SUPPORT_DDR_MEMORY
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#include "ddr.h"
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#endif
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#include "log.h"
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#define LOG_MODULE "Preboot"
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#define LOG_LEVEL LOG_LEVEL_MAIN
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/*---------------------------------------------------------------------------*/
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#define SUPPORT_BOOT_GO_TO_PRODUCTION 0
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/*---------------------------------------------------------------------------*/
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#if defined(CPU_MODEL_CRANE)
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extern char __lzma_decode_start, __lzma_decode_size;
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#endif
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/*---------------------------------------------------------------------------*/
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#define UMTI_BASE 0xD4207000
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#define USB_PHY_REG_04 0x10
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#define USB_PHY_REG_25 0x94
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#define USB_PHY_REG_28 0xA0
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#define USB_PHY_REG_29 0xA4
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#define HS_ISEL_MASK (0x3 << 12)
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#define HS_ISEL (0x3 << 12)
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/*---------------------------------------------------------------------------*/
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#define QUECTEL_PREBOOT_OPT
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#ifdef QUECTEL_PREBOOT_OPT
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#include "i2c.h"
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static int Quec_PMIC_GET_PWEKY_STATUS(void)
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{
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uint8_t reg_val;
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pi2c_read_reg(0x01, ®_val);
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if(reg_val & (0x01<<1))
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{
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return 1;
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}
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else
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{
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return 0;
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}
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return 0;
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}
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static int Quec_PowerOnCheck(void)
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{
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unsigned int i=0;
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//uart_printf("[Quec][PWK]OnkeyPowerOnCheck\r\n");
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/* Set 15s for power-down-by-long-ONKEY-pressing period, this register is
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restricted to change only one bit each time. */
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pi2c_init(PMIC_BASE_PAGE_ADDR);
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#if (AROM_VERSION == AROM_VER_2022_11_06_CRANEL_CR5)
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for(i=0;i<80;i++) // 1602ƽ̨ 520ms+100ms(run here need 270ms )= 620ms for powerkey check.
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#elif (AROM_VERSION == AROM_VER_2020_07_30_CRANEGM_A0)
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for(i=0;i<20;i++)
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#else
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for(i=0;i<5;i++) // 1606ƽ̨ 520ms+100ms(run here need 270ms )= 620ms for powerkey check.
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#endif
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{
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if (!Quec_PMIC_GET_PWEKY_STATUS())
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{
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LOG_PRINT("short press, do poweroff!!\r\n");
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clock_wait_ms(10); /* 100 ms */
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return 1; //Power down if ONKEY is not pressed long enough.
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}
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clock_wait_ms(1); /* 5 ms */
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}
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LOG_PRINT("long press, do poweron!!\r\n");
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return 0;
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}
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void quec_powerkey_check(void)
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{
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unsigned char power_up_flag = 0xff, i = 0;
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unsigned char val;
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int pmic_reset_retry = 3;
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unsigned char reg[10] = {0};
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while(pmic_reset_retry--) {
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pi2c_bus_reset();
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pi2c_reset();
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pi2c_init(PMIC_BASE_PAGE_ADDR);
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if(pi2c_read_reg(PMIC_ID, &val) == 0) {
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break;
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}
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}
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pi2c_read_reg(0x01, ®[0]);//status
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pi2c_read_reg(0x10, ®[1]);
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pi2c_read_reg(0xe5, ®[2]);
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pi2c_read_reg(0xe6, ®[3]);
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pi2c_read_reg(0xe2, ®[4]);
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pi2c_read_reg(0xeb, ®[5]);
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LOG_PRINT("PMIC REG:0x01,0x10,0xe5,0xe6,0xe2,0xeb\r\n");
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LOG_PRINT("PMIC VAL:0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x\r\n",reg[0],reg[1],reg[2],reg[3],reg[4],reg[5]);
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if(smux_running_mode_get() == SMUX_MODE_NORMAL)
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{
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power_up_flag = 0x01; // hot power on
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LOG_PRINT("download mode, do power on\n");
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}
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else
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{
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if (PMIC_PID(val) == PM802)
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{
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pi2c_read_reg(0x10, ®[0]); //read power up log
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pi2c_read_reg(0xf0, ®[1]); //read xo reg
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pi2c_read_reg(0x01, ®[2]); //read exton1n status
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if((reg[1] & 0xf0) == 0x0) //cold power up
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{
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if((reg[0] == 0x0) && ((reg[2] & 0x02) == 0)) // unkown wakeup source && pwrkey is not pressed
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{
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LOG_PRINT("unkown wakeup:%d, do power off!!!\n",reg[0]);
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pi2c_write_reg(0xe2, 0xf0); //set discharger timer to 0S //default 2S
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pi2c_read_reg(0xe7, ®[0]);
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pi2c_write_reg(0xe7, (reg[0] & 0xfb)); //disalbe fault wakeup
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pi2c_read_reg(0x0d, ®[0]);
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pi2c_write_reg(0x0d, (reg[0])|0x20) ;
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return;
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}
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}
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pi2c_write_reg(0xe2, 0xf1); //set discharger timer back to 1S
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}
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if( 0 == (reg[5]&0x80))
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{
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power_up_flag = 0x00; // cold power on
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LOG_PRINT("cold power on\n");
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}
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else
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{
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power_up_flag = 0x01; // hot power on
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LOG_PRINT("hot power on\n");
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}
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if(0x00 == power_up_flag) // cold power on
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{
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if(Quec_PowerOnCheck())
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{
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LOG_PRINT("warning: powkey too short !!!!!\r\n");
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//quec_pmic_sw_pdown();
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pmic_sw_pdown();
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return;
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}
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//save hot flag
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pi2c_write_reg(0xeb, (reg[5] | 0x80));
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}
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}
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for(i = 0;i < 10; i++)
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{
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if(reg[i] == 0x0)
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{
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reg[i] = 0xFF;
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}
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}
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reg[9] = 0x0;
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asr_property_set("power_down_reg", (const char*)(reg));
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}
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#endif
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void
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usb_phy_config(void)
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{
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unsigned val;
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unsigned chip_id;
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chip_id = hw_chip_id();
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if(chip_id == CHIP_ID_CRANE) {
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/* driver strength */
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val = (unsigned)readl(UMTI_BASE + USB_PHY_REG_28);
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writel((val & ~HS_ISEL_MASK) | HS_ISEL, UMTI_BASE + USB_PHY_REG_28);
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LOG_PRINT("Usb phy reg 28 0x%x -> 0x%lx\n", val, readl(UMTI_BASE + USB_PHY_REG_28));
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} else if((CHIP_ID_CRANEG == chip_id) || (CHIP_ID_CRANEM == chip_id)) {
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val = (unsigned)readl(UMTI_BASE + USB_PHY_REG_29);
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writel((val & ~0x1F) | 0x1B, UMTI_BASE + USB_PHY_REG_29);
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LOG_PRINT("Usb phy reg 29 0x%x -> 0x%lx\n", val, readl(UMTI_BASE + USB_PHY_REG_29));
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val = (unsigned)readl(UMTI_BASE + USB_PHY_REG_25);
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writel(val | (BIT7), UMTI_BASE + USB_PHY_REG_25);
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val = (unsigned)readl(UMTI_BASE + USB_PHY_REG_04);
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writel(val | (BIT4 | BIT5 | BIT6), UMTI_BASE + USB_PHY_REG_04);
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}
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}
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/*---------------------------------------------------------------------------*/
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#if defined(CPU_MODEL_CRANE) && (AROM_VERSION != AROM_VER_2024_04_30_LAPWING_CR5)
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static void
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psram_mpu_config(void)
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{
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#if SUPPORT_DDR_MEMORY
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extern char __ddr_base;
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unsigned base = (unsigned)&__ddr_base;
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unsigned size = get_ddr_size();
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#else
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extern char __psram_base;
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unsigned base = (unsigned)&__psram_base;
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unsigned size = get_psram_size();
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#endif
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mpu_region_config(ATCM_CODE_REGION_NUM, 0x0, 0x10000, MPU_ATTR_RWX);
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mpu_region_config(PSRAM_DDR_REGION_NUM_RWX, base, size, MPU_ATTR_RWX);
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mpu_region_config(PSRAM_DDR_REGION_NUM_NONE, 0x0, 0x80000000, MPU_ATTR_NONE);
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/* These used memory(>= 0x8000_0000) should be configurated to MPU normal,
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* if not configurated in bootrom for Cortex R5.
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*/
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#if (AROM_VERSION == AROM_VER_2020_07_30_CRANEGM_A0 || \
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AROM_VERSION == AROM_VER_2022_11_06_CRANEL_CR5)
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extern char __aram_ctext_start, __aram_ctext_size;
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mpu_region_config(L2SRAM_REGION_NUM, &__aram_ctext_start, &__aram_ctext_size, MPU_ATTR_RWX);
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#endif
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}
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#endif
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#if NOT_MCU_CR5
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static int
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pmic_config(void)
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{
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if(hw_platform_type() != HW_PLATFORM_TYPE_SILICON) {
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return 0;
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}
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pmic_setup();
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uint8_t powerup_reason = pmic_powerup_get_reason();
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LOG_PRINT("Power_up_reason=0x%x.\n", powerup_reason);
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pmic_fault_wu_en_disable();
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uint8_t pmic_id = pmic_get_id();
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/* PM803 is different with others */
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uint8_t invalid_bits = (pmic_id == PM803) ? PM803_INVALID_STATE :
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PM813_INVALID_STATE;
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if(powerup_reason & invalid_bits) {
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LOG_WARN("Warning: power_up_reason=0x%x is abnormal.\n", powerup_reason);
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/* pmic_sw_pdown(); */
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/* return 0; */
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}
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switch(pmic_id) {
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case PM802:
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case PM802S:
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/* workaround for PM802, if power up log = 0 or 8(bat_wu_log), pmic power down. PM813 no this hardware bug. */
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if(0 == powerup_reason || 8 == powerup_reason) {
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LOG_WARN("Warning: power_up_reason = 0 or 8(bat_wu_log). need pmic power down\n");
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pmic_sw_pdown();
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/* never reach here. */
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}
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break;
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case PM813L:
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/* pmic813L A0's bug: onkey reason cannot set bit in powerup_reason, So add workaround */
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break;
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default:
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break;
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}
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return 0;
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}
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#endif
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/*---------------------------------------------------------------------------*/
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int
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main(void)
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{
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/*read or write geu, must enable clk at first, else, geu bank dump always be 0. */
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#if (AROM_VERSION != AROM_VER_2022_08_08_CRANEW_CR5)
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/* watch1 cr5 does not require the use of the GEU module. */
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geu_clk_enable();
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#endif
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#if defined(CPU_MODEL_CRANE)
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cr5_axi_set_max_freq();
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#endif
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LOG_PRINT("Executing preboot application...\n");
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LOG_PRINT("Preboot version: %s\n", BOOTLOADER_VERSION);
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/* force init prop 1K space: 0XB0020C00~ 0xB0021000 */
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asr_property_area_init(1);
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asr_property_set("bl2.preboot.ver", BOOTLOADER_VERSION);
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#if defined(CPU_MODEL_CRANE) || defined(CPU_MODEL_CRANEW_MCU)
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#if NOT_MCU_CR5
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/* arom-crane alread print log, this is only for set prop */
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if(!fuse_trust_boot_enabled()) {
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/*LOG_PRINT("### Non-trusted boot mode. ###\n"); */
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asr_property_set("bl1.secureboot", "0");
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} else {
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/*LOG_PRINT("### Trusted boot mode. ###\n"); */
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asr_property_set("bl1.secureboot", "1");
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}
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#else
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/*LOG_PRINT("### Non-trusted boot mode. ###\n"); */
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asr_property_set("bl1.secureboot", "0");
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#endif
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#if NOT_MCU_CR5
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/*
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* "halt": When download completed, if usb pull out, board powerdown. defaultly it is "halt",
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* "reboot": some customer want to reboot instead of powerdown, so customer set it to "reboot" manually.
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* "noaction": if vbus is unconnected, usb_connect() is 0.
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* need set "noaction" to workaround the bug:
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* After download, flasher judges that it is usb pulled out, enter forcedown by mistake.
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*/
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asr_property_set("bl2.usb_disconnect", "halt");
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/* enter production mode after go(boot continue) if bl2.go_production is true */
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#if SUPPORT_BOOT_GO_TO_PRODUCTION
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asr_property_set(PROP_NAME_GO_PRODUCTION, "true");
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#endif
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usb_phy_config();
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fuse_read_lotid();
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//Move it to pmic_setuppmic_setup(void),after i2c initialization
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//#ifdef QUECTEL_PREBOOT_OPT
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// quec_powerkey_check();
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//#endif
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pmic_config();
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#endif
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#endif
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#if AROM_VERSION == AROM_VER_2022_07_28_WATCH1
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if(efuse_modem_type_is_radio()) {
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asr_property_set("cp.modem.type", "MODEM_RADIO");
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} else {
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asr_property_set("cp.modem.type", "MODEM_ZERO");
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}
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#endif
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#if (SUPPORT_DDR_MEMORY)
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unsigned chip_id = hw_chip_id();
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if(chip_id == CHIP_ID_CRANEGT) {
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ddr_init();
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}
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#endif
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#if (SUPPORT_PSRAM_MEMORY)
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psram_init();
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#endif
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#if AROM_VERSION == AROM_VER_2022_08_08_CRANEW_CR5
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/*
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* Watch1 cr5 psram is initialized in Harmony, and initialization is no longer repeated in
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* bootloader, mcu will write cr5 psram type to SW_SCRATCH(0xD4282CE8) register bit[15:8]
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* in Harmony, so cr5 read SW_SCRATCH bit[15:8] to get psram type here.
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*/
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char psram_type_str[PROP_VALUE_MAX] = "";
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extern void psram_type_name_get_by_sw_scratch(char *psram_type_str, size_t size);
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psram_type_name_get_by_sw_scratch(psram_type_str, sizeof(psram_type_str));
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asr_property_set("fuse.psram.type", psram_type_str);
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#endif
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#if defined(CPU_MODEL_CRANE)
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#if (AROM_VERSION != AROM_VER_2024_04_30_LAPWING_CR5)
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psram_mpu_config();
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#endif
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/*
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* Atcm 64K is not enough to parse bootloder volume, so update to psram.
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*/
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LOG_INFO("Set fip image load address spaces to 0x%x\n",
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(unsigned)&__lzma_decode_start);
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sb_fip_image_setup((void *)&__lzma_decode_start, (unsigned)&__lzma_decode_size);
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#endif
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#if (AROM_VERSION == AROM_VER_2022_08_08_CRANEW_CR5)
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uint32_t val = readl(CIU_BASE + SW_SCRATCH);
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val = (val & ~FLAGS_RUNNING_STAGE_MASK) | FLAGS_RUNNING_STAGE_PREBOOT_COMPLETE;
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writel(val, CIU_BASE + SW_SCRATCH);
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LOG_INFO("Set running stage: [0x%x] = 0x%x.\n", (CIU_BASE + SW_SCRATCH), (unsigned)readl(CIU_BASE + SW_SCRATCH));
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#endif
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return 0;
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}
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/*---------------------------------------------------------------------------*/
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