Initial import of NFC GNSS SDK project

2026-09-15 16:10:12 +08:00
commit 2746cc3d4e
3070 changed files with 892062 additions and 0 deletions
@@ -0,0 +1,5 @@
+MODULE = board
+
+DIRS += $(RIOTBOARD)/libarom-common libarom
+
+include $(RIOTBASE)/Makefile.base
@@ -0,0 +1 @@
+USEMODULE += dbg-io
@@ -0,0 +1 @@
+
@@ -0,0 +1,12 @@
+export CPU = crane
+
+export OFLAGS = -O binary
+export HEXFILE = $(ELFFILE:.elf=.bin)
+USEMODULE += libarom-common
+
+export INCLUDES += -I$(RIOTBOARD)/crane/libarom/include
+export INCLUDES += -I$(RIOTBOARD)/crane/sb_auth
+include $(RIOTBOARD)/libarom-common/Makefile.include
+
+export CFLAGS += -DPROJECT_CONF_PATH=\"project-conf.h\"
+export BASELIBS += $(RIOTBOARD)/crane/libarom/libarom-$(BOARD)-$(APPLICATION)-$(AROM_VERSION).a
@@ -0,0 +1,11 @@
+#ifndef PROJECT_CONFIG_H
+#define PROJECT_CONFIG_H
+
+#include "clk-drv.h"
+
+#define SZALLOC_OFFSET              0x1000
+#define QSPI_CLOCK_LOW              QSPI_CLOCK_52MHZ
+#define QSPI_CLOCK_HIGH             QSPI_CLOCK_104MHZ
+#define SUPPORT_LZMA_SPARSE         1
+
+#endif /* PROJECT_CONFIG_H */
@@ -0,0 +1,6 @@
+MODULE = libarom
+
+CFLAGS += -D_GNU_SOURCE
+CFLAGS += -Wno-int-conversion
+
+include $(RIOTBASE)/Makefile.base
@@ -0,0 +1,29 @@
+#ifndef _CLK_DRV_H_
+#define _CLK_DRV_H_
+
+#include "syscall-arom.h"
+
+/*
+ * QSPI clock freqency definitions
+ */
+ #if 0
+/* cr5 z1 diff with other cranes */
+#define QSPI_CLOCK_13MHZ_CR5_Z1    0
+#define QSPI_CLOCK_26MHZ_CR5_Z1    1
+#define QSPI_CLOCK_48MHZ_CR5_Z1    2
+#define QSPI_CLOCK_52MHZ_CR5_Z1    3
+#define QSPI_CLOCK_78MHZ_CR5_Z1    4
+#define QSPI_CLOCK_104MHZ_CR5_Z1   5
+#endif
+/*              freq           0     1     2     3     4     5    6     7
+ * Z1 new map:  clock[8]   = { 13,   13,   13,  26,   48,   52,   78,  104 };
+ * Z2:          clock[8]   = { 13,   13,   13,  26,   39,   52,   78,  104 };
+ */
+#define QSPI_CLOCK_13MHZ    1
+#define QSPI_CLOCK_26MHZ    3
+#define QSPI_CLOCK_39MHZ    4
+#define QSPI_CLOCK_52MHZ    5
+#define QSPI_CLOCK_78MHZ    6
+#define QSPI_CLOCK_104MHZ   7
+
+#endif
@@ -0,0 +1,230 @@
+#ifndef _CPU_H_
+#define _CPU_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include "syscall-arom.h"
+
+#define CRANE_MFPR_BASE                      0xD401E000
+#define M_ICU_BASE                           0xD4282000
+#define PMU_BASE                             0xD4282800
+#define PMU_MAIN_BASE                        0xD4050000
+#define QSPI_IPB_BASE                        0xD420B000
+#define DMA_BASE                             0xD4000000
+#define CIU_BASE                             0xD4282C00
+#define QSPI_AMBA_BASE                       0x80000000
+#define UTMI_BASE                            0xD4207000
+
+/* apb clock */
+#define APBC_BASE                            0xD4015000
+#define APBC_TWSI0_CLK_RST                   0x2C /* CI2C 0 */
+#define APBC_TWSI1_CLK_RST                   0x60 /* CI2C 1 */
+#define APBC_TWSI2_CLK_RST                   0x78 /* PI2C */
+#define APBC_TWSI3_CLK_RST                   0x7C /* CI2C 2 */
+
+/* timer */
+#define CRANE_APB_TIMER0_BASE                0xD4014000
+#define TIMER_BASE                           CRANE_APB_TIMER0_BASE
+#define TIMER_MAX_DEV_NUM                    3   /* counter */
+#define TIMER_MAX_CHAN_NUM                   3   /* match */
+#define TIMER_DEV0_IRQ                       13
+#define TIMER_DEV1_IRQ                       14
+#define TIMER_DEV2_IRQ                       14
+
+/* uart */
+#define UART0_BASE                           0xD4017000
+#define UART1_BASE                           0xD4018000
+#define UART_IER                             0x4
+#define IER_TIE                              (1 << 1)
+#define UART0_IRQ                            27
+#define UART1_IRQ                            59
+#define HAS_UART_1                           1
+#define APBC_CLK_FPGA                        13000000
+#define APBC_CLK_VDK                         24000000
+
+/* usb */
+#define CRANE_USB_BASE                       0xD4208000
+#define USB_IRQ_NUM                          44
+/* usb clk/reset reg 0x5C */
+#define PMU_USB_CLK_RES_CTRL                 (PMU_BASE + 0x5c)
+#define USB_AXI_CLK_EN                       (1 << 3)
+#define USB_DONGLE_CLK_GATE_MASK             (1 << 1)
+#define USB_AXI_RESET                        (1 << 0)
+/* USB phy */
+#define UTMI_USB2_REG0A                      0x28
+#define UTMI_USB2_REG0B                      0x2C
+#define UTMI_USB2_REG0D                      0x34
+#define UTMI_USB2_REG25                      0x94
+#define UTMI_USB2_REG26                      0x98
+#define UTMI_USB2_REG28                      0xA0
+#define UTMI_USB2_REG29                      0xA4
+
+/* TWSI */
+#define TWSI0_BASE 0xD4011000
+#define TWSI1_BASE 0xD4010800
+#define TWSI2_BASE 0xD4037000
+#define TWSI3_BASE 0xD403E000
+
+/* GEU */
+/*------------------------------------------------------------------------------------*/
+#if (AROM_VERSION == AROM_VER_2022_08_08_CRANEW_CR5)
+#define GEU_BASE                             0x40002000 /* cranew CR5, share use the geu of MCU */
+#define FUSEREG_BASE                         0x40002500 /* bank4 ~7 */
+
+/* GEU clock enable */
+/* MCU AON */
+#define MCU_AON_BASE                         0x41000000
+/* CraneW Cr5 using this register to enable/disable GEU clock */
+#define MCU_SYS_PMU_CTRL                     (MCU_AON_BASE + 0x0)
+#define AEU_CG_EN                            (1 << 18)
+/*------------------------------------------------------------------------------------*/
+#else /* not cranew cr5 */
+/*------------------------------------------------------------------------------------*/
+#define GEU_BASE                             0xD4201000 /* crane, craneG, craneM, craneL */
+
+/* GEU clock enable */
+#define PMU_AES_CLK_RES_CTRL                 (PMU_BASE + 0x68) /* AES Clock/Reset Control Register */
+
+/* PMU_AES_CLK_RES_CTRL */
+typedef union {
+  struct {
+    unsigned aes_axi_reset                  : 1;      /* bit 0 */
+    unsigned reserved0                      : 2;      /* bit 2:1 */
+    unsigned aes_axi_clk_en                 : 1;      /* bit 3 */
+    unsigned reserved1                      : 28;     /* bit 31:4 */
+  } s;
+  unsigned value;
+} pmu_aes_clk_res_ctrl_t;
+/*------------------------------------------------------------------------------------*/
+#endif
+/*------------------------------------------------------------------------------------*/
+/* PMU AP */
+#define PMU_MAIN                             0xD4050000
+#define ACGR                                 (PMU_MAIN + 0x1024) /* Marvell Seagull/Mohawk Clock Gating Register */
+#define APMU_104M_BIT                        12 /* bit12 */
+
+#define APB_SPARE_BASE                       0xD4090000
+#define APB_SPARE12_REG                      (APB_SPARE_BASE + 0x12C)
+/*------------------------------------------------------------------------------------*/
+#if (AROM_VERSION == AROM_VER_2022_08_08_CRANEW_CR5)
+/* CIU */
+/*
+   CR5 reg
+   sw use it to store user data
+   bit[3:0]: booting mode
+   bit[7:4]: running stage
+   bit[15:8]: cr5 psram type
+ */
+#define SW_SCRATCH                           0xE8
+/* booting mode */
+#define FLAGS_NORMAL_MODE                    0x0
+#define FLAGS_FORCE_DOWNLOAD                 (1 << 0)
+#define FLAGS_PRODUCTION_MODE                (1 << 1)
+#define FLAGS_BOOTING_MODE_MASK              0xF
+#define FLAGS_BOOTING_MODE(x)                ((x) & FLAGS_BOOTING_MODE_MASK)
+/* cr5 running stage */
+#define FLAGS_RUNNING_STAGE_AROM_START       (0 << 4)   /* mcu -> cr5 */
+#define FLAGS_RUNNING_STAGE_PREBOOT_COMPLETE (1 << 4)   /* cr5 -> mcu */
+#define FLAGS_RUNNING_STAGE_FLASHER_COMPLETE (2 << 4)   /* cr5 -> mcu */
+#define FLAGS_RUNNING_STAGE_BOOT_CONTINUE    (3 << 4)   /* mcu -> cr5 */
+#define FLAGS_RUNNING_STAGE_MASK             (0xF << 4)
+#define FLAGS_RUNNING_STAGE(x)               ((x) & FLAGS_RUNNING_STAGE_MASK)
+/* cr5 psram type */
+#define FLAGS_PSRAM_TYPE_MASK                (0xFF << 8)
+#define FLAGS_PSRAM_TYPE_SET(val, type)      ((val & ~FLAGS_PSRAM_TYPE_MASK) | (((type) << 8) & FLAGS_PSRAM_TYPE_MASK))
+#define FLAGS_PSRAM_TYPE_GET(val)            (((val) & FLAGS_PSRAM_TYPE_MASK) >> 8)
+
+#define SW_BRANCH_ADDR                       0x24
+/* reserved reg for sw defined */
+//#define SW_DEBUG_REG0                        0x1C0
+//#define SW_DEBUG_REG1                        0x1C4
+//#define SW_DEBUG_REG2                        0x1C8
+#endif
+
+/* sd host controller 1 base address */
+#define EMMC_BASE_ADDR                       0xD4280000
+#define CP_TOP_SDH0_CLK_CTRL                 (PMU_BASE + 0x54)  /*sd or sdio */
+#define CP_TOP_SDH1_CLK_CTRL                 (PMU_BASE + 0x58)  /*emmc */
+
+/* chip id */
+#define CHIP_ID(x)                           ((x) & 0xFFFF)
+#define REV_ID(x)                            (((x) >> 16) & 0xFF)
+
+#define CHIP_ID_CRANE                        (0x6731)
+#define CHIP_ID_CRANEG                       (0x3603) /*craneG A0*/
+#define CHIP_ID_CRANEM                       (0x1603) /*craneM A0*/
+#define CHIP_ID_CRANEL                       (0x1606)
+#define CHIP_ID_CRANELS                      (0x1609)
+#define CHIP_ID_CRANEW                       (0x3606)
+#define CHIP_ID_WATCH_TWO                    (0x3661)
+#define CHIP_ID_CRANELR                      (0x1602)
+#define CHIP_ID_CRANEGT                      (0x3605)
+#define CHIP_ID_CRANEGD                      (0x3611)
+#define CHIP_ID_CRANELG                      (0x1607)
+#define CHIP_ID_CRANELRH                     (0x1605)
+#define CHIP_ID_CRANELB                      (0x3608)
+#define CHIP_ID_LAPWING                      (0x1903)
+#define CHIP_ID_WATCH1                       (0x3660)
+
+#define REV_ID_CRANEGT_Z1                    (0xF0)
+#define REV_ID_CRANEGT_A0                    (0xA0)
+#define REV_ID_CRANEGT_A1                    (0xA1)
+#define REV_ID_CRANEW_Z2                     (0xC0)
+#define REV_ID_WATCH_TWO_Z1                  (0xF0)
+#define REV_ID_WATCH1_Z1                     (0xF0)
+#define REV_ID_WATCH1_A0                     (0xA0)
+
+#define HW_PLATFORM_TYPE_SILICON             0
+#define HW_PLATFORM_TYPE_FPGA                1
+#define HW_PLATFORM_TYPE_ZEBU_Z1             2
+#define HW_PLATFORM_TYPE_VDK                 3
+
+/* MFP */
+#define MFP_GPIO_4                           (0xEC)
+#define MFP_GPIO_5                           (0xF0)
+#define MFP_GPIO_6                           (0xF4)
+#define MFP_GPIO_7                           (0xF8)
+
+#define MFP_GPIO_12                          (0x10C)
+#define MFP_GPIO_13                          (0x110)
+#define MFP_GPIO_14                          (0x114)
+#define MFP_GPIO_15                          (0x118)
+
+#define MFP_GPIO_16                          (0x11C)
+#define MFP_GPIO_17                          (0x120)
+#define MFP_GPIO_18                          (0x124)
+#define MFP_GPIO_19                          (0x128)
+
+#define MFP_GPIO_33                          (0x160)
+#define MFP_GPIO_34                          (0x164)
+#define MFP_GPIO_35                          (0x168)
+#define MFP_GPIO_36                          (0x16C)
+
+#define MFP_GPIO_55                          (0xC8)
+
+#define MFP_GPIO_61                          (0x308)
+#define MFP_GPIO_62                          (0x30C)
+#define MFP_GPIO_63                          (0x310)
+#define MFP_GPIO_64                          (0x314)
+
+/* CraneG has different offset with other chips */
+#define MFP_GPIO_71                          (0x1BC)
+#define MFP_GPIO_72                          (0x1C0)
+#define MFP_GPIO_73                          (0x1C4)
+#define MFP_GPIO_74                          (0x1C8)
+
+#define QSPI_DAT3_MPFI                       (0x2C4)
+#define QSPI_DAT2_MPFI                       (0x2C8)
+#define QSPI_DAT1_MPFI                       (0x2CC)
+#define QSPI_DAT0_MPFI                       (0x2D0)
+#define QSPI_CLK_MPFI                        (0x2D4)
+#define QSPI_CS1_MPFI                        (0x2D8)
+#define QSPI_CS2_MPFI                        (0x2DC)
+#define QSPI_DQM_MPFI                        (0x2E0)
+
+unsigned int hw_platform_type(void);
+unsigned int hw_chip_id(void);
+unsigned int hw_rev_id(void);
+void uart_rx_fixup(void);
+
+#endif /* _CPU_H_ */
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2020, ASR microelectronics
+ * All rights reserved.
+ */
+
+#ifndef CRANE_DEF_H_
+#define CRANE_DEF_H_
+
+#define SPI_CONF_CONTROLLER_COUNT 3
+#define SPI_DMA_ENABLE  1
+
+#endif /*CRANE_DEF_H_*/
@@ -0,0 +1,78 @@
+#ifndef _DMA_H_
+#define _DMA_H_
+
+#include "dma_common.h"
+#include "cpu.h"
+
+/*
+ * DMA register address offset definitions
+ */
+#define DMA_CSR0_31         0x0
+#define DMA_ALGN            0xA0
+#define DMA_PCSR            0xA4
+#define DMA_RQSR0           0xE0
+#define DMA_RQSR1           0xE4
+#define DMA_RQSR2           0xE8
+#define DMA_INT             0xF0
+#define DMA_RCMR0_63        0x100
+#define DMA_RCMR64_99       0x1100
+#define DMA_DADR0           0x200
+#define DMA_SADR0_31        0x204
+#define DMA_TADR0_31        0x208
+#define DMA_CMD0_31         0x20C
+
+#define DCMD_INCSRCADDR     (1 << 31)   /* Source Address Increment Setting. */
+#define DCMD_INCTRGADDR     (1 << 30)   /* Target Address Increment Setting. */
+#define DCMD_FLOWSRC        (1 << 29)   /* Flow Control by the source. */
+#define DCMD_FLOWTRG        (1 << 28)   /* Flow Control by the target. */
+#define DCMD_STARTIRQEN     (1 << 22)   /* Start Interrupt Enable */
+#define DCMD_ENDIRQEN       (1 << 21)   /* End Interrupt Enable */
+#define DCMD_ENDIAN         (1 << 18)   /* Device Endian-ness. */
+#define DCMD_BURST8         (1 << 16)   /* 8 byte burst */
+#define DCMD_BURST16        (2 << 16)   /* 16 byte burst */
+#define DCMD_BURST32        (3 << 16)   /* 32 byte burst */
+#define DCMD_BURST64        (4 << 16)   /* 64 byte burst */
+#define DCMD_WIDTH1         (1 << 14)   /* 1 byte width */
+#define DCMD_WIDTH2         (2 << 14)   /* 2 byte width (HalfWord) */
+#define DCMD_WIDTH4         (3 << 14)   /* 4 byte width (Word) */
+#define DCMD_LENGTH         0x01fff     /* length mask (max = 8K - 1) */
+
+#define DCSR_RUN            (1 << 31)   /* Run Bit (read / write) */
+#define DCSR_NODESC         (1 << 30)   /* No-Descriptor Fetch (read/write) */
+#define DCSR_STOPIRQEN      (1 << 29)   /* Stop INT Enable (read / write) */
+#define DCSR_REQPEND        (1 << 8)    /* Request Pending (read-only) */
+#define DCSR_STOPSTATE      (1 << 3)    /* Stop State (read-only) */
+#define DCSR_ENDINTR        (1 << 2)    /* End Interrupt (read / write) */
+#define DCSR_STARTINTR      (1 << 1)    /* Start Interrupt (read / write) */
+#define DCSR_BUSERR         (1 << 0)    /* Bus Error Interrupt (read/write) */
+
+#define DRCMR_MAPVLD        (1 << 7)    /* Map Valid (read / write) */
+#define DRCMR_CHLNUM        0x1f        /* mask for Chan Number (read/write) */
+
+#define DCMD_INCSRCADDR_SHIFT       31  /* Source address increment */
+#define DCMD_INCTRGADDR_SHIFT       30  /* Target address increment */
+#define DCMD_FLOWSRC_SHIFT          29  /* Source flow control */
+#define DCMD_FLOWTRG_SHIFT          28  /* Target flow control */
+#define DCMD_MAX_BURST_SIZE_SHIFT   16  /* Max burst size */
+#define DCMD_WIDTH_SHIFT            14  /* Width of the on-chip peripheral */
+
+#define DCSR(ch)        (DMA_BASE + DMA_CSR0_31 + 4 * (ch))
+#define DSADR(ch)       (DMA_BASE + DMA_SADR0_31 + 4 * 4 * (ch))
+#define DTADR(ch)       (DMA_BASE + DMA_TADR0_31 + 4 * 4 * (ch))
+#define DCMD(ch)        (DMA_BASE + DMA_CMD0_31 + 4 * 4 * (ch))
+
+#define DMA_BURST_SIZE_8_BYTE   1
+#define DMA_BURST_SIZE_16_BYTE  2
+#define DMA_BURST_SIZE_32_BYTE  3
+
+#define DMA_DEVICE_ID_AES_TX    69
+#define DMA_DEVICE_ID_AES_RX    68
+#define DMA_DEVICE_ID_QSPI_TX   99
+#define DMA_DEVICE_ID_QSPI_RX   97
+
+#define DMA_CHANNEL_AES_TX      1
+#define DMA_CHANNEL_AES_RX      0
+#define DMA_CHANNEL_QSPI_TX     28
+#define DMA_CHANNEL_QSPI_RX     27
+
+#endif