Initial import of NFC GNSS SDK project

2026-09-15 16:10:12 +08:00
commit 2746cc3d4e
3070 changed files with 892062 additions and 0 deletions
@@ -0,0 +1,37 @@
+#ifndef __FREQ_H__
+#define __FREQ_H__
+
+/* pclk_sel */
+#define CR5_PCLK_SEL_416    0
+#define CR5_PCLK_SEL_312    1
+#define CR5_PCLK_SEL_499    2
+#define CR5_PCLK_SEL_624    3
+#define CR5_PCLK_SEL_832    4
+
+/* pclk_div */
+#define CR5_PCLK_DIV_0      0
+#define CR5_PCLK_DIV_1      1
+#define CR5_PCLK_DIV_2      2
+#define CR5_PCLK_DIV_3      3
+
+void cr5_freq_change(unsigned pclk_sel, unsigned pclk_div);
+
+/* aclk_sel */
+#define AXI_FREQ_156M       0
+#define AXI_FREQ_208M       1
+/*for craneLRH and craneGT A0 */
+#define AXI_FREQ_223M_LRH_GT       0
+/*for craneLS/LR/LG/LB and later chip */
+#define AXI_FREQ_223M              3
+/*for Lapwing */
+#define AXI_FREQ_312M              3
+
+void axi_freq_change(unsigned int aclk_sel);
+
+/* pclk: CR5 clk; aclk AXI clk */
+int get_curr_freq(unsigned *ppclk, unsigned *paclk);
+
+void cr5_axi_set_default_freq(void);
+void cr5_axi_set_max_freq(void);
+
+#endif
@@ -0,0 +1,9 @@
+#ifndef _MFP_DRV_H_
+#define _MFP_DRV_H_
+
+void spi_mfp_config(void);
+void qspi_mfp_config(void);
+void qspi_mfp_config_mx(void);
+int uart_rx_gpio_config(void);
+
+#endif
@@ -0,0 +1,61 @@
+#ifndef _MPU_H_
+#define _MPU_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Region number 0 has the lowest priority.
+ * Region number 15 is reserved for ROM code
+ */
+#define AROM_CODE_REGION_NUM         15 /* For AROM code */
+#define SRAM_CODE_REGION_NUM         14 /* For SRAM code */
+#define SQU_CODE_REGION_NUM          13 /* For SQU code */
+#define SHMEM_CODE_REGION_NUM        12 /* For SHMEM code */
+#define ATCM_CODE_REGION_NUM         11 /* For ATCM code */
+#define PSRAM_DDR_REGION_NUM_RWX     10 /* For PSRAM or DDR RAM */
+#define PSRAM_DDR_REGION_NUM_NONE    9  /* For PSRAM or DDR RAM */
+#define L2SRAM_REGION_NUM            8  /* For L2SRAM */
+#define SYS_APB_GROUP_REGION_NUM     7  /* For MCU SYS AHB/APB periperals */
+#define MAX_USER_REGION_NUM          6
+
+/* The MPU region access control definitions */
+#define MPU_REGION_ACCESS_CTRL_B      (1 << 0)              /* Bufferable */
+#define MPU_REGION_ACCESS_CTRL_C      (1 << 1)              /* Cacheable */
+#define MPU_REGION_ACCESS_CTRL_S      (1 << 2)              /* Shared */
+
+/*
+ * TEX: 0x1, non-cacheable
+ */
+#define MPU_REGION_ACCESS_CTRL_TEX(x) (((x) & 0x7) << 3)    /* Type Extensions */
+/*
+ * AP: 0, Permission fault
+ *     1, Privileged Access only
+ *     2, No user-mode write
+ *     3, Full access
+ */
+#define MPU_REGION_ACCESS_CTRL_AP(x)  (((x) & 0x7) << 8)    /* Access Permissions */
+
+#define MPU_REGION_ACCESS_CTRL_XN     (1 << 12)             /* Execute Never */
+
+#define MPU_ATTR_RWX                  (MPU_REGION_ACCESS_CTRL_AP(3) | \
+                                       MPU_REGION_ACCESS_CTRL_TEX(1))
+
+#define MPU_ATTR_NONE                 (MPU_REGION_ACCESS_CTRL_XN | \
+                                       MPU_REGION_ACCESS_CTRL_AP(0))
+
+/* The MPU region base address should be aligned with the size and the max size is 4GB */
+int mpu_region_config(unsigned num, unsigned base, unsigned size, unsigned acc_ctrl);
+int mpu_enable_max_priority_region(unsigned base, unsigned size, unsigned acc_ctrl);
+void mpu_disable_max_priority_region(void);
+int mpu_get_next_empty_region(void);
+void mpu_disable_all_user_region(void);
+void mpu_disable_user_used_region(void);
+void mpu_clear(unsigned index);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
@@ -0,0 +1,45 @@
+#ifndef _SYSTEM_H_
+#define _SYSTEM_H_
+
+/*---------------------------------------------------------------------------*/
+#define MPU_REGION_ACCESS_CTRL_TEX(x) (((x) & 0x7) << 3)    /* Type Extensions */
+#define MPU_REGION_ACCESS_CTRL_AP(x)  (((x) & 0x7) << 8)    /* Access Permissions */
+/*---------------------------------------------------------------------------*/
+#define isb() __asm__ volatile ("isb" : : : "memory")
+#define dsb() __asm__ volatile ("dsb" : : : "memory")
+/*---------------------------------------------------------------------------*/
+#define SCTLR_M    (1 << 0)     /* Enable the MPU */
+#define SCTLR_A    (1 << 1)     /* Alignment check enable bit */
+#define SCTLR_C    (1 << 2)     /* Cache enable bit */
+#define SCTLR_SW   (1 << 10)    /* SWP/SWPB enable bit */
+#define SCTLR_Z    (1 << 11)    /* Branch prediction enable bit */
+#define SCTLR_I    (1 << 12)    /* Instruction cache enable bit */
+#define SCTLR_V    (1 << 13)    /* Vectors relocated to 0xffff0000 */
+#define SCTLR_RR   (1 << 14)    /* Not on Cortex-R7 processor. Round Robin bit for cache implementation policy */
+#define SCTLR_BR   (1 << 17)    /* Background region bit */
+#define SCTLR_DZ   (1 << 19)    /* Divide by zero fault bit */
+#define SCTLR_FI   (1 << 21)    /* Fast interrupts configuration enable */
+#define SCTLR_U    (1 << 22)    /* Not on Cortex-R7 processor. Indicates use of the alignment model */
+#define SCTLR_EE   (1 << 25)    /* Exception endianness */
+#define SCTLR_NMFI (1 << 27)    /* Non-maskable FIQ(NMFI) support */
+#define SCTLR_TE   (1 << 30)    /* Thumb exception enable */
+#define SCTLR_IE   (1 << 31)    /* Instruction Endianness */
+/*---------------------------------------------------------------------------*/
+static inline unsigned int
+sctlr_get(void)
+{
+  unsigned int val;
+
+  __asm__ __volatile__ ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val) : : "memory", "cc");
+
+  return val;
+}
+/*---------------------------------------------------------------------------*/
+static inline void
+sctlr_set(unsigned int val)
+{
+  __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val) : "memory", "cc");
+  isb();
+}
+/*---------------------------------------------------------------------------*/
+#endif /* _SYSTEM_H_ */