Initial import of NFC GNSS SDK project
This commit is contained in:
chenjintao
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#ifndef _EFUSE_H
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#define _EFUSE_H
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* define fuse value for psram devie
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* PSRAM Type Code:
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* AP 16M 00000
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* Winbond 16M 00001
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* AP 8M + 8M 00010
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* Winbond 8M + 8M 00100
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* AP 8M 00101
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* Winbond 8M 00110
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* Winbond 250MHz 8M 00111
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* AP UHS 8M + UHS 8M 01000
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* Winbond 250MHz 8M + 250MHz 8M 01001
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*/
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#define AP_16M 0
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#define WB_16M 1
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#define AP_8M8M 2
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#define UNIIC_16M 3
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#define WB_8M8M 4
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#define AP_8M 5
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#define WB_8M 6
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#define WB_250MHZ_8M 7
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#define AP_UHS_8M8M 8
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#define WB_250MHZ_8M8M 9
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#define AP_250MHZ_8M8M 10
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#define WB_XCCELA_8M 11
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#define WB_XCCELA_8M8M 12
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#define WB_4M 13
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#define AP_4M 14
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#define WB_XCCELA_4M 15
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#define AP_250MHZ_8M 16
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#define WB_32M 17
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#define AP_250MHZ_16M 18
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#define WB_250MHZ_16M 19
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#define UNIIC_4M 20
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#define GD_4M 21
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#define GD_8M 22
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#define WB_8M_HYPER21 23
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#define WB_8M8M_HYPER21 24
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typedef enum {
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NO_PHY_AP_4M, /* 0 */
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NO_PHY_WB_4M, /* 1 */
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NO_PHY_AP_8M, /* 2 */
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NO_PHY_WB_8M, /* 3 */
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NO_PHY_AP_16M, /* 4 */
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NO_PHY_WB_16M, /* 5 */
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NO_PHY_UNIIC_16M, /* 6 */
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NO_PHY_UNIIC_4M, /* 7 */
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NO_PHY_PSRAM_TYPE_MAX /* 8 */
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} NO_PHY_PSRAM_TYPE_T;
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#define AP_16M_NAME "AP_16M" /* 0 */
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#define WB_16M_NAME "WB_16M" /* 1 */
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#define AP_8M8M_NAME "AP_8M8M" /* 2 */
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#define UNIIC_16M_NAME "UNIIC_16M" /* 3 */
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#define WB_8M8M_NAME "WB_8M8M" /* 4 */
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#define AP_8MB_NAME "AP_8M" /* 5 */
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#define WB_8MB_NAME "WB_8M" /* 6 */
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#define WB_250MHZ_8M_NAME "WB_250MHZ_8M" /* 7 */
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#define AP_UHS_8M8M_NAME "AP_UHS_8M8M" /* 8 */
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#define WB_250MHZ_8M8M_NAME "WB_250MHZ_8M8M" /* 9 */
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#define AP_250MHZ_8M8M_NAME "AP_250MHZ_8M8M" /* 10 */
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#define WB_XCCELA_8M_NAME "WB_XCCELA_8M" /* 11 */
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#define WB_XCCELA_8M8M_NAME "WB_XCCELA_8M8M" /* 12 */
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#define WB_4MB_NAME "WB_4M" /* 13 */
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#define AP_4MB_NAME "AP_4M" /* 14 */
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#define WB_XCCELA_4M_NAME "WB_XCCELA_4M" /* 15 */
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#define AP_250MHZ_8M_NAME "AP_250MHZ_8M" /* 16 */
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#define WB_32M_NAME "WB_32M" /* 17 */
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#define AP_250MHZ_16M_NAME "AP_250MHZ_16M" /* 18 */
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#define WB_250MHZ_16M_NAME "WB_250MHZ_16M" /* 19 */
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#define UNIIC_4M_NAME "UNIIC_4M" /* 20 */
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#define GD_4M_NAME "GD_4M" /* 21 */
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#define GD_8M_NAME "GD_8M" /* 22 */
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/* 3660 CR5 boot by mcu, not in preboot, preboot only read psram type for scrtach reg, and set prop */
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#define WB_8M_HYPER21_NAME "WB_8M_HYPER21" /* 23 */
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#define WB_8M8M_HYPER21_NAME "WB_8M8M_HYPER21" /* 24 */
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/* psram_crane_mcu.h defined psram type id instead of efuse.h */
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#define AP256Mb_1_2V_X16_CS0_NAME "AP256Mb_1_2V_X16_CS0" /* 0 */
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#define AP256Mb_1_2V_X16_CS1_NAME "AP256Mb_1_2V_X16_CS1" /* 1 */
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#define AP256Mb_1_2V_X16_CS0_CS1_NAME "AP256Mb_1_2V_X16_CS0_CS1" /* 2 */
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#define WB256Mb_1_8V_X16_CS0_NAME "WB256Mb_1_8V_X16_CS0" /* 3 */
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#define WB256Mb_1_8V_X16_CS1_NAME "WB256Mb_1_8V_X16_CS1" /* 4 */
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#define WB256Mb_1_8V_X16_CS0_CS1_NAME "WB256Mb_1_8V_X16_CS0_CS1" /* 5 */
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#define PSRAM_SIZE_4M 0x400000
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#define PSRAM_SIZE_8M 0x800000
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#define PSRAM_SIZE_16M 0x1000000
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#define PSRAM_SIZE_32M 0x2000000
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/* software defined ddr type, can diff with fuse value for ddr device:
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* DDR Type Code:
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* CraneGT use DDR， connect flash instead of SIP
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* 3605S： DDR 32MB + Nor flash 16MB
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* 3605E： DDR 64MB + Nand flash 64MB
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*/
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typedef enum {
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DRAM_AP_32M, /* 0 / * 3605S-111 * / */
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DRAM_UniIC_32M, /* 1 / * 3605S-110 * / */
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DRAM_AP_64M, /* 2 / * 3605E-110 * / */
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DSRAM_TYPE_MAX /* 3 */
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} DRAM_TYPE_T;
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#define DRAM_AP_32M_NAME "DRAM_AP_32M" /*Bytes */
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#define DRAM_AP_64M_NAME "DRAM_AP_64M"
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#define DRAM_UniIC_32M_NAME "DRAM_UniIC_32M"
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#define DRAM_UniIC_64M_NAME "DRAM_UniIC_64M"
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/* reversed fuse ddr bits, but not use fuse now, use autodetect */
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#define DRAM_SIZE_32M 0x2000000
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#define DRAM_SIZE_64M 0x4000000
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#define DRAM_SIZE_128M 0x8000000
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unsigned int efuse_get_psram_version(void);
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unsigned efuse_cranew_mcu_psram(void);
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unsigned int get_psram_size(void);
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unsigned int get_ddr_size(void);
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void fuse_read_lotid(void);
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int fuse_trust_boot_enabled(void);
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bool is_chip_support_auto_detect(void);
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bool efuse_modem_type_is_radio(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _EFUSE_H */
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/** @} */
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@@ -0,0 +1,278 @@
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#ifndef __FLASH_H__
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#define __FLASH_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include <pt.h>
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#include <process.h>
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#ifndef FLASH_VERIFY_EN
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#define FLASH_VERIFY_EN (1) /* defaultly need verify flash written data */
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#endif
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#ifndef FLASH_CHECK_FF_EN
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#define FLASH_CHECK_FF_EN (1) /* defaultly need read flash and check whether are erased, all 0xFF */
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#endif
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#define FLASH_INFO_MAGIC 0x46494E46
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#define MAX_FLASH_DEVICE_NAME 64
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#define MAX_FLASH_DEVICE_TYPE 32
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#define FLASH_TYPE_QSPI_NAND "QSPI_NAND"
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/* the first QSPI flash, crane is extern QSPI flash, craneM/craneG is internal QSPI flash.*/
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#define FLASH_TYPE_QSPI_NOR "QSPI_NOR"
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#define FLASH_TYPE_SPI_NOR "SPI_NOR"
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#define FLASH_TYPE_SPI_NAND "SPI_NAND"
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#define FLASH_TYPE_EMMC "EMMC"
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#define FLASH_TYPE_MEM "MEM"
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#define FLASH_TYPE_DUMMY "DUMMY"
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#define FLASH_TYPE_QSPI2_NOR "QSPI2_NOR"
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#define FLASH_ERR_OTHERS (-1)
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#define FLASH_ERR_BAD_BLOCK (-2)
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#define FLASH_ERR_BAD_PARAMETER (-3)
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#define FLASH_ERR_ECC_ERR (-4)
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#define FLASH_ERR_PROGRAM_ERR (-5)
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#define FLASH_ERR_ERASE_ERR (-6)
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#define SPI_PORT_QSPI 0
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#define SPI_PORT_QSPI0 0
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#define SPI_PORT_SSP0 1
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#define SPI_PORT_SSP1 2
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#define SPI_PORT_SSP2 3
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#define SPI_PORT_QSPI2 4
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#define SPI_PORT_EMMC 5
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#define SPI_PORT_MEM 6
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#define SPI_PORT_QSPI1 7
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/* SSP_<CLK>_<FRM>_<RXD>_<TXD> */
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typedef enum {
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SSP_GPIO_CONFIG_DEFAULT,
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SSP_GPIO4_FUNC2_GPIO5_FUNC2_GPIO6_FUNC2_GPIO7_FUNC2,
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SSP_GPIO4_FUNC7_GPIO5_FUNC7_GPIO6_FUNC7_GPIO7_FUNC7,
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SSP_GPIO12_FUNC1_GPIO13_FUNC1_GPIO14_FUNC1_GPIO15_FUNC1,
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SSP_GPIO16_FUNC2_GPIO17_FUNC2_GPIO19_FUNC2_GPIO18_FUNC2,
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SSP_GPIO16_FUNC2_GPIO17_FUNC2_GPIO18_FUNC4_GPIO19_FUNC4,
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SSP_GPIO33_FUNC1_GPIO34_FUNC1_GPIO35_FUNC1_GPIO36_FUNC1,
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SSP_GPIO33_FUNC2_GPIO34_FUNC2_GPIO35_FUNC2_GPIO36_FUNC2,
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SSP_GPIO64_FUNC7_GPIO63_FUNC7_GPIO61_FUNC7_GPIO62_FUNC7,
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SSP_GPIO71_FUNC2_GPIO72_FUNC2_GPIO73_FUNC2_GPIO74_FUNC2,
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SSP_QSPI_CLK_FUNC2_QSPI_CS1_FUNC2_QSPI_DAT1_FUNC2_QSPI_DAT0_FUNC2,
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SSP_QSPI_CLK_FUNC4_QSPI_CS1_FUNC4_QSPI_DAT1_FUNC4_QSPI_DAT0_FUNC4,
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SSP_GPIO4_FUNC2_GPIO55_FUNC0_GPIO6_FUNC2_GPIO7_FUNC2,
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} ssp_gpio_config_t;
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struct compatible_device {
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uint16_t vendor_id;
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uint16_t device_id;
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uint32_t reserved1;
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char device_name[MAX_FLASH_DEVICE_NAME];
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};
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/**
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* \brief Flash information
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*/
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struct flash_info {
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uint32_t magic;
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uint16_t vendor_id;
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uint16_t device_id;
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char device_name[MAX_FLASH_DEVICE_NAME];
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char device_type[MAX_FLASH_DEVICE_TYPE];
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/* the following two parameters are used by ubi */
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uint32_t min_io_size;
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uint32_t peb_size;
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/* the following three parameters are used by erase and program */
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uint32_t page_size;
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uint32_t sector_size;
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uint32_t block_size;
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uint8_t reserved1[3];
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uint8_t ssp_gpio : 6;
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uint8_t ssp_clk : 2;
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/* total flash size */
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uint64_t flash_size;
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uint8_t erased_value; /*/< Contents of erased memory (usually 0xFF) */
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uint8_t chained;
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uint8_t spi_port;
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uint8_t combined_flash_size_in_mb; /* combined flash size in MB */
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uint32_t compatible_device_num;
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struct compatible_device compatible_device_list[1];
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};
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typedef enum {
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SSP_CLK_52M,
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SSP_CLK_26M,
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SSP_CLK_13M,
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SSP_CLK_6500K,
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} ssp_clk_config_t;
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typedef struct {
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uint32_t pnum;
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uint32_t offset;
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} ubi_addr_t;
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typedef struct {
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const void *flash;
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size_t partition_size;
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} sparse_param_t;
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typedef struct {
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/* Containers for the State */
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struct pt pt;
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/* Input Variables */
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process_event_t ev;
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union {
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uint64_t addr;
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ubi_addr_t ubi_addr;
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sparse_param_t sparse_param;
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};
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const void *data;
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size_t size;
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size_t repeats;
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/* Output Variables */
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int result; /**< Result Code */
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} flash_state_t;
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/* support spi_nor_flash.c use qspi controller common interface, although spi did not use qspi controller */
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typedef int (*qspi_read_t)(unsigned seqid, unsigned addr, void *data, size_t size);
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typedef int (*qspi_write_t)(unsigned seqid, unsigned addr, const void *data, size_t size);
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typedef void (*qspi_cmd_t)(unsigned seqid, unsigned addr);
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typedef struct {
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qspi_read_t qspi_read;
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qspi_write_t qspi_write;
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qspi_cmd_t qspi_cmd;
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} qpsi_lut_operation_t;
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typedef int (*flash_read_t)(uint64_t addr, void *data, size_t size);
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typedef char (*flash_write_t)(flash_state_t *state);
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typedef char (*flash_erase_t)(flash_state_t *state);
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typedef const struct flash_info *(*flash_get_info_t)(void);
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typedef int (*flash_erase_sync_t)(uint64_t addr, size_t size);
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typedef int (*flash_write_sync_t)(uint64_t addr, const void *data, size_t size);
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/*---------------------------------------------------------------------------*/
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typedef void (*flash_quad_enable_cb_t)(const qpsi_lut_operation_t *lut_op, bool enable);
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/*---------------------------------------------------------------------------*/
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struct flash_operation {
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flash_read_t read;
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flash_write_t write;
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flash_erase_t erase;
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flash_write_sync_t write_sync;
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flash_erase_sync_t erase_sync;
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flash_get_info_t info;
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};
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typedef enum {
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FLASH_ID_FIRST, /* first flash */
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FLASH_ID_SECOND, /* second flash */
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FLASH_ID_THIRD, /* third flash */
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FLASH_ID_MAX
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} flash_id_t;
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/* start a protothread to do thread_fun(uint64_t address, const void *buf, size_t sz).
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* state: supply parent pt for thread_fun.
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* child_state: pt for thread_fun.(if multi pt threads, child_state may be custom defined)
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* state->result: return result of thread_fun.
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*
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* eg: if thread_fun is partition_raw_flash(uint64_t address, const void *buf, size_t sz),
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* invoke FLASH_BASE_TASK(state, partition_raw_flash_state, partition_raw_flash, address, buf, sz);
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*/
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#define FLASH_BASE_TASK(state, child_state, thread_fun, address, buf, sz, repts) \
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{ \
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static flash_state_t child_state; \
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memset(&child_state, 0, sizeof(child_state)); \
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child_state.ev = state->ev; \
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child_state.addr = address; \
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child_state.data = buf; \
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child_state.size = sz; \
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child_state.repeats = repts; \
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PT_SPAWN(&state->pt, &(child_state.pt), thread_fun(&child_state)); \
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state->result = child_state.result; \
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}
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#define INPUT_VOID_TASK(state, child_state, thread_fun) \
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FLASH_BASE_TASK(state, child_state, thread_fun, 0, NULL, 0, 0)
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/* start a protothread to do thread_fun(void).
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* state: supply parent pt for thread_fun(void).
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* state->result: return result of thread_fun(void).
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*
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* eg: if thread_fun(void) is wait_for_complete_task(void),
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* invoke WAIT_TASK(state, wait_for_complete_task);
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*/
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#define WAIT_TASK(state, thread_fun) \
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FLASH_BASE_TASK(state, wait_state, thread_fun, 0, NULL, 0, 0)
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/* start a protothread to do thread_fun(uint64_t address, size_t sz).
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* state: supply parent pt for thread_fun.
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* state->result: return result of thread_fun.
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*
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* eg: if thread_fun is flash->erase(uint64_t address, size_t sz),
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* invoke FLASH_ERASE_TASK(state, flash->erase, address, sz);
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*/
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#define FLASH_ERASE_TASK(state, thread_fun, address, sz) \
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FLASH_BASE_TASK(state, erase_state, thread_fun, address, NULL, sz, 0)
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/* start a protothread to do thread_fun(uint64_t address, const void *buf, size_t sz, size_t repeats).
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* state: supply parent pt for thread_fun.
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* state->result: return result of thread_fun.
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*
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* eg: if thread_fun is flash->write(uint64_t address, const void *buf, size_t sz, size_t repeats),
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* invoke FLASH_WRITE_TASK(state, flash->write, address, buf, sz, repeats);
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*/
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#define FLASH_WRITE_TASK(state, thread_fun, address, buf, sz, repeats) \
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FLASH_BASE_TASK(state, write_state, thread_fun, address, buf, sz, repeats)
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int flash_info_init(const void *data, size_t size);
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int flash_force_all_probe(void);
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const struct flash_operation *flash_set_operation(flash_id_t flash_id);
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const struct flash_operation *flash_get_operation(void);
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const struct flash_operation *flash_get_operation_with_id(flash_id_t flash_id);
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int flash_verify(uint64_t addr, const void *data, size_t size);
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bool flash_is_chip_erased(flash_id_t id);
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void flash_set_chip_erased(flash_id_t id);
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void flash_reset_chip_erased(void);
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flash_id_t flash_get_current_flash_id(void);
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/* read current flash from any address */
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int flash_read_unaligned(uint64_t addr, void *data, size_t size);
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uint8_t *flash_get_tmp_buffer(size_t sz);
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#define FLASH_IS_ALL_FF_TASK(state, address, sz) \
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FLASH_BASE_TASK(state, flash_is_all_ff_state, flash_is_all_ff, address, NULL, sz, 0)
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PT_THREAD(flash_is_all_ff(flash_state_t * state));
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|
||||
#define FLASH_VERIFY_TASK(state, address, data, sz) \
|
||||
FLASH_BASE_TASK(state, flash_verify_state, flash_verify_pt, address, data, sz, 0)
|
||||
|
||||
PT_THREAD(flash_verify_pt(flash_state_t * state));
|
||||
|
||||
#ifdef USE_QSPI_NOR_FLASH
|
||||
extern bool flash_with_qspi2_nor;
|
||||
int flash_nor_write_by_page(uint64_t address, const void *data, size_t size);
|
||||
int flash_nor_erase_by_sector(uint64_t address, size_t size);
|
||||
#endif
|
||||
|
||||
#ifdef USE_QSPI_NAND_FLASH
|
||||
int flash_nand_write_by_page(uint64_t address, const void *data, size_t size);
|
||||
int flash_nand_erase_by_sector(uint64_t address, size_t size);
|
||||
#endif
|
||||
|
||||
void flash_get_info_base(uintptr_t *base, size_t *size);
|
||||
|
||||
#ifdef __cplusplus
|
||||
} /* extern "C" */
|
||||
#endif
|
||||
|
||||
#endif /* __FLASH_H__ */
|
||||
@@ -0,0 +1,68 @@
|
||||
#ifndef PERIPH_PSRAM_H
|
||||
#define PERIPH_PSRAM_H
|
||||
#include "syscall-arom.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* craneg not support clk mode, but bit8 reserved */
|
||||
typedef enum {
|
||||
CLK_MODE_1X = 0, /* 1x mode */
|
||||
CLK_MODE_2X, /* 2x mode */
|
||||
CLK_MODE_MAX
|
||||
} clk_mode_t;
|
||||
|
||||
/*
|
||||
* PHYCLK clk select , bit20~18
|
||||
* craneg: phy clk = phy_sel/(phy_clk_divider+1), eg: phy clk = phy_sel/2 = 156/2=78M
|
||||
* craneLR A0/cranew cr5: phy clk = phy_sel/(phy_clk_divider+1)/clk_mode. clk_mode=1(1xmode), clk_mode=2(2xmode),
|
||||
* psram two edge samples, so Mbps = MHz *2;
|
||||
* If mcu is 208MHz, means it is 416Mbps(PSRAM_FREQ_416M).
|
||||
* PSRAM_FREQ_156Mbps: phy clk 78MHz
|
||||
*/
|
||||
struct PsramPP_t {
|
||||
unsigned freq;
|
||||
unsigned clkSel; /*clock selection ( pc clk select: bit28~26, phy clk select: bit20~18,) */
|
||||
unsigned clkDiv; /*phy clk divider (bit17~16) */
|
||||
clk_mode_t clkMode; /*0: 1x mode; 1: 2xmode, add after craneLR, include cranew cr5 */
|
||||
};
|
||||
|
||||
#define PSRAM_FREQ_156M 0 /*LV0: 78M 156Mps*/
|
||||
#define PSRAM_FREQ_312M 1 /*LV1: 156M 312Mps*/
|
||||
#define PSRAM_FREQ_350M 2 /*LV2: 175M 350Mbps, craneLR: 356Mbps */
|
||||
#define PSRAM_FREQ_416M 3 /*LV3: 208M 416Mps*/
|
||||
#define PSRAM_FREQ_500M 4 /*LV4: 250M 500Mps*/
|
||||
|
||||
#if 0
|
||||
//test lower freq can use it
|
||||
#define PSRAM_FREQ_LV4 4 /*LV4: */
|
||||
#define PSRAM_FREQ_LV5 5 /*LV5: */
|
||||
#endif
|
||||
/*
|
||||
* preboot will not use psram LV4 PSRAM_FREQ_533M, cp use LV4.
|
||||
* phy clk 533M ~2000M need enable PLL2, see Asic code: psram_fc_init -> phy_pll2_fc
|
||||
*/
|
||||
/*PCCLK clk select , bit28~26 */
|
||||
#define PSRAM_PCCLK_PLL1_312M 0
|
||||
#define PSRAM_PCCLK_PLL1_350M 1
|
||||
#define PSRAM_PCCLK_PLL1_416M 2
|
||||
#define PSRAM_PCCLK_PLL1_208M 4
|
||||
#define PSRAM_PCCLK_PLL1_156M 5
|
||||
|
||||
#define PSRAM_CACHELINE_64B 0
|
||||
#define PSRAM_CACHELINE_128B 1
|
||||
#define PSRAM_CACHELINE_256B 2
|
||||
#define PSRAM_CACHELINE_512B 3
|
||||
|
||||
void psram_init(void);
|
||||
void psram_pll1_enable(void);
|
||||
void psram_test(void);
|
||||
void psram_phy_fc_config(unsigned phyclk_level);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PERIPH_PSRAM_H */
|
||||
/** @} */
|
||||
@@ -0,0 +1,111 @@
|
||||
#ifndef PSRAM_MEM_VERIFY_H
|
||||
#define PSRAM_MEM_VERIFY_H
|
||||
|
||||
#include <limits.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include <string.h>
|
||||
#include "pt.h"
|
||||
#include "process.h"
|
||||
#include "contiki.h"
|
||||
#include "flash.h"
|
||||
|
||||
#define PSRAM_MEM_TEST_ALL 0
|
||||
|
||||
/*
|
||||
* crane_flasehr and psram.c will use it
|
||||
* If scan psram memory to test psram, enable it
|
||||
*/
|
||||
/*#define PSRAM_MEM_TEST_ALL 1 */
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
typedef unsigned long ul;
|
||||
typedef unsigned long long ull;
|
||||
typedef unsigned long volatile ulv;
|
||||
typedef unsigned char volatile u8v;
|
||||
typedef unsigned short volatile u16v;
|
||||
/*---------------------------------------------------------------------------*/
|
||||
typedef struct {
|
||||
/* Containers for the State */
|
||||
struct pt pt;
|
||||
/* Input Variables */
|
||||
process_event_t ev;
|
||||
union {
|
||||
unsigned long volatile *bufa;
|
||||
unsigned long start;
|
||||
};
|
||||
union {
|
||||
unsigned long volatile *bufb;
|
||||
unsigned long end;
|
||||
};
|
||||
union {
|
||||
size_t count;
|
||||
size_t size;
|
||||
};
|
||||
|
||||
unsigned int id;
|
||||
/* Output Variables */
|
||||
int result; /**< Result Code */
|
||||
} pmem_state_t;
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/* start a protothread to do thread_fun(uint64_t address, const void *buf, size_t sz).
|
||||
* state: supply parent pt for thread_fun.
|
||||
* child_state: pt for thread_fun.(if multi pt threads, child_state may be custom defined)
|
||||
* state->result: return result of thread_fun.
|
||||
*
|
||||
* eg: if thread_fun is test_xor_comparison(unsigned long volatile *bufa, unsigned long volatile *bufb, size_t count),
|
||||
* invoke PMEM_BASE_TASK(state, test_xor_comparison_state, test_xor_comparison, bufa, bufb, count);
|
||||
*/
|
||||
#define PMEM_BASE_TASK(state, child_state, thread_fun, buf_a, buf_b, sz, case_id) \
|
||||
{ \
|
||||
static pmem_state_t child_state; \
|
||||
memset(&child_state, 0, sizeof(child_state)); \
|
||||
child_state.ev = state->ev; \
|
||||
child_state.bufa = buf_a; \
|
||||
child_state.bufb = buf_b; \
|
||||
child_state.count = sz; \
|
||||
child_state.id = case_id; \
|
||||
PT_SPAWN(&state->pt, &(child_state.pt), thread_fun(&child_state)); \
|
||||
state->result = child_state.result; \
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
#define ADD_FAIL_NUM(state) \
|
||||
{ \
|
||||
if(!state->result) { \
|
||||
LOG_INFO(" ok\n"); \
|
||||
} else { \
|
||||
LOG_INFO(" fail\n"); \
|
||||
pmem_fail_num++; \
|
||||
} \
|
||||
LOG_INFO("\n\r"); \
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
typedef enum {
|
||||
PMEM_ID_TEST_RANDOM, /*0*/
|
||||
PMEM_ID_TEST_XOR, /*1*/
|
||||
PMEM_ID_TEST_SUB, /*2*/
|
||||
PMEM_ID_TEST_MUL, /*3*/
|
||||
PMEM_ID_TEST_DIV, /*4*/
|
||||
PMEM_ID_TEST_OR, /*5*/
|
||||
PMEM_ID_TEST_AND, /*6*/
|
||||
PMEM_ID_TEST_SEQINC, /*7*/
|
||||
PMEM_ID_TEST_SOLIDBITS, /*8*/
|
||||
PMEM_ID_TEST_BLOCKSEQ, /*9*/
|
||||
PMEM_ID_TEST_CHECHERBORD, /*10*/
|
||||
PMEM_ID_TEST_BITSPREAD, /*11*/
|
||||
PMEM_ID_TEST_BITFLIP, /*12*/
|
||||
PMEM_ID_TEST_WALKBITS1, /*13*/
|
||||
PMEM_ID_TEST_WALKBITS0, /*14*/
|
||||
PMEM_ID_TEST_8BIT_WIDE_RANDOM, /*15*/
|
||||
PMEM_ID_TEST_16BIT_WIDE_RANDOM, /*16*/
|
||||
PMEM_ID_TEST_DDR_PATTERN_ALL_0, /*17*/
|
||||
PMEM_ID_TEST_DDR_PATTERN_ALL_1, /*18*/
|
||||
PMEM_ID_TEST_DDR_PATTERN_SPLIT_1, /*19*/
|
||||
|
||||
PMEM_ID_MAX
|
||||
} pmem_id_t;
|
||||
|
||||
PT_THREAD(psram_mem_test_all(pmem_state_t * state));
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,8 @@
|
||||
#ifndef __USB_SERIAL_H__
|
||||
#define __USB_SERIAL_H__
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
bool usb_enumeration_is_complete(void);
|
||||
|
||||
#endif /* __USB_SERIAL_H__ */
|
||||
Reference in New Issue
Block a user