Initial import of NFC GNSS SDK project
This commit is contained in:
chenjintao
@@ -0,0 +1,89 @@
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#-------------------------------------------------------------------------------
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# Configure variable
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#-------------------------------------------------------------------------------
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TOP_DIR:=${TOP_DIR}
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MAKEFILE_PATH :=$(subst $(strip \),/,$(abspath $(lastword $(MAKEFILE_LIST))))
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#-------------------------------------------------------------------------------
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# Configure source code files
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#-------------------------------------------------------------------------------
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SRC_FILES+= \
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cinit1.c \
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utilities.c \
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crane_ds_mpu.c \
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initTaskUtil.c \
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quec_init.c \
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cinit2.c \
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main.c \
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#-------------------------------------------------------------------------------
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# the include directories
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#-------------------------------------------------------------------------------
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INC_DIRS+= \
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-I${TOP_DIR}\ \
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-I${TOP_DIR}\common\include \
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-I${TOP_DIR}\common\include\Arbel\src \
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-I${TOP_DIR}\common\include\env\inc \
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#-------------------------------------------------------------------------------
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# Configure compile flag for C
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#-------------------------------------------------------------------------------
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ifneq (,$(findstring 1606,${ASR_PLATFORM}))
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U_FLAGS+= \
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endif
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ifneq (,$(findstring 1602,${ASR_PLATFORM}))
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U_FLAGS+= \
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endif
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ifneq (,$(findstring 1605,${ASR_PLATFORM}))
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U_FLAGS+= \
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endif
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#-------------------------------------------------------------------------------
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# Configure compile flag for C++
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#-------------------------------------------------------------------------------
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U_CPPFLAGS+=
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#-------------------------------------------------------------------------------
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# Configure default macro define
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#-------------------------------------------------------------------------------
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ifneq (,$(findstring 1606,${ASR_PLATFORM}))
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DFLAGS+= \
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-D"NO_APLP=0" \
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-D"GPRS_MULTISLOT_CLASS=12" \
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-DGPIO_TRACE \
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-D"EGPRS_MULTISLOT_CLASS=12" \
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endif
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ifneq (,$(findstring 1602,${ASR_PLATFORM}))
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DFLAGS+= \
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-D"NO_APLP=0" \
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-D"GPRS_MULTISLOT_CLASS=12" \
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-DGPIO_TRACE \
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-D"EGPRS_MULTISLOT_CLASS=12" \
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endif
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ifneq (,$(findstring 1605,${ASR_PLATFORM}))
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DFLAGS+= \
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-D"NO_APLP=0" \
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-D"GPRS_MULTISLOT_CLASS=12" \
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-DGPIO_TRACE \
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-D"EGPRS_MULTISLOT_CLASS=12" \
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endif
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#-------------------------------------------------------------------------------
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# Configure link library
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#-------------------------------------------------------------------------------
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U_LIBS:=
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#-------------------------------------------------------------------------------
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# include mk file
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#-------------------------------------------------------------------------------
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include ${TOP_DIR}\config\common\makefile.mk
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,298 @@
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/*------------------------------------------------------------
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(C) Copyright [2006-2008] Marvell International Ltd.
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All Rights Reserved
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------------------------------------------------------------*/
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/*--------------------------------------------------------------------------------------------------------------------
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INTEL CONFIDENTIAL
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Copyright 2006 Intel Corporation All Rights Reserved.
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The source code contained or described herein and all documents related to the source code ("Material") are owned
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by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or
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its suppliers and licensors. The Material contains trade secrets and proprietary and confidential information of
|
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Intel or its suppliers and licensors. The Material is protected by worldwide copyright and trade secret laws and
|
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treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted,
|
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transmitted, distributed, or disclosed in any way without Intel's prior express written permission.
|
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|
||||
No license under any patent, copyright, trade secret or other intellectual property right is granted to or
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conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement,
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estoppel or otherwise. Any license under such intellectual property rights must be express and approved by
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Intel in writing.
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-------------------------------------------------------------------------------------------------------------------*/
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/***************************************************************************
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* MODULE IMPLEMENTATION FILE
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****************************************************************************
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* Title: Initialing code
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*
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* Filename: cinit2.c
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*
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* Target, platform: Manitoba, Hermon
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*
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* Authors: Gideon Yuval
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*
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* Description:
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* Final Stack Init
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*
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******************************************************************************/
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/*----------- External include files -----------------------------------------*/
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#if defined(__arm)
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#include <locale.h>
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#endif
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#include <string.h>
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#include "global_types.h"
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#include "utils.h"
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#include "bsp_config.h"
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#ifdef PLAT_USE_THREADX
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#include <tx_port.h>
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#include <tx_thread.h>
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#include <tx_timer.h>
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#include <tx_initialize.h>
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#endif
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#include "UART.h"
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#include "quec_cust_feature.h"
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#define AGGRESSIVE_STACK_REUSE
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#define REUSE_HISR_STACK_FOR_TIMERS
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/*----------- Local include files --------------------------------------------*/
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extern VOID INC_Initialize(VOID *first_available_memory);
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/*
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* NOTE: Beware to chose right stack sizes.
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* Improper stack sizes may cause severe SW failures !!!
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*/
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/* Larger Sytem stack and HISR stack set mainly due to /softutil/transport stack consumption - reduce later */
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#define STACK_ALIGNMENT 8 /*Bytes*/
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#define SYSTEM_STACK_SIZE (1024*4) /* Number of bytes in System stack */
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#if defined(PLAT_USE_THREADX) || defined(PLAT_USE_ALIOS)
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#define SYSTEM_TIMER_STACK_SIZE (1024*4)
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#endif
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#if !defined(REUSE_HISR_STACK_FOR_TIMERS)
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#define SYSTEM_HISR_STACK_SIZE (1024*4) /* Number of bytes in System HISR stack */
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#endif
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#define IRQ_STACK_SIZE (1024*2) /* Number of bytes in IRQ stack */
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#if defined (AGGRESSIVE_STACK_REUSE)
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#define COMMON_STACK_SIZE 0x200
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#else
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#define FIQ_STACK_SIZE 1024 /* Number of bytes in FIQ stack */
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#define DATA_ABORT_STACK_SIZE 0x200 /* Number of bytes data abort stack */
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#define UNDEFINED_STACK_SIZE 0x200 /* Number of bytes UNDEFINED_MODE stack */
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#endif
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#if defined(PLAT_USE_THREADX) || defined(PLAT_USE_ALIOS)
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static UINT32 __align(STACK_ALIGNMENT) __System_Timer_Stack[SYSTEM_TIMER_STACK_SIZE/sizeof(UINT32)];
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#endif
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static UINT32 __align(STACK_ALIGNMENT) __System_Stack[SYSTEM_STACK_SIZE/sizeof(UINT32)];
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#if defined(PLAT_USE_ALIOS)
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UINT32 sys_stack_top;
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#endif
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#if !defined(REUSE_HISR_STACK_FOR_TIMERS)
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/*
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* System HISR Stack is used by Nucleus timer HISR
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*/
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static UINT32 __align(STACK_ALIGNMENT) __System_HISR_Stack[SYSTEM_HISR_STACK_SIZE/sizeof(UINT32)];
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#else
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#if 0//NOT NU_OS
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extern UINT32 __align(STACK_ALIGNMENT) hisrStack[HISR_PRIORITY_LEVELS][HISR_STACK_SIZE/sizeof(UINT32)];
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#endif
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#endif
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/*
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* System IRQ Stack is used by Nucleus IRQ interrupt handler
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*/
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static UINT32 __align(STACK_ALIGNMENT) __IRQ_Stack[IRQ_STACK_SIZE/sizeof(UINT32)];
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#if defined (AGGRESSIVE_STACK_REUSE)
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/* Reuse one same System Stack for Nucleus FIQ interrupt handler, DataAbortHandler and UNDEFINED mode Handler */
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static UINT32 __align(STACK_ALIGNMENT) __Common_Stack[COMMON_STACK_SIZE/sizeof(UINT32)];
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#define __FIQ_Stack __Common_Stack
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#define __ABORT_Stack __Common_Stack
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#define __UNDEFINED_Stack __Common_Stack
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#else
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static UINT32 __align(STACK_ALIGNMENT) __FIQ_Stack[FIQ_STACK_SIZE/sizeof(UINT32)];
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static UINT32 __align(STACK_ALIGNMENT) __ABORT_Stack[DATA_ABORT_STACK_SIZE/sizeof(UINT32)];
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static UINT32 __align(STACK_ALIGNMENT) __UNDEFINED_Stack[UNDEFINED_STACK_SIZE/sizeof(UINT32)];
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#endif
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/* Timer HISR priority (values from 0 to 2, where 0 is highest) */
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#define TIMER_PRIORITY 2
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extern UINT32 OsaTaskStackMagic(void);
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INT32 task_stack_magic = 0;
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/*----------- Global function definition -------------------------------------*/
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/******************************************************************************
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* Function : Cinit2
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*******************************************************************************
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*
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* Description :
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*
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******************************************************************************/
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void Cinit2 (void)
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{
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#ifdef PLAT_USE_THREADX
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UINT32 SystemStack, SystemLimit;
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extern volatile ULONG _tx_thread_system_state;
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CPUartLogPrintf("Cinit 2");
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_tx_thread_system_state = TX_INITIALIZE_IN_PROGRESS;
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task_stack_magic = OsaTaskStackMagic();
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/*Init final stacks*/
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//ToDo - except the system stack, v7 isn't initialized as it was done for the temp stacks - fix this
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/* Fill in basic stacks in order to detect overlow */
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memset((void*)__System_Stack, 0xA5, sizeof(__System_Stack));
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memset((void*)__System_Timer_Stack, 0xA5, sizeof(__System_Timer_Stack));
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#if !defined(REUSE_HISR_STACK_FOR_TIMERS)
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memset((void*)__System_HISR_Stack, 0xA5, sizeof(__System_HISR_Stack));
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#else
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#if 0//NOT NU_OS
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memset((void*)hisrStack, 0xA5, sizeof(hisrStack));
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#endif
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#endif
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memset((void*)__IRQ_Stack, 0xA5, sizeof(__IRQ_Stack));
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memset((void*)__FIQ_Stack, 0xA5, sizeof(__FIQ_Stack));
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memset((void*)__ABORT_Stack, 0xA5, sizeof(__ABORT_Stack));
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memset((void*)__UNDEFINED_Stack, 0xA5, sizeof(__UNDEFINED_Stack));
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// Setup mode stacks
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SetMode_R13(CPSR_MODE_FIQ,((UINT32)__FIQ_Stack)+sizeof(__FIQ_Stack));
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SetMode_R13(CPSR_MODE_IRQ,((UINT32)__IRQ_Stack)+sizeof(__IRQ_Stack));
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SetMode_R13(CPSR_MODE_ABT,((UINT32)__ABORT_Stack)+sizeof(__ABORT_Stack));
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SetMode_R13(CPSR_MODE_UND,((UINT32)__UNDEFINED_Stack)+sizeof(__UNDEFINED_Stack));
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#if defined(__arm)
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/* Ensure proper functionality of some C library functions */
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setlocale(LC_ALL, "C");
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#endif
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SystemLimit= (UINT32)__System_Stack;
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SystemStack = SystemLimit + sizeof(__System_Stack);
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_tx_thread_system_stack_ptr = (void*)__System_Stack;
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_tx_timer_stack_start = (void*)__System_Timer_Stack;
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_tx_timer_stack_size = SYSTEM_TIMER_STACK_SIZE;
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_tx_timer_priority = 0;
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SetSystemStack(SystemStack, SystemLimit);
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tx_kernel_enter();
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#elif defined(PLAT_USE_ALIOS)
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UINT32 SystemStack, SystemLimit;
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task_stack_magic = OsaTaskStackMagic();
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/*Init final stacks*/
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//ToDo - except the system stack, v7 isn't initialized as it was done for the temp stacks - fix this
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/* Fill in basic stacks in order to detect overlow */
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memset((void*)__System_Stack, 0xA5, sizeof(__System_Stack));
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memset((void*)__System_Timer_Stack, 0xA5, sizeof(__System_Timer_Stack));
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#if !defined(REUSE_HISR_STACK_FOR_TIMERS)
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memset((void*)__System_HISR_Stack, 0xA5, sizeof(__System_HISR_Stack));
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#else
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#if 0//NOT NU_OS
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memset((void*)hisrStack, 0xA5, sizeof(hisrStack));
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#endif
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#endif
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memset((void*)__IRQ_Stack, 0xA5, sizeof(__IRQ_Stack));
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memset((void*)__FIQ_Stack, 0xA5, sizeof(__FIQ_Stack));
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memset((void*)__ABORT_Stack, 0xA5, sizeof(__ABORT_Stack));
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memset((void*)__UNDEFINED_Stack, 0xA5, sizeof(__UNDEFINED_Stack));
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// Setup mode stacks
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SetMode_R13(CPSR_MODE_FIQ,((UINT32)__FIQ_Stack)+sizeof(__FIQ_Stack));
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SetMode_R13(CPSR_MODE_IRQ,((UINT32)__IRQ_Stack)+sizeof(__IRQ_Stack));
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SetMode_R13(CPSR_MODE_ABT,((UINT32)__ABORT_Stack)+sizeof(__ABORT_Stack));
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SetMode_R13(CPSR_MODE_UND,((UINT32)__UNDEFINED_Stack)+sizeof(__UNDEFINED_Stack));
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#if defined(__arm)
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/* Ensure proper functionality of some C library functions */
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||||
setlocale(LC_ALL, "C");
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#endif
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SystemLimit= (UINT32)__System_Stack;
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SystemStack = SystemLimit + sizeof(__System_Stack);
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sys_stack_top = SystemStack;
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SetSystemStack(SystemStack, SystemLimit);
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||||
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||||
extern void start_aos_kernel(void);
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start_aos_kernel();
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#else
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|
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/* Nucleus variables to setup before INC_Initiaize call */
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||||
extern UINT32 TCD_System_Stack, TCT_System_Limit, TMD_HISR_Stack_Ptr, TMD_HISR_Stack_Size, TMD_HISR_Priority;
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||||
|
||||
/*Init final stacks*/
|
||||
//ToDo - except the system stack, v7 isn't initialized as it was done for the temp stacks - fix this
|
||||
/* Fill in basic stacks in order to detect overlow */
|
||||
memset((void*)__System_Stack, 0xA5, sizeof(__System_Stack));
|
||||
#if !defined(REUSE_HISR_STACK_FOR_TIMERS)
|
||||
memset((void*)__System_HISR_Stack, 0xA5, sizeof(__System_HISR_Stack));
|
||||
#else
|
||||
#if 0//NOT NU_OS
|
||||
memset((void*)hisrStack, 0xA5, sizeof(hisrStack));
|
||||
#endif
|
||||
#endif
|
||||
memset((void*)__IRQ_Stack, 0xA5, sizeof(__IRQ_Stack));
|
||||
memset((void*)__FIQ_Stack, 0xA5, sizeof(__FIQ_Stack));
|
||||
memset((void*)__ABORT_Stack, 0xA5, sizeof(__ABORT_Stack));
|
||||
memset((void*)__UNDEFINED_Stack, 0xA5, sizeof(__UNDEFINED_Stack));
|
||||
|
||||
// Setup mode stacks
|
||||
SetMode_R13(CPSR_MODE_FIQ,((UINT32)__FIQ_Stack)+sizeof(__FIQ_Stack));
|
||||
SetMode_R13(CPSR_MODE_IRQ,((UINT32)__IRQ_Stack)+sizeof(__IRQ_Stack));
|
||||
SetMode_R13(CPSR_MODE_ABT,((UINT32)__ABORT_Stack)+sizeof(__ABORT_Stack));
|
||||
SetMode_R13(CPSR_MODE_UND,((UINT32)__UNDEFINED_Stack)+sizeof(__UNDEFINED_Stack));
|
||||
|
||||
#if !defined(REUSE_HISR_STACK_FOR_TIMERS)
|
||||
TMD_HISR_Stack_Size=sizeof(__System_HISR_Stack);
|
||||
TMD_HISR_Stack_Ptr=(UINT32)__System_HISR_Stack;
|
||||
#else
|
||||
#if 0//NOT NU_OS
|
||||
TMD_HISR_Stack_Size=HISR_STACK_SIZE;
|
||||
TMD_HISR_Stack_Ptr=(UINT32)hisrStack[TIMER_PRIORITY];
|
||||
#endif
|
||||
#endif
|
||||
TMD_HISR_Priority=TIMER_PRIORITY;
|
||||
|
||||
TCT_System_Limit=(UINT32)__System_Stack;
|
||||
TCD_System_Stack=TCT_System_Limit+sizeof(__System_Stack);
|
||||
SetSystemStack(TCD_System_Stack,TCT_System_Limit);
|
||||
|
||||
|
||||
#if defined(__arm)
|
||||
/* Ensure proper functionality of some C library functions */
|
||||
setlocale(LC_ALL, "C");
|
||||
#endif
|
||||
|
||||
/*Init Nucleus*/
|
||||
INC_Initialize (/*(VOID*)&top_of_heap_chk*/0); // The parameter "first_available_memory" must be present
|
||||
// is not used by Nucleus, but is passed to Application_Initialize (also does not use it)
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
@@ -0,0 +1,389 @@
|
||||
#include "bsp.h"
|
||||
#include "crane_ds_mpu.h"
|
||||
#include "loadTable.h"
|
||||
#include "UART.h"
|
||||
|
||||
unsigned int region_cnt = 0;
|
||||
|
||||
BOOL xip_access_enable = TRUE;
|
||||
|
||||
#ifdef QUECTEL_PROJECT_CUST
|
||||
extern unsigned int Image$$DDR_NONCACHE_REGION_ACIPC_PS_UL$$Base;
|
||||
unsigned int quec_nocache_start_check(unsigned int addr)
|
||||
{
|
||||
if((unsigned int)(&Image$$DDR_NONCACHE_REGION_ACIPC_PS_UL$$Base) != addr){
|
||||
RTI_LOG("mpu_error %s %s,0x%x,0x%x",__FILE__,__LINE__,(unsigned int)(&Image$$DDR_NONCACHE_REGION_ACIPC_PS_UL$$Base),addr);
|
||||
ASSERT(0)
|
||||
}
|
||||
return addr;
|
||||
}
|
||||
|
||||
#define NOCACHE_STARTADDR_CHECK(ADDR) quec_nocache_start_check(ADDR)
|
||||
#endif
|
||||
|
||||
static unsigned int crane_ds_mpu_16M_psram_16M_flash_xip(unsigned int cnt) {
|
||||
#ifdef CRANE_MCU_DONGLE
|
||||
|
||||
#ifdef CRANELS_16M16M
|
||||
/*
|
||||
mpu_config_region_set_mem(region_num, base_address, REGION_SIZE, ACCESS_PERMISSION, cacheable, shared, execute_never) */
|
||||
mpu_config_region_set_mem(cnt++, 0x00000000, REG_64KB, READ_ONLY, 0, 0, 0);//[ 64K] ATCM
|
||||
mpu_config_region_set_mem(cnt++, 0xB0020000, REG_64KB, FULL_ACCESS, 0, 0, 1);//[ 64k] BTCM
|
||||
mpu_config_region_set_mem(cnt++, 0x80000000, REG_16MB, FULL_ACCESS, 0, 0, 0);//[ 32M] DDR_QSPI_NOR_FLASH (support all 8M/16M/32M flash)
|
||||
mpu_config_region_set_mem(cnt++, 0x7E000000, REG_16MB, FULL_ACCESS, 1, 0, 0);//[ 8M] PSRAM_BACKGROUND (support both 8M/16M PSRAM)
|
||||
|
||||
#ifdef SINGLE_SIM
|
||||
mpu_config_region_set_mem(cnt++, 0x7EF60000, REG_128KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE
|
||||
mpu_config_region_set_mem(cnt++, 0x7EF80000, REG_512KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE
|
||||
#else
|
||||
mpu_config_region_set_mem(cnt++, 0x7EF00000, REG_1MB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE
|
||||
#endif
|
||||
/*
|
||||
mpu_config_region_set_dev(region_num, base_address, region_size, shared); */
|
||||
mpu_config_region_set_dev(cnt++, 0xC0000000, REG_1GB, 1); //[ 1G] ASIC_REG_ADDR (force align)
|
||||
mpu_config_region_set_mem(cnt++, 0xD1000000, REG_64KB, FULL_ACCESS, 0, 1, 1);//[ 64K] SQU (non align)
|
||||
#else
|
||||
/*
|
||||
mpu_config_region_set_mem(region_num, base_address, REGION_SIZE, ACCESS_PERMISSION, cacheable, shared, execute_never) */
|
||||
mpu_config_region_set_mem(cnt++, 0x00000000, REG_64KB, READ_ONLY, 0, 0, 0);//[ 64K] ATCM
|
||||
mpu_config_region_set_mem(cnt++, 0xB0020000, REG_64KB, FULL_ACCESS, 0, 0, 1);//[ 64k] BTCM
|
||||
mpu_config_region_set_mem(cnt++, 0x80000000, REG_32MB, FULL_ACCESS, 0, 0, 0);//[ 32M] DDR_QSPI_NOR_FLASH (support all 8M/16M/32M flash)
|
||||
mpu_config_region_set_mem(cnt++, 0x7E000000, REG_16MB, FULL_ACCESS, 1, 0, 0);//[ 16M] PSRAM_BACKGROUND (support both 8M/16M PSRAM)
|
||||
|
||||
#if defined(DM_LTEONLY_16MPSRAM)
|
||||
mpu_config_region_set_mem(cnt++, 0x7E000000, REG_4MB, READ_ONLY, 1, 0, 0);
|
||||
mpu_config_region_set_mem(cnt++, 0x7E400000, REG_1MB, READ_ONLY, 1, 0, 0);//[ 8M] DDR_PSRAM_CODE
|
||||
#else
|
||||
mpu_config_region_set_mem(cnt++, 0x7E000000, REG_8MB, READ_ONLY, 1, 0, 0);
|
||||
mpu_config_region_set_mem(cnt++, 0x7E800000, REG_1MB, READ_ONLY, 1, 0, 0);//[ 8M] DDR_PSRAM_CODE
|
||||
#endif
|
||||
|
||||
mpu_config_region_set_mem(cnt++, 0x7EF00000, REG_1MB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE
|
||||
/*
|
||||
mpu_config_region_set_dev(region_num, base_address, region_size, shared); */
|
||||
mpu_config_region_set_dev(cnt++, 0xC0000000, REG_1GB, 1); //[ 1G] ASIC_REG_ADDR (force align)
|
||||
mpu_config_region_set_mem(cnt++, 0xD1000000, REG_64KB, FULL_ACCESS, 0, 1, 1);//[ 64K] SQU (non align)
|
||||
#endif
|
||||
#else
|
||||
/*
|
||||
mpu_config_region_set_mem(region_num, base_address, REGION_SIZE, ACCESS_PERMISSION, cacheable, shared, execute_never) */
|
||||
mpu_config_region_set_mem(cnt++, 0x00000000, REG_64KB, READ_ONLY, 0, 0, 0);//[ 64K] ATCM
|
||||
mpu_config_region_set_mem(cnt++, 0xB0020000, REG_64KB, FULL_ACCESS, 0, 0, 1);//[ 64k] BTCM
|
||||
mpu_config_region_set_mem(cnt++, 0x80000000, REG_32MB, FULL_ACCESS, 0, 0, 0);//[ 32M] DDR_QSPI_NOR_FLASH (support both 16M/32M flash)
|
||||
mpu_config_region_set_mem(cnt++, 0x7E000000, REG_16MB, FULL_ACCESS, 1, 0, 0);//[ 16M] PSRAM_BACKGROUND
|
||||
#ifdef ENABLE_CAT1_LG
|
||||
mpu_config_region_set_mem(cnt++, 0x7E000000, REG_2MB, READ_ONLY, 1, 0, 0);//[ 3M] DDR_DSP_RO & PS_CRANE_MCU_DONGLE
|
||||
mpu_config_region_set_mem(cnt++, 0x7E200000, REG_1MB, READ_ONLY, 1, 0, 0);
|
||||
#else
|
||||
mpu_config_region_set_mem(cnt++, 0x7E000000, REG_2MB, READ_ONLY, 1, 0, 0);//[2.5M] DDR_DSP_RO & PS_CRANE_MCU_DONGLE
|
||||
mpu_config_region_set_mem(cnt++, 0x7E200000, REG_1MB, READ_ONLY, 1, 0, 0);
|
||||
mpu_config_region_set_mem(cnt++, 0x7E280000, REG_512KB, FULL_ACCESS, 1, 0, 0);
|
||||
#endif
|
||||
|
||||
mpu_config_region_set_mem(cnt++, 0x7EE80000, REG_512KB, FULL_ACCESS, 0, 1, 0);//[1.5M] DDR_NONCACHE
|
||||
mpu_config_region_set_mem(cnt++, 0x7EF00000, REG_1MB, FULL_ACCESS, 0, 1, 0);
|
||||
/*
|
||||
mpu_config_region_set_dev(region_num, base_address, region_size, shared); */
|
||||
mpu_config_region_set_dev(cnt++, 0xC0000000, REG_1GB, 1); //[ 1G] ASIC_REG_ADDR (force align)
|
||||
mpu_config_region_set_mem(cnt++, 0xD1000000, REG_64KB, FULL_ACCESS, 0, 1, 1);//[ 64K] SQU (non align)
|
||||
#endif
|
||||
return (cnt-1);//return configed region count
|
||||
}
|
||||
|
||||
static unsigned int crane_ds_mpu_16M_psram_16M_flash_psram(unsigned int cnt) {
|
||||
/*
|
||||
mpu_config_region_set_mem(region_num, base_address, REGION_SIZE, ACCESS_PERMISSION, cacheable, shared, execute_never) */
|
||||
mpu_config_region_set_mem(cnt++, 0x00000000, REG_64KB, READ_ONLY, 0, 0, 0);//[ 64K] ATCM
|
||||
mpu_config_region_set_mem(cnt++, 0xB0020000, REG_64KB, FULL_ACCESS, 0, 0, 1);//[ 64k] BTCM
|
||||
mpu_config_region_set_mem(cnt++, 0x80000000, REG_32MB, FULL_ACCESS, 0, 0, 0);//[ 32M] DDR_QSPI_NOR_FLASH (support both 16M/32M flash)
|
||||
mpu_config_region_set_mem(cnt++, 0x7E000000, REG_16MB, FULL_ACCESS, 1, 0, 0);//[ 16M] PSRAM_BACKGROUND (support both 8M/16M PSRAM)
|
||||
#ifdef ENABLE_CAT1_LG
|
||||
//TODO:xiaoke for further refine
|
||||
/*
|
||||
mpu_config_region_set_mem(cnt++, 0x7E000000, REG_2MB, READ_ONLY, 0, 0, 1);//[2.25M] DDR_DSP_RO
|
||||
mpu_config_region_set_mem(cnt++, 0x7E200000, REG_256KB, READ_ONLY, 0, 0, 1);//[+256K]
|
||||
*/
|
||||
#else
|
||||
//TODO:xiaoke for further refine
|
||||
/*
|
||||
mpu_config_region_set_mem(cnt++, 0x7E000000, REG_1MB, FULL_ACCESS, 0, 0, 1);//[1.5M] DDR_DSP_RO
|
||||
mpu_config_region_set_mem(cnt++, 0x7E100000, REG_512KB, READ_ONLY, p, 1, 1);
|
||||
*/
|
||||
#endif
|
||||
mpu_config_region_set_mem(cnt++, 0x7EE00000, REG_2MB, FULL_ACCESS, 0, 1, 1);//[1.5M] DDR_NONCACHE
|
||||
mpu_config_region_set_mem(cnt++, 0x7EE00000, REG_512KB, FULL_ACCESS, 1, 0, 0);
|
||||
/*
|
||||
mpu_config_region_set_dev(region_num, base_address, region_size, shared); */
|
||||
mpu_config_region_set_dev(cnt++, 0xC0000000, REG_1GB, 1); //[ 1G] ASIC_REG_ADDR (force align)
|
||||
mpu_config_region_set_mem(cnt++, 0xD1000000, REG_64KB, FULL_ACCESS, 0, 1, 1);//[ 64K] SQU (non align)
|
||||
|
||||
return (cnt-1);//return configed region count
|
||||
}
|
||||
|
||||
|
||||
#if defined(CRANEM_SS_16MRAM)
|
||||
static unsigned int crane_ss_mpu_16M_psram_8M_flash_xip(unsigned int cnt) {
|
||||
/*
|
||||
mpu_config_region_set_mem(region_num, base_address, REGION_SIZE, ACCESS_PERMISSION, cacheable, shared, execute_never) */
|
||||
mpu_config_region_set_mem(cnt++, 0x00000000, REG_64KB, READ_ONLY, 0, 0, 0);//[ 64K] ATCM
|
||||
mpu_config_region_set_mem(cnt++, 0xB0020000, REG_64KB, FULL_ACCESS, 0, 0, 1);//[ 64k] BTCM
|
||||
mpu_config_region_set_mem(cnt++, 0x80000000, REG_32MB, FULL_ACCESS, 0, 0, 0);//[ 32M] DDR_QSPI_NOR_FLASH (support both 16M/32M flash)
|
||||
mpu_config_region_set_mem(cnt++, 0x7E000000, REG_16MB, FULL_ACCESS, 1, 0, 0);//[ 16M] PSRAM_BACKGROUND (support both 8M/16M PSRAM)
|
||||
|
||||
mpu_config_region_set_mem(cnt++, 0x7EF00000, REG_1MB, FULL_ACCESS, 0, 1, 1);//[1.0M] DDR_NONCACHE
|
||||
mpu_config_region_set_mem(cnt++, 0x7EF00000, REG_128KB, FULL_ACCESS, 1, 0, 0);//[256K] DDR_CACHE
|
||||
|
||||
/*
|
||||
mpu_config_region_set_dev(region_num, base_address, region_size, shared); */
|
||||
mpu_config_region_set_dev(cnt++, 0xC0000000, REG_1GB, 1); //[ 1G] ASIC_REG_ADDR (force align)
|
||||
mpu_config_region_set_mem(cnt++, 0xD1000000, REG_64KB, FULL_ACCESS, 0, 1, 1);//[ 64K] SQU (non align)
|
||||
|
||||
return (cnt-1);//return configed region count
|
||||
}
|
||||
#endif
|
||||
|
||||
static unsigned int crane_ds_mpu_8M_psram_8M_flash_xip(unsigned int cnt) {
|
||||
#ifdef CRANE_MCU_DONGLE
|
||||
/*
|
||||
mpu_config_region_set_mem(region_num, base_address, REGION_SIZE, ACCESS_PERMISSION, cacheable, shared, execute_never) */
|
||||
mpu_config_region_set_mem(cnt++, 0x00000000, REG_64KB, READ_ONLY, 0, 0, 0);//[ 64K] ATCM
|
||||
mpu_config_region_set_mem(cnt++, 0xB0020000, REG_64KB, FULL_ACCESS, 0, 0, 1);//[ 64k] BTCM
|
||||
mpu_config_region_set_mem(cnt++, 0x80000000, REG_8MB, FULL_ACCESS, 0, 0, 0);//[ 32M] DDR_QSPI_NOR_FLASH (support all 8M/16M/32M flash)
|
||||
mpu_config_region_set_mem(cnt++, 0x7E000000, REG_8MB, FULL_ACCESS, 1, 0, 0);//[ 8M] PSRAM_BACKGROUND (support both 8M/16M PSRAM)
|
||||
|
||||
#ifdef ASR_PLATFORM_CRANELS//8+8 nocache 配置走else pony add 20230414
|
||||
mpu_config_region_set_mem(cnt++, NOCACHE_STARTADDR_CHECK(0x7E760000), REG_128KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE
|
||||
mpu_config_region_set_mem(cnt++, 0x7E780000, REG_512KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE
|
||||
#elif defined(LTEGSM_THIN) //1603c
|
||||
mpu_config_region_set_mem(cnt++, NOCACHE_STARTADDR_CHECK(0x7E720000), REG_128KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE
|
||||
mpu_config_region_set_mem(cnt++, 0x7E740000, REG_256KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE
|
||||
mpu_config_region_set_mem(cnt++, 0x7E780000, REG_512KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE
|
||||
#else //1606
|
||||
//For 1606 8+8 项目，R07 SDK
|
||||
mpu_config_region_set_mem(cnt++, NOCACHE_STARTADDR_CHECK(0x7E700000), REG_1MB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE
|
||||
#endif
|
||||
/*
|
||||
mpu_config_region_set_dev(region_num, base_address, region_size, shared); */
|
||||
mpu_config_region_set_dev(cnt++, 0xC0000000, REG_1GB, 1); //[ 1G] ASIC_REG_ADDR (force align)
|
||||
mpu_config_region_set_mem(cnt++, 0xD1000000, REG_64KB, FULL_ACCESS, 0, 1, 1);//[ 64K] SQU (non align)
|
||||
|
||||
#else
|
||||
/*
|
||||
mpu_config_region_set_mem(region_num, base_address, REGION_SIZE, ACCESS_PERMISSION, cacheable, shared, execute_never) */
|
||||
mpu_config_region_set_mem(cnt++, 0x00000000, REG_64KB, READ_ONLY, 0, 0, 0);//[ 64K] ATCM
|
||||
mpu_config_region_set_mem(cnt++, 0xB0020000, REG_64KB, FULL_ACCESS, 0, 0, 1);//[ 64k] BTCM
|
||||
mpu_config_region_set_mem(cnt++, 0x80000000, REG_32MB, FULL_ACCESS, 0, 0, 0);//[ 32M] DDR_QSPI_NOR_FLASH (support all 8M/16M/32M flash)
|
||||
mpu_config_region_set_mem(cnt++, 0x7E000000, REG_16MB, FULL_ACCESS, 1, 0, 0);//[ 16M] PSRAM_BACKGROUND (support both 8M/16M PSRAM)
|
||||
|
||||
mpu_config_region_set_mem(cnt++, 0x7E180000, REG_512KB, READ_ONLY, 1, 0, 0);//[+512K] DDR_PSRAM_CODE
|
||||
mpu_config_region_set_mem(cnt++, 0x7E200000, REG_512KB, READ_ONLY, 1, 0, 0);//[+512K]
|
||||
mpu_config_region_set_mem(cnt++, 0x7E680000, REG_512KB, FULL_ACCESS, 0, 1, 0);//[+ 512K] DDR_NONCACHE
|
||||
|
||||
mpu_config_region_set_mem(cnt++, 0x7E700000, REG_1MB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE
|
||||
|
||||
mpu_config_region_set_mem(cnt++, 0x7E000000, REG_1MB, READ_ONLY, 0, 1, 1);//[1.5M] DDR_DSP_RO
|
||||
mpu_config_region_set_mem(cnt++, 0x7E100000, REG_512KB, READ_ONLY, 0, 1, 1);
|
||||
|
||||
/*
|
||||
mpu_config_region_set_dev(region_num, base_address, region_size, shared); */
|
||||
mpu_config_region_set_dev(cnt++, 0xC0000000, REG_1GB, 1); //[ 1G] ASIC_REG_ADDR (force align)
|
||||
mpu_config_region_set_mem(cnt++, 0xD1000000, REG_64KB, FULL_ACCESS, 0, 1, 1);//[ 64K] SQU (non align)
|
||||
#endif
|
||||
return (cnt-1);//return configed region count
|
||||
}
|
||||
|
||||
static unsigned int crane_ds_mpu_4M_psram_4M_flash_xip(unsigned int cnt) {
|
||||
#ifdef CRANE_MCU_DONGLE
|
||||
/*
|
||||
mpu_config_region_set_mem(region_num, base_address, REGION_SIZE, ACCESS_PERMISSION, cacheable, shared, execute_never) */
|
||||
mpu_config_region_set_mem(cnt++, 0x00000000, REG_64KB, READ_ONLY, 0, 0, 0);//[ 64K] ATCM
|
||||
mpu_config_region_set_mem(cnt++, 0xB0020000, REG_64KB, FULL_ACCESS, 0, 0, 1);//[ 64k] BTCM
|
||||
mpu_config_region_set_mem(cnt++, 0x80000000, REG_32MB, FULL_ACCESS, 0, 0, 0);//[ 32M] DDR_QSPI_NOR_FLASH (support all 8M/16M/32M flash)
|
||||
mpu_config_region_set_mem(cnt++, 0x7E000000, REG_4MB, FULL_ACCESS, 1, 0, 0);//[ 4M] PSRAM_BACKGROUND (support both 8M/16M PSRAM)
|
||||
|
||||
//Sharon.li@20230411 OPEN版本4+4和2+4的项目单卡的基线NOCACHE分区起始地址一样
|
||||
#ifdef SINGLE_SIM
|
||||
#ifdef QUECTEL_USBNET_SUPPORT
|
||||
//for 1602 2+4 And 4+4 项目,支持USBNET的IPC行业版本
|
||||
mpu_config_region_set_mem(cnt++, NOCACHE_STARTADDR_CHECK(0x7E36A000), REG_8KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE
|
||||
mpu_config_region_set_mem(cnt++, 0x7E368000, REG_32KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE
|
||||
mpu_config_region_set_mem(cnt++, 0x7E370000, REG_64KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE
|
||||
mpu_config_region_set_mem(cnt++, 0x7E380000, REG_512KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE
|
||||
#else
|
||||
//for 1602/1606 2+4 And 4+4 项目
|
||||
mpu_config_region_set_mem(cnt++, NOCACHE_STARTADDR_CHECK(0x7E370000), REG_64KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE
|
||||
mpu_config_region_set_mem(cnt++, 0x7E380000, REG_512KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE
|
||||
#endif
|
||||
#endif
|
||||
/*
|
||||
mpu_config_region_set_dev(region_num, base_address, region_size, shared); */
|
||||
mpu_config_region_set_dev(cnt++, 0xC0000000, REG_1GB, 1); //[ 1G] ASIC_REG_ADDR (force align)
|
||||
mpu_config_region_set_mem(cnt++, 0xD1000000, REG_64KB, FULL_ACCESS, 0, 1, 1);//[ 64K] SQU (non align)
|
||||
|
||||
#endif
|
||||
return (cnt-1);//return configed region count
|
||||
}
|
||||
|
||||
|
||||
//xiaokeweng@20191008 flash cache_line auto config
|
||||
//for partition table , the XIP code part should be cacheable
|
||||
//but the NVM/factory/fota_pkg should always be noncache ,
|
||||
//so implement solution to detect the cache_line address
|
||||
//aligned inside [dsp_start_addr ~ reserved_end_addr] for C-code MPU audo reconfig
|
||||
|
||||
#define CACHELINE_ALIGN_REGION_SIZE(REG_N) (2 << REG_N)
|
||||
|
||||
static unsigned int crane_ds_mpu_flash_noncache_line_auto_mpu(unsigned int cnt){
|
||||
|
||||
//ptable fetch noncache_line area [dsp.bin.start ~ reserved.end]
|
||||
unsigned int dsp_start_addr = get_dsp_start_address_offset();
|
||||
#ifdef QUECTEL_OPEN_CPU
|
||||
/*以app结束地址为cache结束地址*/
|
||||
unsigned int reserved_end_addr = get_flash_cache_end_address_offset();
|
||||
#else
|
||||
unsigned int reserved_end_addr = get_reserved_end_address_offset();
|
||||
#endif
|
||||
|
||||
unsigned int cache_line_max = reserved_end_addr;
|
||||
unsigned int cache_line_min = dsp_start_addr;
|
||||
unsigned int cache_line = 0;
|
||||
|
||||
unsigned int tmp_addr = cache_line_max;
|
||||
unsigned int tmp_align= REG_16MB;
|
||||
unsigned int min_align= REG_1MB;
|
||||
unsigned int mpu_num= 0;
|
||||
|
||||
if(is_partition_internal_flash("nvm")){
|
||||
mpu_config_region_set_mem(++cnt, 0x80000000, REG_32MB, FULL_ACCESS, 1, 0, 0);
|
||||
}else{
|
||||
RTI_LOG("[MPU] cache_line_max = [0x%0.8x], cache_line_min = [0x%0.8x]\r\n",cache_line_max,cache_line_min);
|
||||
|
||||
#if (defined(CRANEL_4MRAM) || defined(CRANEL_8MRAM))
|
||||
min_align = REG_4KB;
|
||||
#endif
|
||||
#ifdef QUECTEL_OPEN_CPU
|
||||
while(!(cache_line > cache_line_max) && (tmp_align >= min_align)) { // open 配置到app_end前
|
||||
#else
|
||||
//while(!(cache_line >= cache_line_min && cache_line <= cache_line_max) && (tmp_align >= min_align)) {
|
||||
#endif
|
||||
RTI_LOG("[MPU] tmp_addr = [0x%0.8x],CACHELINE_ALIGN_REGION_SIZE(tmp_align) = [0x%0.8x] , add/align=[%d]\r\n"
|
||||
,tmp_addr
|
||||
,CACHELINE_ALIGN_REGION_SIZE(tmp_align)
|
||||
,tmp_addr/CACHELINE_ALIGN_REGION_SIZE(tmp_align));
|
||||
|
||||
if(tmp_addr/CACHELINE_ALIGN_REGION_SIZE(tmp_align) == 1){
|
||||
|
||||
//update tmp_addr
|
||||
tmp_addr -= CACHELINE_ALIGN_REGION_SIZE(tmp_align);
|
||||
|
||||
//reconfig mpu
|
||||
//mpu_config_region_set_mem(region_num, base_address, REGION_SIZE, ACCESS_PERMISSION, cacheable, shared, execute_never)
|
||||
mpu_config_region_set_mem(++cnt, 0x80000000+cache_line, (region_size)tmp_align, FULL_ACCESS, 1, 0, 0);//RO cacheable code onside flash
|
||||
|
||||
//update cache_line
|
||||
cache_line += CACHELINE_ALIGN_REGION_SIZE(tmp_align);
|
||||
|
||||
RTI_LOG("[MPU] cnt=[%0.2d],tmp_align=[0x%0.2x],CACHELINE_ALIGN_REGION_SIZE(tmp_align) = [0x%0.8x],cache_line = [0x%0.8x]\r\n"
|
||||
,cnt
|
||||
,tmp_align
|
||||
,CACHELINE_ALIGN_REGION_SIZE(tmp_align)
|
||||
,cache_line);
|
||||
}
|
||||
#ifdef QUECTEL_OPEN_CPU
|
||||
if(cnt>=14){
|
||||
//mpu region cnt at[0-14],cnt 15 should be used by ASR,if cnt exceed 14 will happen assert!
|
||||
RTI_LOG("MPU[%d] num error!", cnt);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
//update tmp_align
|
||||
tmp_align -= 0x01;
|
||||
}
|
||||
}
|
||||
|
||||
if(cnt>=15){
|
||||
//mpu region cnt at[0-14],cnt 15 should be used by ASR,if cnt exceed 14 will happen assert!
|
||||
RTI_LOG("MPU[%d] num error!", cnt);
|
||||
ASSERT(0);
|
||||
}
|
||||
|
||||
//reset unused mpu region
|
||||
mpu_num = cnt;
|
||||
while(mpu_num<15){
|
||||
mpu_config_region_set_mem(++mpu_num, 0x00000000, 0x00, NO_ACCESS, 1, 0, 0);
|
||||
}
|
||||
|
||||
return (cnt);
|
||||
}
|
||||
|
||||
void crane_ds_mpu(void) {
|
||||
unsigned int cnt ;
|
||||
//uart_printf("[MPU] function:%s,line:%d\r\n", __func__,__LINE__);
|
||||
|
||||
CPUartLogPrintf("Crane mpu configure");
|
||||
|
||||
//step1:entry action, disable I/D cache,set 4G FULL_ACCESS background on region BACKGROUND_REGION
|
||||
mpu_config_entry_action();
|
||||
|
||||
//step2:config and enable project mpu , start from (BACKGROUND_REGION+1)
|
||||
cnt = (BACKGROUND_REGION + 1);
|
||||
#ifdef RUN_XIP_MODE
|
||||
#if defined(CRANEM_8MRAM) || defined(_8MNORFLASH) || defined(LTEONLY_8M8M) || defined(LTEGSM_THIN)//8M_FLASH
|
||||
#if defined(CRANELS_16M16M)
|
||||
cnt = crane_ds_mpu_16M_psram_16M_flash_xip(cnt);
|
||||
#elif defined(CRANEM_SS_16MRAM)
|
||||
cnt = crane_ss_mpu_16M_psram_8M_flash_xip(cnt);
|
||||
#else
|
||||
cnt = crane_ds_mpu_8M_psram_8M_flash_xip(cnt);
|
||||
#endif
|
||||
#elif defined(CRANEL_4MRAM)
|
||||
cnt = crane_ds_mpu_4M_psram_4M_flash_xip(cnt);
|
||||
#else
|
||||
cnt = crane_ds_mpu_16M_psram_16M_flash_xip(cnt);
|
||||
#endif
|
||||
#else
|
||||
cnt = crane_ds_mpu_16M_psram_16M_flash_psram(cnt);
|
||||
#endif
|
||||
cnt = crane_ds_mpu_flash_noncache_line_auto_mpu(cnt);
|
||||
|
||||
//step3:exit action, enable I/D cache,enable 4G NO_ACCESS background on region BACKGROUND_REGION
|
||||
mpu_config_exit_action();
|
||||
|
||||
region_cnt = cnt;
|
||||
|
||||
crane_ds_mpu_xip_enable(TRUE);
|
||||
|
||||
//step4:uart dump configed mpu region
|
||||
mpu_config_uart_dump(15);
|
||||
|
||||
//uart_printf("[MPU] function:%s,line:%d\r\n", __func__,__LINE__);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void crane_ds_mpu_xip_enable(bool enable)
|
||||
{
|
||||
if(enable)
|
||||
{
|
||||
mpu_config_region_set_mem(15, 0x80000000, 0x00, NO_ACCESS, 1, 0, TRUE);
|
||||
}
|
||||
else
|
||||
{
|
||||
mpu_config_region_set_mem(15, 0x80000000, REG_32MB, NO_ACCESS, 1, 0, TRUE);
|
||||
}
|
||||
|
||||
if(!SysIsAssert())
|
||||
{
|
||||
xip_access_enable = enable;
|
||||
}
|
||||
}
|
||||
void crane_ds_mpu_xip_cache_enable(void)
|
||||
{
|
||||
mpu_config_region_set_mem(15, 0x80000000, 0x00, FULL_ACCESS, 0, 0, 0);
|
||||
}
|
||||
|
||||
void crane_ds_mpu_xip_cache_disable(void)
|
||||
{
|
||||
mpu_config_region_set_mem(15, 0x80000000, REG_32MB, FULL_ACCESS, 0, 0, 0);
|
||||
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,155 @@
|
||||
/*==========================================================================================================
|
||||
Copyright (c) 2021, Quectel Wireless Solutions Co., Ltd. All rights reserved.
|
||||
Quectel Wireless Solutions Proprietary and Confidential.
|
||||
===========================================================================================================*/
|
||||
|
||||
/*==========================================================================================================
|
||||
|
||||
EDIT HISTORY FOR MODULE
|
||||
|
||||
This section contains comments describing changes made to the module.
|
||||
Notice that changes are listed in reverse chronological order.
|
||||
|
||||
WHEN WHO WHAT, WHERE, WHY
|
||||
------------ ------- -------------------------------------------------------------------------------
|
||||
09/04/2022 Pony.Ma 此文件服务内核加载APP，进行APP的 RO/RW/BSS的加载和初始化
|
||||
|
||||
09/04/2022 Sharon.li 在内核跳转APP之前，进行用户fs的挂载和初始化
|
||||
===========================================================================================================*/
|
||||
/*ASR 头文件*/
|
||||
#include "global_types.h"
|
||||
#include "utilities.h"
|
||||
#include "ptable.h"
|
||||
#include "csw_mem.h"
|
||||
#include "main.h"
|
||||
#include "LzmaLib.h"
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include "ql_ocpu_api.h"
|
||||
#include "ql_appinit.h"
|
||||
#include "quec_fs.h"
|
||||
#include "quec_spi_nor.h"
|
||||
#include "lfs_cache.h"
|
||||
#include "loadTable.h"
|
||||
#include "quec_init.h"
|
||||
|
||||
/*----------- External include files -----------------------------------------*/
|
||||
#if defined(__arm)
|
||||
#include <locale.h>
|
||||
#endif
|
||||
|
||||
#ifdef QUECTEL_OPEN_CPU
|
||||
|
||||
#define QUEC_OPEN_APP_BACKUP 1 /*APP备份功能 0:关闭，1:开启 */
|
||||
int quec_app_backup_enable = QUEC_OPEN_APP_BACKUP;
|
||||
|
||||
#ifdef QUEC_NORFLASH_ERASE_OPTIMIZE
|
||||
//用户补擦区域数组，默认开启customer_fs分区补擦，分区名字符串长度必须小于16
|
||||
const char USER_ERASE_RECORD_AREA[2][16]={"customer_fs", {0}};
|
||||
#endif
|
||||
|
||||
/***********************************************************************
|
||||
*
|
||||
* Name:
|
||||
*
|
||||
* Description: 将app镜像拷贝到执行位置，如果是ramapp则将正ro+rw拷贝到ram_addr
|
||||
* 若是xipapp则只会将 rw拷贝到ram_addr
|
||||
*
|
||||
* Parameters: app_name app分区名；ram_addr appram地址
|
||||
*
|
||||
* Returns:
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
***********************************************************************/
|
||||
extern int copy_customer_app_from_flash_to_psram(char *app_name,unsigned int ram_addr);
|
||||
#ifdef QUEC_APP_FULL_FOTA
|
||||
extern BOOL IsFullfota_app(void);
|
||||
#endif
|
||||
void ql_boot(void);
|
||||
|
||||
|
||||
void ql_app_start_prepare(void)
|
||||
{
|
||||
#ifdef QUEC_APP_FULL_FOTA
|
||||
if(!IsFullfota_app())
|
||||
#endif
|
||||
{
|
||||
if(copy_customer_app_from_flash_to_psram("customer_app",(unsigned int)QUECTEL_OPEN_CPU_ENTRY)){
|
||||
//uart_printf("file:%s,function:%s,line:%d\r\n", __FILE__,__func__,__LINE__);
|
||||
ASSERT(0);
|
||||
}
|
||||
ql_boot();
|
||||
}
|
||||
}
|
||||
|
||||
void ql_boot(void)
|
||||
{
|
||||
ql_boot_2("customer_app",(unsigned int)QUECTEL_OPEN_CPU_ENTRY);
|
||||
}
|
||||
|
||||
void ql_kernel(void)
|
||||
{
|
||||
_ptentry* partition_entrance = NULL;
|
||||
|
||||
partition_entrance = ptable_find_entry("customer_fs");
|
||||
quec_app_log("0x%x , 0x%x",partition_entrance->vstart,partition_entrance->vstart & 0x80000000);
|
||||
//挂载文件系统
|
||||
#ifdef EXTERNAL_SPI_NORFLASH_FS
|
||||
if(partition_entrance->vstart >= 0x90000000){
|
||||
extern int quec_get_extflash_select_port(void);
|
||||
int port=quec_get_extflash_select_port();
|
||||
quec_app_log("SPI FS ADDR:0X%08x SIZE:0x%x",partition_entrance->start,partition_entrance->size);
|
||||
qextfs_init(U_DISK_SYM, "customer_fs",0,port, partition_entrance->start, partition_entrance->size);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
qfs_init(U_DISK_SYM, "customer_fs", 0);
|
||||
}
|
||||
#ifdef QUECTEL_OPEN_CPU //增加open项目在fs中配置audio参数文件功能
|
||||
#ifndef NO_AUDIO
|
||||
extern void ql_update_audio_parameters(void);
|
||||
ql_update_audio_parameters();
|
||||
|
||||
#if defined(ASR_PLATFORM_CRANELR) || defined(ASR_PLATFORM_CRANELRH)
|
||||
#include "AudioHAL.h"
|
||||
#if defined (__QUECTEL_PROJECT_EC600KCN_LC__) || defined(__QUECTEL_PROJECT_EC600KCN_CC__) || defined (__QUECTEL_PROJECT_EC600KCN_MC__)\
|
||||
|| defined(__QUECTEL_PROJECT_EC600KCN_LK__)|| defined(__QUECTEL_PROJECT_EC600KCN_CK__) || defined(__QUECTEL_PROJECT_EG600AKCN_91LC__)\
|
||||
|| defined(__QUECTEL_PROJECT_EG600AKCN_11LC__)|| defined(__QUECTEL_PROJECT_EG600AKCN_11LG__)
|
||||
AudioHAL_AifSetDevicePort(AUDIOHAL_PORT_SSP2);
|
||||
#elif defined(__QUECTEL_PROJECT_EC800KCN_LC__) || defined(__QUECTEL_PROJECT_EC800KCN_CC__) || defined(__QUECTEL_PROJECT_EG800KCN_GC__)\
|
||||
|| defined(__QUECTEL_PROJECT_EG800KEU_CC__)|| defined (__QUECTEL_PROJECT_EC800KCN_MD__) || defined(__QUECTEL_PROJECT_EC800KCN_MC__)\
|
||||
|| defined (__QUECTEL_PROJECT_EG800KLA_LC__) || defined (__QUECTEL_PROJECT_EG800KEU_LC__)|| defined (__QUECTEL_PROJECT_EG800KLA_CC__)\
|
||||
|| defined (__QUECTEL_PROJECT_EC800KCN_LK__)|| defined (__QUECTEL_PROJECT_EC800KCN_CK__)|| defined (__QUECTEL_PROJECT_EG915KEU_LA__) \
|
||||
|| defined (__QUECTEL_PROJECT_EG800AKCN_91LC__)|| defined (__QUECTEL_PROJECT_EG915KEU_LC__) || defined (__QUECTEL_PROJECT_EG915KEU_LG__)\
|
||||
|| defined (__QUECTEL_PROJECT_EG800AKEU_11LC__)|| defined (__QUECTEL_PROJECT_EG800AKEU_11LG__)|| defined (__QUECTEL_PROJECT_EG800AKLA_11LC__)\
|
||||
|| defined (__QUECTEL_PROJECT_EG800AKCN_11LN__)|| defined (__QUECTEL_PROJECT_EG915KLA_LC__)|| defined (__QUECTEL_PROJECT_EG915KLA_LA__)\
|
||||
|| defined (__QUECTEL_PROJECT_EG800AKLA_11LG__)
|
||||
AudioHAL_AifSetDevicePort(AUDIOHAL_PORT_SSP1);
|
||||
#endif
|
||||
quec_app_log("used audio port %d",AudioHAL_AifGetDevicePort());
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#ifdef QUEC_APP_FULL_FOTA
|
||||
if(!IsFullfota_app())
|
||||
#endif
|
||||
ql_kernel_2("customer_app",(unsigned int)QUECTEL_OPEN_CPU_ENTRY);
|
||||
|
||||
}
|
||||
|
||||
|
||||
void ql_main(void * argv)
|
||||
{
|
||||
ql_main_2("customer_app",(unsigned int)QUECTEL_OPEN_CPU_ENTRY);
|
||||
quec_rtos_task_delete_ex(NULL);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user