#include "bsp.h" #include "crane_ds_mpu.h" #include "loadTable.h" #include "UART.h" unsigned int region_cnt = 0; BOOL xip_access_enable = TRUE; #ifdef QUECTEL_PROJECT_CUST extern unsigned int Image$$DDR_NONCACHE_REGION_ACIPC_PS_UL$$Base; unsigned int quec_nocache_start_check(unsigned int addr) { if((unsigned int)(&Image$$DDR_NONCACHE_REGION_ACIPC_PS_UL$$Base) != addr){ RTI_LOG("mpu_error %s %s,0x%x,0x%x",__FILE__,__LINE__,(unsigned int)(&Image$$DDR_NONCACHE_REGION_ACIPC_PS_UL$$Base),addr); ASSERT(0) } return addr; } #define NOCACHE_STARTADDR_CHECK(ADDR) quec_nocache_start_check(ADDR) #endif static unsigned int crane_ds_mpu_16M_psram_16M_flash_xip(unsigned int cnt) { #ifdef CRANE_MCU_DONGLE #ifdef CRANELS_16M16M /* mpu_config_region_set_mem(region_num, base_address, REGION_SIZE, ACCESS_PERMISSION, cacheable, shared, execute_never) */ mpu_config_region_set_mem(cnt++, 0x00000000, REG_64KB, READ_ONLY, 0, 0, 0);//[ 64K] ATCM mpu_config_region_set_mem(cnt++, 0xB0020000, REG_64KB, FULL_ACCESS, 0, 0, 1);//[ 64k] BTCM mpu_config_region_set_mem(cnt++, 0x80000000, REG_16MB, FULL_ACCESS, 0, 0, 0);//[ 32M] DDR_QSPI_NOR_FLASH (support all 8M/16M/32M flash) mpu_config_region_set_mem(cnt++, 0x7E000000, REG_16MB, FULL_ACCESS, 1, 0, 0);//[ 8M] PSRAM_BACKGROUND (support both 8M/16M PSRAM) #ifdef SINGLE_SIM mpu_config_region_set_mem(cnt++, 0x7EF60000, REG_128KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE mpu_config_region_set_mem(cnt++, 0x7EF80000, REG_512KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE #else mpu_config_region_set_mem(cnt++, 0x7EF00000, REG_1MB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE #endif /* mpu_config_region_set_dev(region_num, base_address, region_size, shared); */ mpu_config_region_set_dev(cnt++, 0xC0000000, REG_1GB, 1); //[ 1G] ASIC_REG_ADDR (force align) mpu_config_region_set_mem(cnt++, 0xD1000000, REG_64KB, FULL_ACCESS, 0, 1, 1);//[ 64K] SQU (non align) #else /* mpu_config_region_set_mem(region_num, base_address, REGION_SIZE, ACCESS_PERMISSION, cacheable, shared, execute_never) */ mpu_config_region_set_mem(cnt++, 0x00000000, REG_64KB, READ_ONLY, 0, 0, 0);//[ 64K] ATCM mpu_config_region_set_mem(cnt++, 0xB0020000, REG_64KB, FULL_ACCESS, 0, 0, 1);//[ 64k] BTCM mpu_config_region_set_mem(cnt++, 0x80000000, REG_32MB, FULL_ACCESS, 0, 0, 0);//[ 32M] DDR_QSPI_NOR_FLASH (support all 8M/16M/32M flash) mpu_config_region_set_mem(cnt++, 0x7E000000, REG_16MB, FULL_ACCESS, 1, 0, 0);//[ 16M] PSRAM_BACKGROUND (support both 8M/16M PSRAM) #if defined(DM_LTEONLY_16MPSRAM) mpu_config_region_set_mem(cnt++, 0x7E000000, REG_4MB, READ_ONLY, 1, 0, 0); mpu_config_region_set_mem(cnt++, 0x7E400000, REG_1MB, READ_ONLY, 1, 0, 0);//[ 8M] DDR_PSRAM_CODE #else mpu_config_region_set_mem(cnt++, 0x7E000000, REG_8MB, READ_ONLY, 1, 0, 0); mpu_config_region_set_mem(cnt++, 0x7E800000, REG_1MB, READ_ONLY, 1, 0, 0);//[ 8M] DDR_PSRAM_CODE #endif mpu_config_region_set_mem(cnt++, 0x7EF00000, REG_1MB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE /* mpu_config_region_set_dev(region_num, base_address, region_size, shared); */ mpu_config_region_set_dev(cnt++, 0xC0000000, REG_1GB, 1); //[ 1G] ASIC_REG_ADDR (force align) mpu_config_region_set_mem(cnt++, 0xD1000000, REG_64KB, FULL_ACCESS, 0, 1, 1);//[ 64K] SQU (non align) #endif #else /* mpu_config_region_set_mem(region_num, base_address, REGION_SIZE, ACCESS_PERMISSION, cacheable, shared, execute_never) */ mpu_config_region_set_mem(cnt++, 0x00000000, REG_64KB, READ_ONLY, 0, 0, 0);//[ 64K] ATCM mpu_config_region_set_mem(cnt++, 0xB0020000, REG_64KB, FULL_ACCESS, 0, 0, 1);//[ 64k] BTCM mpu_config_region_set_mem(cnt++, 0x80000000, REG_32MB, FULL_ACCESS, 0, 0, 0);//[ 32M] DDR_QSPI_NOR_FLASH (support both 16M/32M flash) mpu_config_region_set_mem(cnt++, 0x7E000000, REG_16MB, FULL_ACCESS, 1, 0, 0);//[ 16M] PSRAM_BACKGROUND #ifdef ENABLE_CAT1_LG mpu_config_region_set_mem(cnt++, 0x7E000000, REG_2MB, READ_ONLY, 1, 0, 0);//[ 3M] DDR_DSP_RO & PS_CRANE_MCU_DONGLE mpu_config_region_set_mem(cnt++, 0x7E200000, REG_1MB, READ_ONLY, 1, 0, 0); #else mpu_config_region_set_mem(cnt++, 0x7E000000, REG_2MB, READ_ONLY, 1, 0, 0);//[2.5M] DDR_DSP_RO & PS_CRANE_MCU_DONGLE mpu_config_region_set_mem(cnt++, 0x7E200000, REG_1MB, READ_ONLY, 1, 0, 0); mpu_config_region_set_mem(cnt++, 0x7E280000, REG_512KB, FULL_ACCESS, 1, 0, 0); #endif mpu_config_region_set_mem(cnt++, 0x7EE80000, REG_512KB, FULL_ACCESS, 0, 1, 0);//[1.5M] DDR_NONCACHE mpu_config_region_set_mem(cnt++, 0x7EF00000, REG_1MB, FULL_ACCESS, 0, 1, 0); /* mpu_config_region_set_dev(region_num, base_address, region_size, shared); */ mpu_config_region_set_dev(cnt++, 0xC0000000, REG_1GB, 1); //[ 1G] ASIC_REG_ADDR (force align) mpu_config_region_set_mem(cnt++, 0xD1000000, REG_64KB, FULL_ACCESS, 0, 1, 1);//[ 64K] SQU (non align) #endif return (cnt-1);//return configed region count } static unsigned int crane_ds_mpu_16M_psram_16M_flash_psram(unsigned int cnt) { /* mpu_config_region_set_mem(region_num, base_address, REGION_SIZE, ACCESS_PERMISSION, cacheable, shared, execute_never) */ mpu_config_region_set_mem(cnt++, 0x00000000, REG_64KB, READ_ONLY, 0, 0, 0);//[ 64K] ATCM mpu_config_region_set_mem(cnt++, 0xB0020000, REG_64KB, FULL_ACCESS, 0, 0, 1);//[ 64k] BTCM mpu_config_region_set_mem(cnt++, 0x80000000, REG_32MB, FULL_ACCESS, 0, 0, 0);//[ 32M] DDR_QSPI_NOR_FLASH (support both 16M/32M flash) mpu_config_region_set_mem(cnt++, 0x7E000000, REG_16MB, FULL_ACCESS, 1, 0, 0);//[ 16M] PSRAM_BACKGROUND (support both 8M/16M PSRAM) #ifdef ENABLE_CAT1_LG //TODO:xiaoke for further refine /* mpu_config_region_set_mem(cnt++, 0x7E000000, REG_2MB, READ_ONLY, 0, 0, 1);//[2.25M] DDR_DSP_RO mpu_config_region_set_mem(cnt++, 0x7E200000, REG_256KB, READ_ONLY, 0, 0, 1);//[+256K] */ #else //TODO:xiaoke for further refine /* mpu_config_region_set_mem(cnt++, 0x7E000000, REG_1MB, FULL_ACCESS, 0, 0, 1);//[1.5M] DDR_DSP_RO mpu_config_region_set_mem(cnt++, 0x7E100000, REG_512KB, READ_ONLY, p, 1, 1); */ #endif mpu_config_region_set_mem(cnt++, 0x7EE00000, REG_2MB, FULL_ACCESS, 0, 1, 1);//[1.5M] DDR_NONCACHE mpu_config_region_set_mem(cnt++, 0x7EE00000, REG_512KB, FULL_ACCESS, 1, 0, 0); /* mpu_config_region_set_dev(region_num, base_address, region_size, shared); */ mpu_config_region_set_dev(cnt++, 0xC0000000, REG_1GB, 1); //[ 1G] ASIC_REG_ADDR (force align) mpu_config_region_set_mem(cnt++, 0xD1000000, REG_64KB, FULL_ACCESS, 0, 1, 1);//[ 64K] SQU (non align) return (cnt-1);//return configed region count } #if defined(CRANEM_SS_16MRAM) static unsigned int crane_ss_mpu_16M_psram_8M_flash_xip(unsigned int cnt) { /* mpu_config_region_set_mem(region_num, base_address, REGION_SIZE, ACCESS_PERMISSION, cacheable, shared, execute_never) */ mpu_config_region_set_mem(cnt++, 0x00000000, REG_64KB, READ_ONLY, 0, 0, 0);//[ 64K] ATCM mpu_config_region_set_mem(cnt++, 0xB0020000, REG_64KB, FULL_ACCESS, 0, 0, 1);//[ 64k] BTCM mpu_config_region_set_mem(cnt++, 0x80000000, REG_32MB, FULL_ACCESS, 0, 0, 0);//[ 32M] DDR_QSPI_NOR_FLASH (support both 16M/32M flash) mpu_config_region_set_mem(cnt++, 0x7E000000, REG_16MB, FULL_ACCESS, 1, 0, 0);//[ 16M] PSRAM_BACKGROUND (support both 8M/16M PSRAM) mpu_config_region_set_mem(cnt++, 0x7EF00000, REG_1MB, FULL_ACCESS, 0, 1, 1);//[1.0M] DDR_NONCACHE mpu_config_region_set_mem(cnt++, 0x7EF00000, REG_128KB, FULL_ACCESS, 1, 0, 0);//[256K] DDR_CACHE /* mpu_config_region_set_dev(region_num, base_address, region_size, shared); */ mpu_config_region_set_dev(cnt++, 0xC0000000, REG_1GB, 1); //[ 1G] ASIC_REG_ADDR (force align) mpu_config_region_set_mem(cnt++, 0xD1000000, REG_64KB, FULL_ACCESS, 0, 1, 1);//[ 64K] SQU (non align) return (cnt-1);//return configed region count } #endif static unsigned int crane_ds_mpu_8M_psram_8M_flash_xip(unsigned int cnt) { #ifdef CRANE_MCU_DONGLE /* mpu_config_region_set_mem(region_num, base_address, REGION_SIZE, ACCESS_PERMISSION, cacheable, shared, execute_never) */ mpu_config_region_set_mem(cnt++, 0x00000000, REG_64KB, READ_ONLY, 0, 0, 0);//[ 64K] ATCM mpu_config_region_set_mem(cnt++, 0xB0020000, REG_64KB, FULL_ACCESS, 0, 0, 1);//[ 64k] BTCM mpu_config_region_set_mem(cnt++, 0x80000000, REG_8MB, FULL_ACCESS, 0, 0, 0);//[ 32M] DDR_QSPI_NOR_FLASH (support all 8M/16M/32M flash) mpu_config_region_set_mem(cnt++, 0x7E000000, REG_8MB, FULL_ACCESS, 1, 0, 0);//[ 8M] PSRAM_BACKGROUND (support both 8M/16M PSRAM) #ifdef ASR_PLATFORM_CRANELS//8+8 nocache 配置走else pony add 20230414 mpu_config_region_set_mem(cnt++, NOCACHE_STARTADDR_CHECK(0x7E760000), REG_128KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE mpu_config_region_set_mem(cnt++, 0x7E780000, REG_512KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE #elif defined(LTEGSM_THIN) //1603c mpu_config_region_set_mem(cnt++, NOCACHE_STARTADDR_CHECK(0x7E720000), REG_128KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE mpu_config_region_set_mem(cnt++, 0x7E740000, REG_256KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE mpu_config_region_set_mem(cnt++, 0x7E780000, REG_512KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE #else //1606 //For 1606 8+8 项目，R07 SDK mpu_config_region_set_mem(cnt++, NOCACHE_STARTADDR_CHECK(0x7E700000), REG_1MB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE #endif /* mpu_config_region_set_dev(region_num, base_address, region_size, shared); */ mpu_config_region_set_dev(cnt++, 0xC0000000, REG_1GB, 1); //[ 1G] ASIC_REG_ADDR (force align) mpu_config_region_set_mem(cnt++, 0xD1000000, REG_64KB, FULL_ACCESS, 0, 1, 1);//[ 64K] SQU (non align) #else /* mpu_config_region_set_mem(region_num, base_address, REGION_SIZE, ACCESS_PERMISSION, cacheable, shared, execute_never) */ mpu_config_region_set_mem(cnt++, 0x00000000, REG_64KB, READ_ONLY, 0, 0, 0);//[ 64K] ATCM mpu_config_region_set_mem(cnt++, 0xB0020000, REG_64KB, FULL_ACCESS, 0, 0, 1);//[ 64k] BTCM mpu_config_region_set_mem(cnt++, 0x80000000, REG_32MB, FULL_ACCESS, 0, 0, 0);//[ 32M] DDR_QSPI_NOR_FLASH (support all 8M/16M/32M flash) mpu_config_region_set_mem(cnt++, 0x7E000000, REG_16MB, FULL_ACCESS, 1, 0, 0);//[ 16M] PSRAM_BACKGROUND (support both 8M/16M PSRAM) mpu_config_region_set_mem(cnt++, 0x7E180000, REG_512KB, READ_ONLY, 1, 0, 0);//[+512K] DDR_PSRAM_CODE mpu_config_region_set_mem(cnt++, 0x7E200000, REG_512KB, READ_ONLY, 1, 0, 0);//[+512K] mpu_config_region_set_mem(cnt++, 0x7E680000, REG_512KB, FULL_ACCESS, 0, 1, 0);//[+ 512K] DDR_NONCACHE mpu_config_region_set_mem(cnt++, 0x7E700000, REG_1MB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE mpu_config_region_set_mem(cnt++, 0x7E000000, REG_1MB, READ_ONLY, 0, 1, 1);//[1.5M] DDR_DSP_RO mpu_config_region_set_mem(cnt++, 0x7E100000, REG_512KB, READ_ONLY, 0, 1, 1); /* mpu_config_region_set_dev(region_num, base_address, region_size, shared); */ mpu_config_region_set_dev(cnt++, 0xC0000000, REG_1GB, 1); //[ 1G] ASIC_REG_ADDR (force align) mpu_config_region_set_mem(cnt++, 0xD1000000, REG_64KB, FULL_ACCESS, 0, 1, 1);//[ 64K] SQU (non align) #endif return (cnt-1);//return configed region count } static unsigned int crane_ds_mpu_4M_psram_4M_flash_xip(unsigned int cnt) { #ifdef CRANE_MCU_DONGLE /* mpu_config_region_set_mem(region_num, base_address, REGION_SIZE, ACCESS_PERMISSION, cacheable, shared, execute_never) */ mpu_config_region_set_mem(cnt++, 0x00000000, REG_64KB, READ_ONLY, 0, 0, 0);//[ 64K] ATCM mpu_config_region_set_mem(cnt++, 0xB0020000, REG_64KB, FULL_ACCESS, 0, 0, 1);//[ 64k] BTCM mpu_config_region_set_mem(cnt++, 0x80000000, REG_32MB, FULL_ACCESS, 0, 0, 0);//[ 32M] DDR_QSPI_NOR_FLASH (support all 8M/16M/32M flash) mpu_config_region_set_mem(cnt++, 0x7E000000, REG_4MB, FULL_ACCESS, 1, 0, 0);//[ 4M] PSRAM_BACKGROUND (support both 8M/16M PSRAM) //Sharon.li@20230411 OPEN版本4+4和2+4的项目单卡的基线NOCACHE分区起始地址一样 #ifdef SINGLE_SIM #ifdef QUECTEL_USBNET_SUPPORT //for 1602 2+4 And 4+4 项目,支持USBNET的IPC行业版本 mpu_config_region_set_mem(cnt++, NOCACHE_STARTADDR_CHECK(0x7E36A000), REG_8KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE mpu_config_region_set_mem(cnt++, 0x7E368000, REG_32KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE mpu_config_region_set_mem(cnt++, 0x7E370000, REG_64KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE mpu_config_region_set_mem(cnt++, 0x7E380000, REG_512KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE #else //for 1602/1606 2+4 And 4+4 项目 mpu_config_region_set_mem(cnt++, NOCACHE_STARTADDR_CHECK(0x7E370000), REG_64KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE mpu_config_region_set_mem(cnt++, 0x7E380000, REG_512KB, FULL_ACCESS, 0, 1, 0);//[ 1M] DDR_NONCACHE #endif #endif /* mpu_config_region_set_dev(region_num, base_address, region_size, shared); */ mpu_config_region_set_dev(cnt++, 0xC0000000, REG_1GB, 1); //[ 1G] ASIC_REG_ADDR (force align) mpu_config_region_set_mem(cnt++, 0xD1000000, REG_64KB, FULL_ACCESS, 0, 1, 1);//[ 64K] SQU (non align) #endif return (cnt-1);//return configed region count } //xiaokeweng@20191008 flash cache_line auto config //for partition table , the XIP code part should be cacheable //but the NVM/factory/fota_pkg should always be noncache , //so implement solution to detect the cache_line address //aligned inside [dsp_start_addr ~ reserved_end_addr] for C-code MPU audo reconfig #define CACHELINE_ALIGN_REGION_SIZE(REG_N) (2 << REG_N) static unsigned int crane_ds_mpu_flash_noncache_line_auto_mpu(unsigned int cnt){ //ptable fetch noncache_line area [dsp.bin.start ~ reserved.end] unsigned int dsp_start_addr = get_dsp_start_address_offset(); #ifdef QUECTEL_OPEN_CPU /*以app结束地址为cache结束地址*/ unsigned int reserved_end_addr = get_flash_cache_end_address_offset(); #else unsigned int reserved_end_addr = get_reserved_end_address_offset(); #endif unsigned int cache_line_max = reserved_end_addr; unsigned int cache_line_min = dsp_start_addr; unsigned int cache_line = 0; unsigned int tmp_addr = cache_line_max; unsigned int tmp_align= REG_16MB; unsigned int min_align= REG_1MB; unsigned int mpu_num= 0; if(is_partition_internal_flash("nvm")){ mpu_config_region_set_mem(++cnt, 0x80000000, REG_32MB, FULL_ACCESS, 1, 0, 0); }else{ RTI_LOG("[MPU] cache_line_max = [0x%0.8x], cache_line_min = [0x%0.8x]\r\n",cache_line_max,cache_line_min); #if (defined(CRANEL_4MRAM) || defined(CRANEL_8MRAM)) min_align = REG_4KB; #endif #ifdef QUECTEL_OPEN_CPU while(!(cache_line > cache_line_max) && (tmp_align >= min_align)) { // open 配置到app_end前 #else //while(!(cache_line >= cache_line_min && cache_line <= cache_line_max) && (tmp_align >= min_align)) { #endif RTI_LOG("[MPU] tmp_addr = [0x%0.8x],CACHELINE_ALIGN_REGION_SIZE(tmp_align) = [0x%0.8x] , add/align=[%d]\r\n" ,tmp_addr ,CACHELINE_ALIGN_REGION_SIZE(tmp_align) ,tmp_addr/CACHELINE_ALIGN_REGION_SIZE(tmp_align)); if(tmp_addr/CACHELINE_ALIGN_REGION_SIZE(tmp_align) == 1){ //update tmp_addr tmp_addr -= CACHELINE_ALIGN_REGION_SIZE(tmp_align); //reconfig mpu //mpu_config_region_set_mem(region_num, base_address, REGION_SIZE, ACCESS_PERMISSION, cacheable, shared, execute_never) mpu_config_region_set_mem(++cnt, 0x80000000+cache_line, (region_size)tmp_align, FULL_ACCESS, 1, 0, 0);//RO cacheable code onside flash //update cache_line cache_line += CACHELINE_ALIGN_REGION_SIZE(tmp_align); RTI_LOG("[MPU] cnt=[%0.2d],tmp_align=[0x%0.2x],CACHELINE_ALIGN_REGION_SIZE(tmp_align) = [0x%0.8x],cache_line = [0x%0.8x]\r\n" ,cnt ,tmp_align ,CACHELINE_ALIGN_REGION_SIZE(tmp_align) ,cache_line); } #ifdef QUECTEL_OPEN_CPU if(cnt>=14){ //mpu region cnt at[0-14],cnt 15 should be used by ASR,if cnt exceed 14 will happen assert! RTI_LOG("MPU[%d] num error!", cnt); break; } #endif //update tmp_align tmp_align -= 0x01; } } if(cnt>=15){ //mpu region cnt at[0-14],cnt 15 should be used by ASR,if cnt exceed 14 will happen assert! RTI_LOG("MPU[%d] num error!", cnt); ASSERT(0); } //reset unused mpu region mpu_num = cnt; while(mpu_num<15){ mpu_config_region_set_mem(++mpu_num, 0x00000000, 0x00, NO_ACCESS, 1, 0, 0); } return (cnt); } void crane_ds_mpu(void) { unsigned int cnt ; //uart_printf("[MPU] function:%s,line:%d\r\n", __func__,__LINE__); CPUartLogPrintf("Crane mpu configure"); //step1:entry action, disable I/D cache,set 4G FULL_ACCESS background on region BACKGROUND_REGION mpu_config_entry_action(); //step2:config and enable project mpu , start from (BACKGROUND_REGION+1) cnt = (BACKGROUND_REGION + 1); #ifdef RUN_XIP_MODE #if defined(CRANEM_8MRAM) || defined(_8MNORFLASH) || defined(LTEONLY_8M8M) || defined(LTEGSM_THIN)//8M_FLASH #if defined(CRANELS_16M16M) cnt = crane_ds_mpu_16M_psram_16M_flash_xip(cnt); #elif defined(CRANEM_SS_16MRAM) cnt = crane_ss_mpu_16M_psram_8M_flash_xip(cnt); #else cnt = crane_ds_mpu_8M_psram_8M_flash_xip(cnt); #endif #elif defined(CRANEL_4MRAM) cnt = crane_ds_mpu_4M_psram_4M_flash_xip(cnt); #else cnt = crane_ds_mpu_16M_psram_16M_flash_xip(cnt); #endif #else cnt = crane_ds_mpu_16M_psram_16M_flash_psram(cnt); #endif cnt = crane_ds_mpu_flash_noncache_line_auto_mpu(cnt); //step3:exit action, enable I/D cache,enable 4G NO_ACCESS background on region BACKGROUND_REGION mpu_config_exit_action(); region_cnt = cnt; crane_ds_mpu_xip_enable(TRUE); //step4:uart dump configed mpu region mpu_config_uart_dump(15); //uart_printf("[MPU] function:%s,line:%d\r\n", __func__,__LINE__); return; } void crane_ds_mpu_xip_enable(bool enable) { if(enable) { mpu_config_region_set_mem(15, 0x80000000, 0x00, NO_ACCESS, 1, 0, TRUE); } else { mpu_config_region_set_mem(15, 0x80000000, REG_32MB, NO_ACCESS, 1, 0, TRUE); } if(!SysIsAssert()) { xip_access_enable = enable; } } void crane_ds_mpu_xip_cache_enable(void) { mpu_config_region_set_mem(15, 0x80000000, 0x00, FULL_ACCESS, 0, 0, 0); } void crane_ds_mpu_xip_cache_disable(void) { mpu_config_region_set_mem(15, 0x80000000, REG_32MB, FULL_ACCESS, 0, 0, 0); }