#include "utilities.h"
#include "psram.h"
#include "bsp.h"
#include "quec_cust_feature.h"

extern int psram_read_mr(unsigned mr_addr, unsigned cs); 


void wb32Mb_psram_fast_refresh(void)
{
    unsigned read_data = 0;

    __asm {DSB};

	PSRAM_REG32(PSRAM_BASE + 0x8024) &= ~(0xf<<12);
	PSRAM_REG32(PSRAM_BASE + 0x9024) &= ~(0xf<<12);

	PSRAM_REG32(PSRAM_BASE + 0x8024) |= (0x4<<12);
	PSRAM_REG32(PSRAM_BASE + 0x9024) |= (0x5<<12);

	// write CR0 to take effect:
	PSRAM_REG32(PSRAM_BASE + 0x8034) = 0x1000;
	PSRAM_REG32(PSRAM_BASE + 0x8030) = 0x10a;
	read_data = PSRAM_REG32(PSRAM_BASE + 0x8030);
	while ((read_data & 0x100) != 0x0) {
	   read_data = PSRAM_REG32(PSRAM_BASE + 0x8030);
	}

	return;
}

#pragma arm section code="PSRAM_WB32_HALFSLEEP"
void wb32Mb_psram_halfsleep_config(void)
{
#define WBD_32Mb
    /*[REG_C: SEQ_TABLE]*/ // WBD LUT 'h7: WR MR6 hybird sleep entry!
    /*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x8100) = 0x93188460;
    /*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x8104) = 0x84ff8f10;
    /*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x8108) = 0x240284e2;
#ifdef  WBD_32Mb
    /*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x8104) = 0xc400cf10;
    /*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x8108) = 0x2402c460;
#endif  // WBD_32Mb
    /*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x810c) = 0x0;
        //LOG_INFO("!!! WB32Mb psram hybrid sleep entry right @@@@  !!!  \n");
    /*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x810c) = 0x0;

    /*[REG_C: SEQ_TABLE]*/ // LUT 'h8: CEN low halfsleep exit!
    /*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x8110) = 0x22012880;
    /*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x8114) = 0x2c056210;
    /*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x8118) = 0x0;

	return;
}
#pragma arm section code


#if !defined(LTEONLY_THIN_SINGLE_SIM_2MFLASH)

#pragma arm section code="PSRAMWRTESTMODE"
void psram_wr_testmode(void)
{
  /*[REG_C: SEQ_TABLE]*/ // WBD LUT 'hb: WR TESTMODE!
  /*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x8140) = 0xc400c440;
  /*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x8144) = 0x4400cb20;
  /*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x8148) = 0x0;
}
#pragma arm section code

int psram_write_testmode(unsigned seq_addr)
{
	unsigned read_data = 0;

	PSRAM_REG32(PSRAM_BASE + 0x8034) = seq_addr;
	PSRAM_REG32(PSRAM_BASE + 0x8030) = 0x10b;

	read_data = PSRAM_REG32(PSRAM_BASE + 0x8030);
	while ((read_data & 0x100) != 0x0) {
		read_data = PSRAM_REG32(PSRAM_BASE + 0x8030);
	}

	return read_data;
}


 int winbond_psram_fast_refresh_entry(void)
{
	
	psram_write_testmode(0xA4A00008);//STEP1
	psram_write_testmode(0x04000008);//STEP2
	psram_write_testmode(0x04000008);//STEP3
	psram_write_testmode(0xA4A00008);//STEP4
	psram_write_testmode(0x14900008);//STEP5
	psram_write_testmode(0x04c00008);//STEP6

    return 0;
}

int winbond_psram_fast_refresh_entry_test(void)
{
	unsigned reg = 0;

	__asm {DSB};

	reg = PSRAM_REG32(PSRAM_BASE + 0x4010);
	reg |= (1<<12);
	PSRAM_REG32(PSRAM_BASE + 0x4010) = reg;

	PSRAM_REG32(PSRAM_BASE + 0x0004) = 0x7E68F001;
	winbond_psram_fast_refresh_entry();
	PSRAM_REG32(PSRAM_BASE + 0x0004) = 0x7E684001;

	reg = PSRAM_REG32(PSRAM_BASE + 0x4010);
	reg &= ~(1<<12);
	PSRAM_REG32(PSRAM_BASE + 0x4010) = reg;

	return 0;
}



int winbond_psram_fast_refresh_exit(void)
{

	psram_write_testmode(0xA4A00008);//STEP1
	psram_write_testmode(0x54600008);//STEP2
	psram_write_testmode(0x04000008);//STEP3

    return 0;
}

 int winbond_psram_fast_refresh_exit_test(void)
 {
 	unsigned reg = 0;

    __asm {DSB};

	reg = PSRAM_REG32(PSRAM_BASE + 0x4010);
	reg |= (1<<12);
	PSRAM_REG32(PSRAM_BASE + 0x4010) = reg;
	
 	PSRAM_REG32(PSRAM_BASE + 0x0004) = 0x7E68F001;
	winbond_psram_fast_refresh_exit();
	PSRAM_REG32(PSRAM_BASE + 0x0004) = 0x7E684001;

	reg = PSRAM_REG32(PSRAM_BASE + 0x4010);
	reg &= ~(1<<12);
	PSRAM_REG32(PSRAM_BASE + 0x4010) = reg;


	return 0;

 }


static int psram_read_mr(unsigned mr_addr, unsigned cs)
{
    unsigned read_data = 0;

    // read MR register
    PSRAM_REG32(PSRAM_BASE + 0x8034) = mr_addr + (cs << 23);
    PSRAM_REG32(PSRAM_BASE + 0x8030) = 0x109;
    read_data = PSRAM_REG32(PSRAM_BASE + 0x8030);
    while ((read_data & 0x100) != 0x0) {
        read_data = PSRAM_REG32(PSRAM_BASE + 0x8030);
    }
    read_data = PSRAM_REG32(PSRAM_BASE + 0x8038);     // this is the mr read data value
	RTI_LOG("RB: MR0x%x_CS%d: @[0x%08X]=[0x%08X]\r\n", mr_addr, cs, (PSRAM_BASE + 0x8034), PSRAM_REG32(PSRAM_BASE + 0x8034));
	RTI_LOG("RB: MR0x%x_CS%d: @[0x%08X]=[0x%08X]\r\n", mr_addr, cs, (PSRAM_BASE + 0x8038), read_data);

    return read_data;
}



int psram_fast_refresh_exit(void)
{
#if 0
    unsigned char psram_type = getPsramType();
    
	//RTI_LOG("psram_fast_refresh_exit,psram_type: %d\r\n",psram_type);
	
	switch (psram_type) {
		//case WB_8M8M:
		//case WB_250MHZ_8M8M:
		case WB_8M:
		case WB_250MHZ_8M:
			winbond_psram_fast_refresh_exit_test();
			//psram_read_mr(0x1002, 0);
            //psram_read_mr(0x1002, 1);
			break;
		#if 0
		case WB_4M:
            psram_read_mr(0x1000,0);
		    break;
		#endif
		default:
			break;
	}
#endif
    return 0;
}

int psram_fast_refresh_entry(void)
{
#if 0
    unsigned char psram_type = getPsramType();
    //RTI_LOG("psram_fast_refresh_entry,psram_type: %d\r\n",psram_type);
	switch (psram_type) {
		//case WB_8M8M:
		//case WB_250MHZ_8M8M:
		case WB_8M:
		case WB_250MHZ_8M:
			winbond_psram_fast_refresh_entry_test();
			//psram_read_mr(0x1002, 0);
	        //psram_read_mr(0x1002, 1);
			break;
	    #if 0
		case WB_4M:
		    psram_read_mr(0x1000,0);
		    break;
		#endif
		default:
			break;
	}
#endif
    return 0;
}

#endif

int crane_psram_init(void)
{
#if !defined(LTEONLY_THIN_SINGLE_SIM_2MFLASH)
    unsigned long read_data = 0;
#endif
    unsigned char psram_type = getPsramType();
    switch (psram_type) {
#if !defined(LTEONLY_THIN_SINGLE_SIM_2MFLASH)
        /************************************************/
        /************************************************/
        //bug:212193,move WB_8M8M psram config from cinit1 function, fix get wrong psram type
        case WB_8M8M:
        	read_data = PSRAM_REG32(PSRAM_BASE + 0x8000);
    		read_data &= 0xff00ffff;
    		read_data |= (5<<16)|(5<<20);
    		PSRAM_REG32(PSRAM_BASE + 0x8000) = read_data;
            break;
        /************************************************/
        /************************************************/
        /************************************************/
        case WB_8M:
        case WB_250MHZ_8M:
        //case WB_8M8M:
        //case WB_250MHZ_8M8M:
            //psram_wr_testmode();
            //winbond_psram_fast_refresh_exit_test();
		#ifdef QUECTEL_PROJECT_CUST	//quectelĬÈÏʹÄÜ8M psram fast refresh
            psram_wr_testmode();
            winbond_psram_fast_refresh_entry_test();
		#endif //QUECTEL_PROJECT_CUST
            break;
            
        case AP_8M:
        case AP_250MHZ_8M:
        //case AP_8M8M:
        //case AP_250MHZ_8M8M:
        //case AP_16M:
            PSRAM_REG32(0xC0108024) &= 0xFF00FFFF;
            PSRAM_REG32(0xC0109024) &= 0xFF00FFFF;
            PSRAM_REG32(0xC0108024) |= 0x480000;
            PSRAM_REG32(0xC0109024) |= 0x280000;
            AP8M_psram_lpm_table();
            break;
#endif  
        case WB_4M:
            wb32Mb_psram_halfsleep_config();
            wb32Mb_psram_fast_refresh(); 
            WB4M_psram_lpm_table();
            break;
            
        case AP_4M:
            AP4M_psram_lpm_table();
            break;

            
        default:
            break;
    }
    
    if(CHIP_IS_CRANELR || CHIP_IS_CRANELS || CHIP_IS_CRANELG || CHIP_IS_CRANELRH)
    {
         unsigned int reg_val = 0;
         reg_val = PSRAM_REG32(0xD4090128);
         reg_val &=~(0x3<<28);
         reg_val |= (0x1<<28); // change psram pad to pull down
         PSRAM_REG32(0xD4090128) = reg_val;
    }

    return 0;
}