/*------------------------------------------------------------
(C) Copyright [2006-2008] Marvell International Ltd.
All Rights Reserved
------------------------------------------------------------*/

/************************************************************************/
/*  COPYRIGHT (C) 2002 Intel Corporation.                               */
/*                                                                      */
/*  This file and the software in it is furnished under                 */
/*  license and may only be used or copied in accordance with the terms */
/*  of the license. The information in this file is furnished for       */
/*  informational use only, is subject to change without notice, and    */
/*  should not be construed as a commitment by Intel Corporation.       */
/*  Intel Corporation assumes no responsibility or liability for any    */
/*  errors or inaccuracies that may appear in this document or any      */
/*  software that may be provided in association with this document.    */
/*  Except as permitted by such license, no part of this document may   */
/*  be reproduced, stored in a retrieval system, or transmitted in any  */
/*  form or by any means without the express written consent of Intel   */
/*  Corporation.                                                        */
/*                                                                      */
/* Title: Communication Subsystem Power Management Unit                 */
/*               (macros) Header File                                   */
/*    													                */
/* Filename: cpmu_def.h                                                 */
/*                                                                      */
/* Author:   Olga Fomenko                                          */
/*                                                                      */
/* Project, Target, subsystem: Tavor, Arbel, HOP     					*/
/*																		*/
/* Remarks: 									*/
/*    													                */
/* Created: 20/04/2005                                                   */
/*                                                                      */
/* Modified:                                                            */
/************************************************************************/

#ifndef _CPMU_DEF_H
#define _CPMU_DEF_H


#include "cpmu.h"
#include "cpmu_hw.h"

#define CPMURegisters (* (CPMU_HW_Registers *) CPMU_BASE_ADDRESS)

// definition for additional A0 registers
#define CPMU_GPBLCSR_REG      (* (UINT32 *) CPMU_GPBLCSR_REG_ADDR)
#define CPMU_WRST_WR_REG      (* (UINT32 *) CPMU_WRST_WR_REG_ADDR)
#define CPMU_WRST_RD_REG      (* (UINT32 *) CPMU_WRST_RD_REG_ADDR)

// TBD - should be replaced to make file
//#define CPMU_DEBUG  // undefine this flag for regular work mode

#define CPMU_CORE_VOLTAGE_CHANGE_TIMEOUT 8000 // TBD, not relevant in QT

#define CLEAR_BITS(reg, mask)                   ((reg) &= (~(mask)))

#define SET_BITS(reg, value, mask, shift)       {CLEAR_BITS(reg, mask);\
                                                 reg |= (((value)<<(shift))&(mask));}

#define SET_BIT(reg, value, mask)               {reg = (value)?((reg) | (mask)):((reg) & (~(mask)));}

#define CLEAN_STATUS_BITS_FROM_REG(reg,mask)    ((reg) & (~mask))
//#define EXPAND_TO_ALL_BITS(enableDisable)       ((enableDisable)?0xFFFFFFFF)

#define GET_BITS(reg, mask, shift)              (((reg)&(mask))>>(shift))

// this MACRO is related to CPMU_RetainInD2ResourceE enum typedef
#define RESOURCE_IS_MEMORY(x)					((x==CPMU_RD2R_MEM_GB_L1) || \
												 (x==CPMU_RD2R_MEM_ARBEL))
#define RESOURCES_MEM_GET(x)                    (x&(CPMU_RD2R_MEM_GB_L1|CPMU_RD2R_MEM_ARBEL))
#define RESOURCES_VOL_GET(x)					( x & (~(CPMU_RD2R_MEM_GB_L1|CPMU_RD2R_MEM_ARBEL)) )
// this MACROs is related to CPMU_State enum typedef
#define NOT_LOGICAL_TO_ENABLE_DISABLE(x)        ((x == CPMU_ENABLE)?CPMU_DISABLE:CPMU_ENABLE)
#define CONVERT_TO_ENABLE_DISABLE(x)            ((x)?CPMU_ENABLE:CPMU_DISABLE)

// this MACROs is related to CPMU_State enum typedef CPMU_WakeUpEventE
#define ONLY_GP_WAKEUPS(x)						(!(x&(~CPMU_WAKEUP_ALL_GP)))
#define ONLY_ENABLE_DISABLE_WAKEUPS(x)			(!(x&(~CPMU_WAKEUP_ALL_ENABLE_DISABLE)))

// this MACROs is related to CPMU_State enum typedef CPMU_PeripheralE
#define ONLY_COMMON_RESET_ASSERTION_PER(x)     (!(x&(~CPMU_ALL_COMMON_RESET_ASSERTION_PER)))
#define ONLY_2_RESET_ASSERTION_PER(x)          (!(x&(~CPMU_ALL_2_RESET_ASSERTION_PER)))
#define FUNCTIONAL_ASSERTION_MASK              0x551
#define BUS_ASSERTION_MASK                     0xAA2

// CPCR
#define CPCR_WMP_REQ_MASK		 0x00400000
#define CPCR_WMP_REQ_SHIFT		 22

#define CPCR_PM_MASK			 0x00000003
#define CPCR_PM_SHIFT            0

#define CPCR_D2R_COMM_MASK       0x00000008
#define CPCR_D2R_COMM_SHIFT      3
#define CPCR_D2R_SRAM_MASK       0x00000010
#define CPCR_D2R_SRAM_SHIFT      4

//CL1CR
#define CL1CR_GL1SR_MASK         0x00000001
#define CL1CR_GL1SR_SHIFT        0

#define CL1CR_CL1SR_MASK         0x00000002
#define CL1CR_CL1SR_SHIFT        1

//CPSR
#define CPSR_STATUS_BITS_MASK    0x0000000F
#define CPSR_SWR_MASK            0xF0000000
#define CPSR_SWR_SHIFT           28

#define CPSR_WDTA_MASK           0x08000000
#define CPSR_WDTA_SHIFT          27

#define CPSR_WMS_MASK            0x00000020
#define CPSR_WMS_SHIFT           5

#define CPSR_RDH_MASK            0x00000008
#define CPSR_RDH_SHIFT           3


#define CPSR_LPM_MASK			 0x00000002
#define CPSR_LPM_SHIFT           1

#define CPSR_WDT_MASK			 0x00000001
#define CPSR_WDT_SHIFT           0

#define CPSR_VCS_MASK            0x00000004
#define CPSR_VCS_SHIFT           2

//CL2DR
#define CL2DR_DMC_MASK           0x00000001

//CPR
#define CPR_PMIC_GO_MASK         0x00000001
#define CPR_PMIC_GO_SHIFT		 0

#define CPR_PMIC_CS_MASK         0x00000006
#define CPR_PMIC_CS_SHIFT        1

#define CPR_PMIC_D2E_MASK        0x00000008
#define CPR_PMIC_D2E_SHIFT       3

//CRAR
#define CRAR_ASSP_FRA_MASK       0x00000010
#define CRAR_ASSP_BRA_MASK       0x00000020

#define CRAR_SSP_FRA_MASK        0x00000040
#define CRAR_SSP_BRA_MASK        0x00000080

//CCRAR (Arm D2 reset address)
#define CPMU_CCRAR_MASK          (0xFFFFFFFC)

//GPBLCSR
#define  GPBLCSR_D1DES_BIT_MASK     0x1

//WRST_WR
#define WRST_WR_I2C_EVENT_CODE     0x00000000   //0<<1
#define WRST_WR_GSIM_EVENT_CODE    0x00000002   //1<<1
#define WRST_WR_GSSP1_EVENT_CODE   0x00000004   //2<<1
#define WRST_WR_GSSP2_EVENT_CODE   0x00000006   //3<<1
#define WRST_WR_PMIC_EVENT_CODE    0x00000008   //4<<1
#define WRST_WR_UART_EVENT_CODE    0x0000000A   //5<<1
#define WRST_WR_CGPIO_EVENT_CODE   0x0000000C   //6<<1
#define WRST_WR_ALL_EVENT_CODE     0x0000001E   //F<<1

#define WRST_WR_EVTDIS_ENABLE      0x00000001
#define WRST_WR_EVTDIS_DISABLE     0x00000000

//GPBMCSR
#define GPBMCSR_TCU_CE_SEL            0x00000001
#define GPBMCSR_UART_CLK_EN			  0x00000002	//HUCE
#define GPBMCSR_USIM_NMOS_DISENGAGE	  0x00000004    //UPEND



#define CWESR_WAKE_UP_EN_MASK          0x40000000
#define CWESR_RST_STICKY_MASK          0x80000000
#define CWESR_SW_BIT_BOTH_MASK       0xC0000000

//MTV_CTL
#define MTV_CTL_WB_GSM_SLP_TIMER_SEL		  	0x00000001  //SGW
#define MTV_CTL_GSM_ACTIVE_SC                   0x00000002  //SGS
#define MTV_CTL_GSM_STKY_RST					0x00000004  //GWE_STKY_RST
#define MTV_CTL_WB_SLEEP_MODULE_POLARITY_FIX    0x00000008  //(not documented yet)
/*
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// CMCR bit masks
#define	CMCR_GC_MASK             0x00000007 // 0:2 Grid count, decremented each 16*(GC+1) clocks (13MHz), values 16 - 128
#define CMCR_GC_SHIFT            0
#define	CMCR_N2PCC_MASK          0x00000078 // 3:6 NMOS to PMOS Clamp count, values 16 - 256
#define	CMCR_N2PCC_SHIFT         3
#define	CMCR_P2NCC_MASK          0x00000780 // 7:10 PMOS to NMOS Clamp count, values 16 - 256
#define	CMCR_P2NCC_SHIFT         7
#define	CMCR_N2UCC_MASK          0x00007800 // 11:14 NMOS to UDSWY count, values 16 - 256
#define	CMCR_N2UCC_SHIFT         11

// CL2CR bit masks
#define CMCR_L2_BANK_SHIFT (bankNumber)     (bankNumber*2)
#define CMCR_L2_BANK_MASK  (bankNumber)     (0x3L<<CMCR_L2_BANK_SHIFT (bankNumber))
*/

// global data base
typedef struct
{
	CPMUL2PowerChangeNotifyFn    l2PowerChangeNotifyFn;
	BOOL                         l2PowerChangeEnable;
	CPMUPMICCOmmandSetNotifyFn   pmicCommnadSetNotifyFn;
	BOOL                         pmicCommnadSetEnable;
	CPMUFrequencyChangeNotifyFn  freqChangeNotifyFn;
	BOOL                         freqChangeEnable;
	BOOL						 memoryConfigurationNotRequired;
	BOOL						 CommpmUsimNmosEngageInUse;
}CPMU_DataBaseS;

typedef const struct {

		UINT32 CPMUControlBitsToReg[CPMU_NUM_OF_CONROL_BITS]; //rafiagiv 27.12
		UINT32            CPMUControBitToBitMask[CPMU_NUM_OF_CONROL_BITS];
    } CPMU_LookUpTablesS;

    static CPMU_LookUpTablesS _CPMULookUpTables =
    {
        {   // CPMUControlBitsToReg
            //CPMU_WB_GSM_TCU_CE_SEL  - TCU_CE_SEL
			CPMU_MCSR_GPB_REG_ADDR,
			//CPMU_WB_GSM_SLP_TIMER_SEL             //SGW
			CPMU_MVT_CTL_REG_ADDR,
			//CPMU_GSM_STKY_RST,				    //GWE_STKY_RST
			CPMU_MVT_CTL_REG_ADDR,
			//CPMU_WB_SLEEP_MODULE_POLARITY_FIX,    //(not documented yet)
			CPMU_MVT_CTL_REG_ADDR,
			//CPMU_UART_CLK_EN					    //HUCE
			CPMU_MCSR_GPB_REG_ADDR,
			//CPMU_USIM_NMOS_DISENGAGE              //UPEND
			CPMU_MCSR_GPB_REG_ADDR
		},
		{	//CPMUControBitToBitMask
			//CPMU_WB_GSM_TCU_CE_SEL  - TCU_CE_SEL
			GPBMCSR_TCU_CE_SEL,
			//CPMU_WB_GSM_SLP_TIMER_SEL             //SGW
			MTV_CTL_WB_GSM_SLP_TIMER_SEL,
			//CPMU_GSM_STKY_RST,				    //GWE_STKY_RST
			MTV_CTL_GSM_STKY_RST,
			//CPMU_WB_SLEEP_MODULE_POLARITY_FIX,    //(not documented yet)
			MTV_CTL_WB_SLEEP_MODULE_POLARITY_FIX,
			//CPMU_UART_CLK_EN					    //HUCE
			GPBMCSR_UART_CLK_EN,
			//CPMU_USIM_NMOS_DISENGAGE              //UPEND
			GPBMCSR_USIM_NMOS_DISENGAGE
		}
	};

	#define CPMU_LUT_CONTROL_BIT_TO_REG_MAP(controlBit)  \
		(_CPMULookUpTables.CPMUControlBitsToReg[controlBit])

	#define CPMU_LUT_CONTROL_BIT_TO_MASK_MAP(controlBit)  \
		(_CPMULookUpTables.CPMUControBitToBitMask[controlBit])

//20090625, below added from pmum.h, apmu.h
//#ifdef PHS_SW_DEMO_TTC_PM
#define BIT_0 (1 << 0)
#define BIT_1 (1 << 1)
#define BIT_2 (1 << 2)
#define BIT_3 (1 << 3)
#define BIT_4 (1 << 4)
#define BIT_5 (1 << 5)
#define BIT_6 (1 << 6)
#define BIT_7 (1 << 7)
#define BIT_8 (1 << 8)
#define BIT_9 (1 << 9)
#define BIT_10 (1 << 10)
#define BIT_11 (1 << 11)
#define BIT_12 (1 << 12)
#define BIT_13 (1 << 13)
#define BIT_14 (1 << 14)
#define BIT_15 (1 << 15)
#define BIT_16 (1 << 16)
#define BIT_17 (1 << 17)
#define BIT_18 (1 << 18)
#define BIT_19 (1 << 19)
#define BIT_20 (1 << 20)
#define BIT_21 (1 << 21)
#define BIT_22 (1 << 22)
#define BIT_23 (1 << 23)
#define BIT_24 (1 << 24)
#define BIT_25 (1 << 25)
#define BIT_26 (1 << 26)
#define BIT_27 (1 << 27)
#define BIT_28 (1 << 28)
#define BIT_29 (1 << 29)
#define BIT_30 (1 << 30)
#define BIT_31 ((unsigned)1 << 31)

#define SHIFT0(Val)  (Val)
#define SHIFT1(Val)  ((Val) << 1)
#define SHIFT2(Val)  ((Val) << 2)
#define SHIFT3(Val)  ((Val) << 3)
#define SHIFT4(Val)  ((Val) << 4)
#define SHIFT5(Val)  ((Val) << 5)
#define SHIFT6(Val)  ((Val) << 6)
#define SHIFT7(Val)  ((Val) << 7)
#define SHIFT8(Val)  ((Val) << 8)
#define SHIFT9(Val)  ((Val) << 9)
#define SHIFT10(Val) ((Val) << 10)
#define SHIFT11(Val) ((Val) << 11)
#define SHIFT12(Val) ((Val) << 12)
#define SHIFT13(Val) ((Val) << 13)
#define SHIFT14(Val) ((Val) << 14)
#define SHIFT15(Val) ((Val) << 15)
#define SHIFT16(Val) ((Val) << 16)
#define SHIFT17(Val) ((Val) << 17)
#define SHIFT18(Val) ((Val) << 18)
#define SHIFT19(Val) ((Val) << 19)
#define SHIFT20(Val) ((Val) << 20)
#define SHIFT21(Val) ((Val) << 21)
#define SHIFT22(Val) ((Val) << 22)
#define SHIFT23(Val) ((Val) << 23)
#define SHIFT24(Val) ((Val) << 24)
#define SHIFT25(Val) ((Val) << 25)
#define SHIFT26(Val) ((Val) << 26)
#define SHIFT27(Val) ((Val) << 27)
#define SHIFT28(Val) ((Val) << 28)
#define SHIFT29(Val) ((Val) << 29)
#define SHIFT30(Val) ((Val) << 30)
#define SHIFT31(Val) ((Val) << 31)


/*
 *
 *	THE BASE ADDRESSES
 *
 */
#define	PMUM_BASE	0xD4050000

/*
 *
 *	THE REGISTER DEFINES
 *
 */
#define	PMUM_CPCR	(PMUM_BASE+0x0000)	/* 32 bit	Marvell CPU Power Control
										 *			Register
										 */
#define	PMUM_CPSR	(PMUM_BASE+0x0004)	/* 32 bit	Marvell CPU Power Status
										 *			Register
										 */
#define	PMUM_FCCR	(PMUM_BASE+0x0008)	/* 32 bit	Frequency Change Control
										 *			Register
										 */
#define	PMUM_POCR	(PMUM_BASE+0x000C)	/* 32 bit	PLL and Oscillator Control
										 *			Register
										 */
#define	PMUM_POSR	(PMUM_BASE+0x0010)	/* 32 bit	PLL and Oscillator Status
										 *			Register
										 */
#define	PMUM_SUCCR	(PMUM_BASE+0x0014)	/* 29 bit	Slow UART (UART 1) Clock
										 *			Generation Control
										 *			Register
										 */
#define	PMUM_VRCR	(PMUM_BASE+0x0018)	/* 32 bit	VCXO Request Control
										 *			Register
										 */
#define	PMUM_CPRR	(PMUM_BASE+0x0020)	/* 32 bit	Marvell CPU Programmable
										 *			Reset Register
										 */
#define	PMUM_CCGR	(PMUM_BASE+0x0024)	/* 32 bit	Marvell CPU Clock Gating
										 *			Register
										 */
#define	PMUM_CRSR	(PMUM_BASE+0x0028)	/* 32 bit	Marvell CPU Reset Status
										 *			Register
										 */
#define	PMUM_GPCR	(PMUM_BASE+0x0030)	/* 32 bit	General Purpose Clock
										 *			Generation Control
										 *			Register
										 */
#define	PMUM_PLL2CR	(PMUM_BASE+0x0034)	/* 32 bit	PLL2 Control Register */
#define	PMUM_SCCR	(PMUM_BASE+0x0038)	/* 32 bit	Slow Clock Control Register */
#define	PMUM_MCCR	(PMUM_BASE+0x003C)	/* 32 bit	MSA Clock Control Register */
#define	PMUM_ISCCRX	(PMUM_BASE+0x0040)	/* I2S Clock Generation Control Register
										 *			Start
										 */
#define	PMUM_CWUCRS	(PMUM_BASE+0x0048)	/* 32 bit	Wakeup and Clock Resume
										 *			Lines Status Register
										 */
#define	PMUM_CWUCRM	(PMUM_BASE+0x004C)	/* 31 bit	Wakeup and Clock Resume
										 *			Lines Mask Register
										 */
#define	PMUM_DSOC	(PMUM_BASE+0x0100)	/* 32 bit	Debug Signals Output
										 *			Control Register
										 */
#define	PMUM_WDTPCR	(PMUM_BASE+0x0200)	/* 32 bit	WDT (Communication
										 *			Subsystem Timers) Control
										 *			Register
										 */
#define	PMUM_CMPRX	(PMUM_BASE+0x0400)	/* Marvell CPU Module Power Register Start */
#define	PMUM_APCR	(PMUM_BASE+0x1000)	/* 32 bit	Marvell CPU Power Control
										 *			Register
										 */
#define	PMUM_APSR	(PMUM_BASE+0x1004)	/* 32 bit	Marvell CPU Power Status
										 *			Register
										 */
#define	PMUM_APRR	(PMUM_BASE+0x1020)	/* 32 bit	Marvell CPU Programmable
										 *			Reset Register
										 */
#define	PMUM_ACGR	(PMUM_BASE+0x1024)	/* 32 bit	Marvell CPU Clock Gating
										 *			Register
										 */
#define	PMUM_ARSR	(PMUM_BASE+0x1028)	/* 32 bit	Marvell CPU Reset Status
										 *			Register
										 */
#define	PMUM_AWUCRS	(PMUM_BASE+0x1048)	/* 32 bit	Wakeup and Clock Resume
										 *			Lines Status Register
										 */
#define	PMUM_AWUCRM	(PMUM_BASE+0x104C)	/* 31 bit	Wakeup and Clock Resume
										 *			Lines Mask Register
										 */

/*
 *
 *	THE BIT DEFINES
 *
 */
/*	PMUM_CPCR	0x0000	Marvell CPU Power Control Register */
#define	PMUM_CPCR_AXISD					BIT_31			/* AXISD */
#define	PMUM_CPCR_DSPSD					BIT_30			/* DSPSD */
#define	PMUM_CPCR_SLPEN					BIT_29			/* SLPEN */
#define	PMUM_CPCR_DTCMSD				BIT_28			/* DTCMSD */
#define	PMUM_CPCR_DDRCORSD				BIT_27			/* DDRCORSD */
#define	PMUM_CPCR_APBSD					BIT_26			/* APBSD */
#define	PMUM_CPCR_BBSD					BIT_25			/* BBSD */
#define	PMUM_CPCR_INTCLR				BIT_24			/* Interrupt clear register */
/* Sleep mode Wake-up decoder Port 0 disable */
#define	PMUM_CPCR_SLPWP0				BIT_23
/* Sleep mode Wake-up decoder Port 1 disable */
#define	PMUM_CPCR_SLPWP1				BIT_22
/* Sleep mode Wake-up decoder Port 2 disable */
#define	PMUM_CPCR_SLPWP2				BIT_21
/* Sleep mode Wake-up decoder Port 3 disable */
#define	PMUM_CPCR_SLPWP3				BIT_20
#define	PMUM_CPCR_VCTCXOSD				BIT_19			/* VCTCXOSD */
/* Sleep mode Wake-up decoder Port 4 disable */
#define	PMUM_CPCR_SLPWP4				BIT_18
/* Sleep mode Wake-up decoder Port 5 disable */
#define	PMUM_CPCR_SLPWP5				BIT_17
/* Sleep mode Wake-up decoder Port 6 disable */
#define	PMUM_CPCR_SLPWP6				BIT_16
/* Sleep mode Wake-up decoder Port 7 disable */
#define	PMUM_CPCR_SLPWP7				BIT_15
#define	PMUM_CPCR_MSASLPEN				BIT_14			/* MSASLPEN */
#define	PMUM_CPCR_UDR				    BIT_13
#define	PMUM_CPCR_CP_VOTE_AP_SLPEN	    BIT_3

/*	PMUM_CPSR	0x0004	Marvell CPU Power Status Register */
#define	PMUM_CPSR_DSPIDL				BIT_31			/* DSPIDL */
#define	PMUM_CPSR_APIDL					BIT_30			/* APIDL */
#define	PMUM_CPSR_CPIDL					BIT_29			/* CPIDL */
#define	PMUM_CPSR_DSPAVL				BIT_28			/* DSPAVL */
#define	PMUM_CPSR_AP_FULL_IDLE			BIT_27			/* AP_FULL_IDLE */
#define	PMUM_CPSR_CP_FULL_IDLE			BIT_26			/* CP_FULL_IDLE */
#define	PMUM_CPSR_AP_SS_SLEEP			BIT_25			/* AP_SS_SLEEP */
#define	PMUM_CPSR_CP_SS_SLEEP			BIT_24			/* CP_SS_SLEEP */
/*		Bit(s) PMUM_CPSR_RSRV_23_21 reserved */
/*		Bit(s) PMUM_CPSR_RSRV_20 reserved */
/*		Bit(s) PMUM_CPSR_RSRV_19_17 reserved */
/*		Bit(s) PMUM_CPSR_RSRV_16_0 reserved */

/*	PMUM_FCCR	0x0008	Frequency Change Control Register */
/* Marvell <var Processor: Mohawk> CPU clock selection */
#define	PMUM_FCCR_MOHCLKSEL_MSK			SHIFT29(0x7)
#define	PMUM_FCCR_MOHCLKSEL_BASE		29
/* Marvell <var Processor: Osprey> CPU clock selection */
#define	PMUM_FCCR_SEAGCLKSEL_MSK		SHIFT26(0x7)
#define	PMUM_FCCR_SEAGCLKSEL_BASE		26
/* AXI and DDR clock selection */
#define	PMUM_FCCR_AXICLKSEL_MSK			SHIFT23(0x7)
#define	PMUM_FCCR_AXICLKSEL_BASE		23
/*		Bit(s) PMUM_FCCR_RSRV_22_18 reserved */
/*		Bit(s) PMUM_FCCR_RSRV_17_16 reserved */
#define	PMUM_FCCR_MFC					BIT_15			/* MFC */
#define	PMUM_FCCR_PLL1CEN				BIT_14			/* PLL1 control enable */
#define	PMUM_FCCR_PLL1REFD_MSK			SHIFT9(0x1f)	/* PLL1 REFDIV */
#define	PMUM_FCCR_PLL1REFD_BASE			9
#define	PMUM_FCCR_PLL1FBD_MSK			SHIFT0(0x1ff)	/* PLL1 FBDIV */
#define	PMUM_FCCR_PLL1FBD_BASE			0

/*	PMUM_POCR	0x000C	PLL and Oscillator Control Register */
#define	PMUM_POCR_FORCE					BIT_31			/* FORCE */
/*		Bit(s) PMUM_POCR_RSRV_30_24 reserved */
#define	PMUM_POCR_VCXOST_MSK			SHIFT16(0xff)	/* VCXOST */
#define	PMUM_POCR_VCXOST_BASE			16
/*		Bit(s) PMUM_POCR_RSRV_15_12 reserved */
#define	PMUM_POCR_PLLLOCK_MSK			SHIFT0(0xfff)	/* PLLLOCK */
#define	PMUM_POCR_PLLLOCK_BASE			0

/*	PMUM_POSR	0x0010	PLL and Oscillator Status Register */
/*		Bit(s) PMUM_POSR_RSRV_31_28 reserved */
#define	PMUM_POSR_PLL2REFD_MSK			SHIFT23(0x1f)	/* PLL2REFD */
#define	PMUM_POSR_PLL2REFD_BASE			23
#define	PMUM_POSR_PLL2FBD_MSK			SHIFT14(0x1ff)	/* PLL2FBD */
#define	PMUM_POSR_PLL2FBD_BASE			14
#define	PMUM_POSR_PLL1REFD_MSK			SHIFT9(0x1f)	/* PLL1REFD */
#define	PMUM_POSR_PLL1REFD_BASE			9
#define	PMUM_POSR_PLL1FBD_MSK			SHIFT0(0x1ff)	/* PLL1FBD */
#define	PMUM_POSR_PLL1FBD_BASE			0

/*	PMUM_SUCCR	0x0014	Slow UART (UART 1) Clock Generation Control Register */
#define	PMUM_SUCCR_UARTDIVN_MSK			SHIFT16(0x1fff)	/* UARTDIVN */
#define	PMUM_SUCCR_UARTDIVN_BASE		16
/*		Bit(s) PMUM_SUCCR_RSRV_15_13 reserved */
#define	PMUM_SUCCR_UARTDIVD_MSK			SHIFT0(0x1fff)	/* UARTDIVD */
#define	PMUM_SUCCR_UARTDIVD_BASE		0

/*	PMUM_VRCR	0x0018	VCXO Request Control Register */
/*		Bit(s) PMUM_VRCR_RSRV_31_9 reserved */
#define	PMUM_VRCR_SW_REQ				BIT_8				/* SW Request */
#define	PMUM_VRCR_REQ_POL_MSK			SHIFT4(0xf)			/* HW Request Polarity */
#define	PMUM_VRCR_REQ_POL_BASE			4
#define	PMUM_VRCR_REQ_EN_MSK			SHIFT0(0xf)			/* HW Request Enable */
#define	PMUM_VRCR_REQ_EN_BASE			0

/*	PMUM_CPRR	0x0020	Marvell CPU Programmable Reset Register */
/*		Bit(s) PMUM_CPRR_RSRV_31_7 reserved */
#define	PMUM_CPRR_SLAVE_R				BIT_6				/* SLAVE_R */
#define	PMUM_CPRR_DSRAMINT				BIT_5				/* DSRAMINT */
#define	PMUM_CPRR_WDTR					BIT_4				/* WDTR */
#define	PMUM_CPRR_BBR					BIT_3				/* BBR */
#define	PMUM_CPRR_DSPR					BIT_2				/* DSPR */
#define	PMUM_CPRR_APR					BIT_1				/* APR */
#define	PMUM_CPRR_CPR					BIT_0				/* CPR */

/*	PMUM_CCGR	0x0024	Marvell CPU Clock Gating Register */
#define	PMUM_CCGR_W_208M		BIT_31	/* W_208M */
#define	PMUM_CCGR_W_312M		BIT_30	/* W_312M */
/*		Bit(s) PMUM_CCGR_RSRV_29 reserved */
#define	PMUM_CCGR_G_LP52M		BIT_28	/* G_LP52M */
#define	PMUM_CCGR_G_LP26M		BIT_27	/* G_LP26M */
#define	PMUM_CCGR_G_104M		BIT_26	/* G_104M */
#define	PMUM_CCGR_G_78M			BIT_25	/* G_78M */
#define	PMUM_CCGR_G_52M			BIT_24	/* G_52M */
#define	PMUM_CCGR_G_48MHZ		BIT_23	/* G_48MHz */
#define	PMUM_CCGR_G_TWSI		BIT_22	/* G_TWSI */
#define	PMUM_CCGR_G_HFI2S		BIT_21	/* G_HFI2S */
#define	PMUM_CCGR_G_26M			BIT_20	/* G_26M */
#define	PMUM_CCGR_G_13M			BIT_19	/* G_13M */
#define	PMUM_CCGR_G_6_5M		BIT_18	/* G_6.5M */
#define	PMUM_CCGR_G_SUART		BIT_17	/* G_SUART */
/*		Bit(s) PMUM_CCGR_RSRV_16 reserved */
#define	PMUM_CCGR_APMU_624M		BIT_15	/* APMU_624M */
#define	PMUM_CCGR_APMU_PLL2		BIT_14	/* APMU_PLL2 */
#define	PMUM_CCGR_APMU_312M		BIT_13	/* APMU_312M */
#define	PMUM_CCGR_APMU_104M		BIT_12	/* APMU_104M */
#define	PMUM_CCGR_APMU_52M		BIT_11	/* APMU_52M */
#define	PMUM_CCGR_APMU_48M		BIT_10	/* APMU_48M */
#define	PMUM_CCGR_GPC			BIT_9	/* GPC */
#define	PMUM_CCGR_AP_FUART		BIT_8	/* AP_FUART */
#define	PMUM_CCGR_AP_52M		BIT_7	/* AP_52M */
#define	PMUM_CCGR_AP_HSTWSI		BIT_6	/* AP_HSTWSI */
#define	PMUM_CCGR_AP_HFI2S		BIT_5	/* AP_HFI2S */
#define	PMUM_CCGR_AP_26M		BIT_4	/* AP_26M */
#define	PMUM_CCGR_AP_13M		BIT_3	/* AP_13M */
#define	PMUM_CCGR_AP_6_5M		BIT_2	/* AP_6.5M */
#define	PMUM_CCGR_AP_SUART		BIT_1	/* AP_SUART */
/*		Bit(s) PMUM_CCGR_RSRV_0 reserved */

/*	PMUM_CRSR	0x0028	Marvell CPU Reset Status Register */
/*		Bit(s) PMUM_CRSR_RSRV_31_12 reserved */
#define	PMUM_CRSR_SWR_MSK				SHIFT8(0xf)			/* SWR */
#define	PMUM_CRSR_SWR_BASE				8
/*		Bit(s) PMUM_CRSR_RSRV_7_3 reserved */
#define	PMUM_CRSR_WDTR					BIT_2				/* WDTR */
/*		Bit(s) PMUM_CRSR_RSRV_1 reserved */
#define	PMUM_CRSR_POR					BIT_0				/* POR */

/*	PMUM_GPCR	0x0030	General Purpose Clock Generation Control Register */
#define	PMUM_GPCR_GPCDIVN_MSK		SHIFT16(0xffff)	/* GPCDIVN */
#define	PMUM_GPCR_GPCDIVN_BASE		16
#define	PMUM_GPCR_GPCDIVD_MSK		SHIFT0(0xffff)	/* GPCDIVD */
#define	PMUM_GPCR_GPCDIVD_BASE		0

/*	PMUM_PLL2CR	0x0034	PLL2 Control Register */
/*		Bit(s) PMUM_PLL2CR_RSRV_31_24 reserved */
#define	PMUM_PLL2CR_PLL2REFD_MSK		SHIFT19(0x1f)	/* PLL2 REFDIV */
#define	PMUM_PLL2CR_PLL2REFD_BASE		19
#define	PMUM_PLL2CR_PLL2FBD_MSK			SHIFT10(0x1ff)	/* PLL2 FBDIV */
#define	PMUM_PLL2CR_PLL2FBD_BASE		10
#define	PMUM_PLL2CR_CTRL				BIT_9			/* PLL2 activation control */
#define	PMUM_PLL2CR_EN					BIT_8			/* EN */
/*		Bit(s) PMUM_PLL2CR_RSRV_7_6 reserved */
/*		Bit(s) PMUM_PLL2CR_RSRV_5_0 reserved */

/*	PMUM_SCCR	0x0038	Slow Clock Control Register */
/*		Bit(s) PMUM_SCCR_RSRV_31_2 reserved */
#define	PMUM_SCCR_AFE_CLK_EN			BIT_1				/* AFE_CLK_EN */
#define	PMUM_SCCR_SCS					BIT_0				/* SCS */

/*	PMUM_MCCR	0x003C	MSA Clock Control Register */
/*		Bit(s) PMUM_MCCR_RSRV_31_2 reserved */
/* DSP Core Clock Frequency */
#define	PMUM_MCCR_DSP_FRQ				BIT_1
/* DSP Clock PLL source select */
#define	PMUM_MCCR_DSP_CLK				BIT_0

/*	PMUM_ISCCRx	0x0040	I2S Clock Generation Control Register */
#define	PMUM_ISCCRX_SYSCLK_EN				BIT_31			/* SYSCLK_EN */
#define	PMUM_ISCCRX_SYSCLK_BASE				BIT_30			/* SYSCLK_BASE */
#define	PMUM_ISCCRX_BITCLK_EN				BIT_29			/* BITCLK_EN */
#define	PMUM_ISCCRX_BITCLK_DIV_468_MSK		SHIFT27(0x3)	/* BITCLK_DIV_468 */
#define	PMUM_ISCCRX_BITCLK_DIV_468_BASE		27
#define	PMUM_ISCCRX_DENOM_MSK				SHIFT15(0xfff)	/* DENOM */
#define	PMUM_ISCCRX_DENOM_BASE				15
#define	PMUM_ISCCRX_NOM_MSK					SHIFT0(0x7fff)	/* NOM */
#define	PMUM_ISCCRX_NOM_BASE				0

/*	PMUM_CWUCRS	0x0048	Wakeup and Clock Resume Lines Status Register */
#define	PMUM_CWUCRS_BB_DROWSY_EN						BIT_31	/* Bb_drowsy_en */
/* Wakeup 0-7 status */
#define	PMUM_CWUCRS_ALL_WAKEUP							BIT_30
/* Feis_wanna_wake/Pm_bb_clkres */
#define	PMUM_CWUCRS_FEIS_WANNA_WAKE_PM_BB_CLKRES		BIT_29
#define	PMUM_CWUCRS_PM_XSC_CLKRES						BIT_28	/* Pm_xsc_clkres */
#define	PMUM_CWUCRS_GSM_WAKEUP							BIT_27	/* GSM Wakeup */
#define	PMUM_CWUCRS_WCDMA_WAKEUP						BIT_26	/* WCDMA Wakeup */
#define	PMUM_CWUCRS_AP_ASYNC_INT						BIT_25	/* AP ASYNC INT */
#define	PMUM_CWUCRS_AP_FULL_IDLE						BIT_24	/* AP Full idle */
#define	PMUM_CWUCRS_SDH1								BIT_23	/* SDH1 */
#define	PMUM_CWUCRS_SDH2								BIT_22	/* SDH2 */
#define	PMUM_CWUCRS_KEYPRESS							BIT_21	/* KeyPress */
#define	PMUM_CWUCRS_TRACKBALL							BIT_20	/* Trackball */
#define	PMUM_CWUCRS_NEWROTARY							BIT_19	/* NewRotary */
#define	PMUM_CWUCRS_WDT									BIT_18	/* WDT */
#define	PMUM_CWUCRS_RTC_ALARM							BIT_17	/* RTC ALARM */
#define	PMUM_CWUCRS_CP_TIMER_3							BIT_16	/* CP Timer 3 */
#define	PMUM_CWUCRS_CP_TIMER_2							BIT_15	/* CP Timer 2 */
#define	PMUM_CWUCRS_CP_TIMER_1							BIT_14	/* CP Timer 1 */
#define	PMUM_CWUCRS_AP2_TIMER_3							BIT_13	/* AP2 Timer 3 */
#define	PMUM_CWUCRS_AP2_TIMER_2							BIT_12	/* AP2 Timer 2 */
#define	PMUM_CWUCRS_AP2_TIMER_1							BIT_11	/* AP2 Timer 1 */
#define	PMUM_CWUCRS_AP1_TIMER_3							BIT_10	/* AP1 Timer 3 */
#define	PMUM_CWUCRS_AP1_TIMER_2							BIT_9	/* AP1 Timer 2 */
#define	PMUM_CWUCRS_AP1_TIMER_1							BIT_8	/* AP1 Timer 1 */
/* Wakeup6 line in status */
#define	PMUM_CWUCRS_WAKEUP6								BIT_6
/* Wakeup5 line in status */
#define	PMUM_CWUCRS_WAKEUP5								BIT_5
/* Wakeup4 line in status */
#define	PMUM_CWUCRS_WAKEUP4								BIT_4
/* Wakeup3 line in status */
#define	PMUM_CWUCRS_WAKEUP3								BIT_3
/* Wakeup2 line in status */
#define	PMUM_CWUCRS_WAKEUP2								BIT_2
/* Wakeup1 line in status */
#define	PMUM_CWUCRS_WAKEUP1								BIT_1
/* Wakeup0 line in status */
#define	PMUM_CWUCRS_WAKEUP0								BIT_0

/*	PMUM_CWUCRM	0x004C	Wakeup and Clock Resume Lines Mask Register */
/*		Bit(s) PMUM_CWUCRM_RSRV_30_31 reserved */
#define	PMUM_CWUCRM_GSM_WAKEUPWMX		BIT_29		/* GSM WakeupWMX */
#ifdef EDEN_1928
#define	PMUM_CWUCRM_WB_LTE_WAKEUPX		BIT_31		/* WCDMA WakeupX */
#define	PMUM_CWUCRM_TD_LTE_CP_D2_WAKEUPX BIT_31
#else
#define	PMUM_CWUCRM_WB_LTE_WAKEUPX		BIT_28		/* WCDMA WakeupX */
#define	PMUM_CWUCRM_TD_LTE_WAKEUPX		BIT_28		/* WCDMA WakeupX */
#endif
#define	PMUM_CWUCRM_GSM_WAKEUPWM		BIT_27		/* GSM WakeupWM */
#define	PMUM_CWUCRM_TD_LTE_WAKEUPWM		BIT_26		/* WCDMA WakeupWM */
#define	PMUM_CWUCRM_WB_LTE_WAKEUPWM		BIT_26		/* WCDMA WakeupWM */
#define	PMUM_CWUCRM_AP_ASYNC_INT		BIT_25		/* AP ASYNC INT */
#define	PMUM_CWUCRM_AP_FULL_IDLE		BIT_24		/* AP Full idle */
#define	PMUM_CWUCRM_SDH1				BIT_23		/* SDH1 */
#define	PMUM_CWUCRM_SDH2				BIT_22		/* SDH2 */
#define	PMUM_CWUCRM_KEYPRESS			BIT_21		/* KeyPress */
#define	PMUM_CWUCRM_Z3_LTE_WAKEUPWM	    BIT_20
#define	PMUM_CWUCRM_Z3_TD_WAKEUPWM	    BIT_19
#define	PMUM_CWUCRM_Z3_WB_WAKEUPWM	    BIT_19
#define	PMUM_CWUCRM_WDT					BIT_18		/* WDT */
#define	PMUM_CWUCRM_RTC_ALARM			BIT_17		/* RTC ALARM */
#define	PMUM_CWUCRM_CP_TIMER_3			BIT_16		/* CP Timer 3 */
#define	PMUM_CWUCRM_CP_TIMER_2			BIT_15		/* CP Timer 2 */
#define	PMUM_CWUCRM_CP_TIMER_1			BIT_14		/* CP Timer 1 */
#define	PMUM_CWUCRM_AP2_TIMER_3			BIT_13		/* AP2 Timer 3 */
#define	PMUM_CWUCRM_AP2_TIMER_2			BIT_12		/* AP2 Timer 2 */
#define	PMUM_CWUCRM_AP2_TIMER_1			BIT_11		/* AP2 Timer 1 */
#define	PMUM_CWUCRM_AP1_TIMER_3			BIT_10		/* AP1 Timer 3 */
#define	PMUM_CWUCRM_AP1_TIMER_2			BIT_9		/* AP1 Timer 2 */
#define	PMUM_CWUCRM_AP1_TIMER_1			BIT_8		/* AP1 Timer 1 */
#define	PMUM_CWUCRM_WAKEUP7				BIT_7		/* Wakeup7 */
#define	PMUM_CWUCRM_WAKEUP6				BIT_6		/* Wakeup6 */
#define	PMUM_CWUCRM_WAKEUP5				BIT_5		/* Wakeup5 */
#define	PMUM_CWUCRM_WAKEUP4				BIT_4		/* Wakeup4 */
#define	PMUM_CWUCRM_WAKEUP3				BIT_3		/* Wakeup3 */
#define	PMUM_CWUCRM_WAKEUP2				BIT_2		/* Wakeup2 */
#define	PMUM_CWUCRM_WAKEUP1				BIT_1		/* Wakeup1 */
#define	PMUM_CWUCRM_WAKEUP0				BIT_0		/* Wakeup0 */

/*	PMUM_DSOC	0x0100	Debug Signals Output Control Register */
/*		Bit(s) PMUM_DSOC_RSRV_31_9 reserved */
#define	PMUM_DSOC_TPCTL					BIT_8				/* TPCTL */
/*		Bit(s) PMUM_DSOC_RSRV_7 reserved */
#define	PMUM_DSOC_TPSEL_MSK				SHIFT0(0x7f)		/* TPSEL */
#define	PMUM_DSOC_TPSEL_BASE			0

/*	PMUM_WDTPCR	0x0200	WDT (Communication Subsystem Timers) Control Register */
/*		Bit(s) PMUM_WDTPCR_RSRV_31_7 reserved */
#define	PMUM_WDTPCR_FNCLKSEL_MSK		SHIFT4(0x7)			/* FNCLKSEL */
#define	PMUM_WDTPCR_FNCLKSEL_BASE		4
/*		Bit(s) PMUM_WDTPCR_RSRV_3 reserved */
#define	PMUM_WDTPCR_RST					BIT_2				/* RST */
#define	PMUM_WDTPCR_FNCLK				BIT_1				/* FNCLK */
#define	PMUM_WDTPCR_ABCLK				BIT_0				/* ABCLK */

/*	PMUM_CMPRx	0x0400	Marvell CPU Module Power Register */
/*		Bit(s) PMUM_CMPRX_RSRV_31_3 reserved */
#define	PMUM_CMPRX_MSR					BIT_2				/* MSR */
#define	PMUM_CMPRX_AG					BIT_1				/* AG */
#define	PMUM_CMPRX_MCE					BIT_0				/* MCE */

/*	PMUM_APCR	0x1000	Marvell CPU Power Control Register */
#define	PMUM_APCR_AXISD					BIT_31			/* AXISD */
#define	PMUM_APCR_DSPSD					BIT_30			/* DSPSD */
#define	PMUM_APCR_SLPEN					BIT_29			/* SLPEN */
#define	PMUM_APCR_DTCMSD				BIT_28			/* DTCMSD */
#define	PMUM_APCR_DDRCORSD				BIT_27			/* DDRCORSD */
#define	PMUM_APCR_APBSD					BIT_26			/* APBSD */
#define	PMUM_APCR_BBSD					BIT_25			/* BBSD */
#define	PMUM_APCR_INTCLR				BIT_24			/* INTCLR */
#define	PMUM_APCR_SLPWP0				BIT_23			/* SLPWP0 */
#define	PMUM_APCR_SLPWP1				BIT_22			/* SLPWP1 */
#define	PMUM_APCR_SLPWP2				BIT_21			/* SLPWP2 */
#define	PMUM_APCR_SLPWP3				BIT_20			/* SLPWP3 */
#define	PMUM_APCR_VCTCXOSD				BIT_19			/* VCTCXOSD */
#define	PMUM_APCR_SLPWP4				BIT_18			/* SLPWP4 */
#define	PMUM_APCR_SLPWP5				BIT_17			/* SLPWP5 */
#define	PMUM_APCR_SLPWP6				BIT_16			/* SLPWP6 */
#define	PMUM_APCR_SLPWP7				BIT_15			/* SLPWP7 */
#define	PMUM_APCR_MSASLPEN				BIT_14			/* MSASLPEN */

/*	PMUM_APSR	0x1004	Marvell CPU Power Status Register */
#define	PMUM_APSR_DSPIDL				BIT_31			/* DSPIDL */
#define	PMUM_APSR_APIDL					BIT_30			/* APIDL */
#define	PMUM_APSR_CPIDL					BIT_29			/* CPIDL */
#define	PMUM_APSR_DSPAVL				BIT_28			/* DSPAVL */
#define	PMUM_APSR_AP_FULL_IDLE			BIT_27			/* AP_FULL_IDLE */
#define	PMUM_APSR_CP_FULL_IDLE			BIT_26			/* CP_FULL_IDLE */
#define	PMUM_APSR_AP_SS_SLEEP			BIT_25			/* AP_SS_SLEEP */
#define	PMUM_APSR_CP_SS_SLEEP			BIT_24			/* CP_SS_SLEEP */
/*		Bit(s) PMUM_APSR_RSRV_23_21 reserved */
/*		Bit(s) PMUM_APSR_RSRV_20 reserved */
/*		Bit(s) PMUM_APSR_RSRV_19_17 reserved */
/*		Bit(s) PMUM_APSR_RSRV_16_0 reserved */

/*	PMUM_APRR	0x1020	Marvell CPU Programmable Reset Register */
/*		Bit(s) PMUM_APRR_RSRV_31_7 reserved */
#define	PMUM_APRR_SLAVE_R				BIT_6				/* SLAVE_R */
/*		Bit(s) PMUM_APRR_RSRV_5 reserved */
#define	PMUM_APRR_WDTR					BIT_4				/* WDTR */
/*		Bit(s) PMUM_APRR_RSRV_3 reserved */
#define	PMUM_APRR_DSPR					BIT_2				/* DSPR */
#define	PMUM_APRR_APR					BIT_1				/* APR */
#define	PMUM_APRR_CPR					BIT_0				/* CPR */

/*	PMUM_ACGR	0x1024	Marvell CPU Clock Gating Register */
#define	PMUM_ACGR_W_208M		BIT_31	/* W_208M */
#define	PMUM_ACGR_W_312M		BIT_30	/* W_312M */
/*		Bit(s) PMUM_ACGR_RSRV_29 reserved */
#define	PMUM_ACGR_G_LP52M		BIT_28	/* G_LP52M */
#define	PMUM_ACGR_G_LP26M		BIT_27	/* G_LP26M */
#define	PMUM_ACGR_G_104M		BIT_26	/* G_104M */
#define	PMUM_ACGR_G_78M			BIT_25	/* G_78M */
#define	PMUM_ACGR_G_52M			BIT_24	/* G_52M */
#define	PMUM_ACGR_G_48MHZ		BIT_23	/* G_48MHz */
#define	PMUM_ACGR_G_TWSI		BIT_22	/* G_TWSI */
#define	PMUM_ACGR_G_HFI2S		BIT_21	/* G_HFI2S */
#define	PMUM_ACGR_G_26M			BIT_20	/* G_26M */
#define	PMUM_ACGR_G_13M			BIT_19	/* G_13M */
#define	PMUM_ACGR_G_6_5M		BIT_18	/* G_6.5M */
#define	PMUM_ACGR_G_SUART		BIT_17	/* G_SUART */
/*		Bit(s) PMUM_ACGR_RSRV_16 reserved */
#define	PMUM_ACGR_APMU_624M		BIT_15	/* APMU_624M */
#define	PMUM_ACGR_APMU_PLL2		BIT_14	/* APMU_PLL2 */
#define	PMUM_ACGR_APMU_312M		BIT_13	/* APMU_312M */
#define	PMUM_ACGR_APMU_104M		BIT_12	/* APMU_104M */
#define	PMUM_ACGR_APMU_52M		BIT_11	/* APMU_52M */
#define	PMUM_ACGR_APMU_48M		BIT_10	/* APMU_48M */
#define	PMUM_ACGR_GPC			BIT_9	/* GPC */
#define	PMUM_ACGR_AP_FUART		BIT_8	/* AP_FUART */
#define	PMUM_ACGR_AP_52M		BIT_7	/* AP_52M */
#define	PMUM_ACGR_AP_HSTWSI		BIT_6	/* AP_HSTWSI */
#define	PMUM_ACGR_AP_HFI2S		BIT_5	/* AP_HFI2S */
#define	PMUM_ACGR_AP_26M		BIT_4	/* AP_26M */
#define	PMUM_ACGR_AP_13M		BIT_3	/* AP_13M */
#define	PMUM_ACGR_AP_6_5M		BIT_2	/* AP_6.5M */
#define	PMUM_ACGR_AP_SUART		BIT_1	/* AP_SUART */
/*		Bit(s) PMUM_ACGR_RSRV_0 reserved */

/*	PMUM_ARSR	0x1028	Marvell CPU Reset Status Register */
/*		Bit(s) PMUM_ARSR_RSRV_31_12 reserved */
#define	PMUM_ARSR_SWR_MSK				SHIFT8(0xf)			/* SWR */
#define	PMUM_ARSR_SWR_BASE				8
/*		Bit(s) PMUM_ARSR_RSRV_7_3 reserved */
#define	PMUM_ARSR_WDTR					BIT_2				/* WDTR */
/*		Bit(s) PMUM_ARSR_RSRV_1 reserved */
#define	PMUM_ARSR_POR					BIT_0				/* POR */

/*	PMUM_AWUCRS	0x1048	Wakeup and Clock Resume Lines Status Register */
#define	PMUM_AWUCRS_BB_DROWSY_EN		BIT_31	/* Bb_drowsy_en */
#define	PMUM_AWUCRS_ALL_WAKEUP			BIT_30	/* Wakeup 0-7 status */
#define	PMUM_AWUCRS_PM_BB_CLKRES		BIT_29	/* Pm_bb_clkres */
#define	PMUM_AWUCRS_PM_XSC_CLKRES		BIT_28	/* Pm_xsc_clkres */
#define	PMUM_AWUCRS_GSM_WAKEUP			BIT_27	/* GSM Wakeup */
#define	PMUM_AWUCRS_WCDMA_WAKEUP		BIT_26	/* WCDMA Wakeup */
#define	PMUM_AWUCRS_AP_ASYNC_INT		BIT_25	/* AP ASYNC INT */
#define	PMUM_AWUCRS_AP_FULL_IDLE		BIT_24	/* AP Full idle */
#define	PMUM_AWUCRS_SDH1				BIT_23	/* SDH1 */
#define	PMUM_AWUCRS_SDH2				BIT_22	/* SDH2 */
#define	PMUM_AWUCRS_KEYPRESS			BIT_21	/* KeyPress */
#define	PMUM_AWUCRS_TRACKBALL			BIT_20	/* Trackball */
#define	PMUM_AWUCRS_NEWROTARY			BIT_19	/* NewRotary */
#define	PMUM_AWUCRS_WDT					BIT_18	/* WDT */
#define	PMUM_AWUCRS_RTC_ALARM			BIT_17	/* RTC ALARM */
#define	PMUM_AWUCRS_CP_TIMER_3			BIT_16	/* CP Timer 3 */
#define	PMUM_AWUCRS_CP_TIMER_2			BIT_15	/* CP Timer 2 */
#define	PMUM_AWUCRS_CP_TIMER_1			BIT_14	/* CP Timer 1 */
#define	PMUM_AWUCRS_AP2_TIMER_3			BIT_13	/* AP2 Timer 3 */
#define	PMUM_AWUCRS_AP2_TIMER_2			BIT_12	/* AP2 Timer 2 */
#define	PMUM_AWUCRS_AP2_TIMER_1			BIT_11	/* AP2 Timer 1 */
#define	PMUM_AWUCRS_AP1_TIMER_3			BIT_10	/* AP1 Timer 3 */
#define	PMUM_AWUCRS_AP1_TIMER_2			BIT_9	/* AP1 Timer 2 */
#define	PMUM_AWUCRS_AP1_TIMER_1			BIT_8	/* AP1 Timer 1 */
#define	PMUM_AWUCRS_WAKEUP6				BIT_6	/* Wakeup6 line in status */
#define	PMUM_AWUCRS_WAKEUP5				BIT_5	/* Wakeup5 line in status */
#define	PMUM_AWUCRS_WAKEUP4				BIT_4	/* Wakeup4 line in status */
#define	PMUM_AWUCRS_WAKEUP3				BIT_3	/* Wakeup3 line in status */
#define	PMUM_AWUCRS_WAKEUP2				BIT_2	/* Wakeup2 line in status */
#define	PMUM_AWUCRS_WAKEUP1				BIT_1	/* Wakeup1 line in status */
#define	PMUM_AWUCRS_WAKEUP0				BIT_0	/* Wakeup0 line in status */

/*	PMUM_AWUCRM	0x104C	Wakeup and Clock Resume Lines Mask Register */
/*		Bit(s) PMUM_AWUCRM_RSRV_30_31 reserved */
#define	PMUM_AWUCRM_GSM_WAKEUPWMX		BIT_29		/* GSM WakeupWMX */
#define	PMUM_AWUCRM_WCDMA_WAKEUPX		BIT_28		/* WCDMA WakeupX */
#define	PMUM_AWUCRM_GSM_WAKEUPWM		BIT_27		/* GSM WakeupWM */
#define	PMUM_AWUCRM_WCDMA_WAKEUPWM		BIT_26		/* WCDMA WakeupWM */
#define	PMUM_AWUCRM_AP_ASYNC_INT		BIT_25		/* AP ASYNC INT */
#define	PMUM_AWUCRM_AP_FULL_IDLE		BIT_24		/* AP Full idle */
#define	PMUM_AWUCRM_SDH1				BIT_23		/* SDH1 */
#define	PMUM_AWUCRM_SDH2				BIT_22		/* SDH2 */
#define	PMUM_AWUCRM_KEYPRESS			BIT_21		/* KeyPress */
#define	PMUM_AWUCRM_TRACKBALL			BIT_20		/* Trackball */
#define	PMUM_AWUCRM_NEWROTARY			BIT_19		/* NewRotary */
#define	PMUM_AWUCRM_WDT					BIT_18		/* WDT */
#define	PMUM_AWUCRM_RTC_ALARM			BIT_17		/* RTC ALARM */
#define	PMUM_AWUCRM_CP_TIMER_3			BIT_16		/* CP Timer 3 */
#define	PMUM_AWUCRM_CP_TIMER_2			BIT_15		/* CP Timer 2 */
#define	PMUM_AWUCRM_CP_TIMER_1			BIT_14		/* CP Timer 1 */
#define	PMUM_AWUCRM_AP2_TIMER_3			BIT_13		/* AP2 Timer 3 */
#define	PMUM_AWUCRM_AP2_TIMER_2			BIT_12		/* AP2 Timer 2 */
#define	PMUM_AWUCRM_AP2_TIMER_1			BIT_11		/* AP2 Timer 1 */
#define	PMUM_AWUCRM_AP1_TIMER_3			BIT_10		/* AP1 Timer 3 */
#define	PMUM_AWUCRM_AP1_TIMER_2			BIT_9		/* AP1 Timer 2 */
#define	PMUM_AWUCRM_AP1_TIMER_1			BIT_8		/* AP1 Timer 1 */
#define	PMUM_AWUCRM_WAKEUP7				BIT_7		/* Wakeup7 */
#define	PMUM_AWUCRM_WAKEUP6				BIT_6		/* Wakeup6 */
#define	PMUM_AWUCRM_WAKEUP5				BIT_5		/* Wakeup5 */
#define	PMUM_AWUCRM_WAKEUP4				BIT_4		/* Wakeup4 */
#define	PMUM_AWUCRM_WAKEUP3				BIT_3		/* Wakeup3 */
#define	PMUM_AWUCRM_WAKEUP2				BIT_2		/* Wakeup2 */
#define	PMUM_AWUCRM_WAKEUP1				BIT_1		/* Wakeup1 */
#define	PMUM_AWUCRM_WAKEUP0				BIT_0		/* Wakeup0 */



//20090625, apmu.h.

/*
 *
 *	THE BASE ADDRESSES
 *
 */
#define	PMUA_BASE	0xD4282800

/*
 *
 *	THE REGISTER DEFINES
 *
 */
#define	PMUA_CC_SEA					(PMUA_BASE+0x0000)	/* 32 bit	<var
														 *			Processor:
														 *			Osprey>
														 *			Clock
														 *			Control
														 *			Register
														 */
#define	PMUA_CC_MOH					(PMUA_BASE+0x0004)	/* 32 bit	<var
														 *			Processor:
														 *			Mohawk>
														 *			Clock
														 *			Control
														 *			Register
														 */
#define	PMUA_DM_CC_SEA				(PMUA_BASE+0x0008)	/* 32 bit	<var
														 *			Processor:
														 *			Osprey>
														 *			Clock
														 *			Control
														 *			Status
														 *			Register
														 */
#define	PMUA_DM_CC_MOH				(PMUA_BASE+0x000C)	/* 32 bit	<var
														 *			Processor:
														 *			Mohawk>
														 *			Clock
														 *			Control
														 *			Status
														 *			Register
														 */
#define	PMUA_FC_TIMER				(PMUA_BASE+0x0010)	/* 32 bit	Frequency
														 *			Change
														 *			Timer
														 *			Register
														 */
#define	PMUA_SEA_IDLE_CFG			(PMUA_BASE+0x0014)	/* 32 bit	<var
														 *			Processor:
														 *			Osprey>
														 *			Idle
														 *			Configuration
														 *			Register
														 */
#define	PMUA_MOH_IDLE_CFG			(PMUA_BASE+0x0018)	/* 32 bit	<var
														 *			Processor:
														 *			Mohawk>
														 *			Idle
														 *			Configuration
														 *			Register
														 */
#define	PMUA_SQU_CLK_GATE_CTRL		(PMUA_BASE+0x001C)	/* 32 bit	SQU Dynamic
														 *			Clock
														 *			Gate
														 *			Control
														 *			Register
														 */
#define	PMUA_IRE_CLK_GATE_CTRL		(PMUA_BASE+0x0020)	/* 32 bit	IRE Dynamic
														 *			Clock
														 *			Gate
														 *			Control
														 *			Register
														 */
#define	PMUA_CCIC_CLK_GATE_CTRL		(PMUA_BASE+0x0028)	/* 32 bit	CCIC
														 *			Dynamic
														 *			Clock
														 *			Gate
														 *			Control
														 *			Register
														 */
#define	PMUA_FBRC1_CLK_GATE_CTRL	(PMUA_BASE+0x002C)	/* 32 bit	Fabric 1
														 *			Dynamic
														 *			Clock
														 *			Gate
														 *			Control
														 *			Register
														 */
#define	PMUA_FBRC2_CLK_GATE_CTRL	(PMUA_BASE+0x0030)	/* 32 bit	Fabric 2
														 *			Dynamic
														 *			Clock
														 *			Gate
														 *			Control
														 *			Register
														 */
#define	PMUA_USB_CLK_GATE_CTRL		(PMUA_BASE+0x0034)	/* 32 bit	USB Dynamic
														 *			Clock
														 *			Gate
														 *			Control
														 *			Register
														 */
#define	PMUA_PMU_CLK_GATE_CTRL		(PMUA_BASE+0x0040)	/* 32 bit	PMU Dynamic
														 *			Clock
														 *			Gate
														 *			Control
														 *			Register
														 */
#define	PMUA_IRE_CLK_RES_CTRL		(PMUA_BASE+0x0048)	/* 32 bit	IRE
														 *			Clock/Reset
														 *			Control
														 *			Register
														 */
#define	PMUA_LCD_CLK_RES_CTRL		(PMUA_BASE+0x004C)	/* 32 bit	LCD
														 *			Clock/Reset
														 *			Control
														 *			Register
														 */
#define	PMUA_CCIC_CLK_RES_CTRL		(PMUA_BASE+0x0050)	/* 32 bit	CCIC
														 *			Clock/Reset
														 *			Control
														 *			Register
														 */
#define	PMUA_SDH0_CLK_RES_CTRL		(PMUA_BASE+0x0054)	/* 32 bit	SDIO Host 0
														 *			Clock/Reset
														 *			Control
														 *			Register
														 */
#define	PMUA_SDH1_CLK_RES_CTRL		(PMUA_BASE+0x0058)	/* 32 bit	SDIO Host 1
														 *			Clock/Reset
														 *			Control
														 *			Register
														 */
#define	PMUA_USB_CLK_RES_CTRL		(PMUA_BASE+0x005C)	/* 32 bit	USB
														 *			Clock/Reset
														 *			Control
														 *			Register
														 */
#define	PMUA_NF_CLK_RES_CTRL		(PMUA_BASE+0x0060)	/* 32 bit	NAND Flash
														 *			Clock/Reset
														 *			Control
														 *			Register
														 */
#define	PMUA_DMA_CLK_RES_CTRL		(PMUA_BASE+0x0064)	/* 32 bit	DMA
														 *			Clock/Reset
														 *			Control
														 *			Register
														 */
#define	PMUA_GEU_CLK_RES_CTRL		(PMUA_BASE+0x0068)	/* 32 bit	GEU
														 *			Clock/Reset
														 *			Control
														 *			Register
														 */
#define	PMUA_BUS_CLK_RES_CTRL		(PMUA_BASE+0x006C)	/* 32 bit	Bus
														 *			Clock/Reset
														 *			Control
														 *			Register
														 */
#define	PMUA_SEA_IMR				(PMUA_BASE+0x0070)	/* 32 bit	PMU <var
														 *			Processor:
														 *			Osprey>
														 *			Interrupt
														 *			Mask
														 *			Register
														 */
#define	PMUA_SEA_IRWC				(PMUA_BASE+0x0074)	/* 32 bit	PMU <var
														 *			Processor:
														 *			Osprey>
														 *			Interrupt
														 *			READ/WRITE
														 *			Clear
														 *			Register
														 */
#define	PMUA_SEA_ISR				(PMUA_BASE+0x0078)	/* 32 bit	PMU <var
														 *			Processor:
														 *			Osprey>
														 *			Interrupt
														 *			Status
														 *			Register
														 */
#define	PMUA_SD_ROT_WAKE_CLR		(PMUA_BASE+0x007C)	/* 32 bit	SDIO/Rotary
														 *			Wake
														 *			Clear
														 *			Register
														 */
#define	PMUA_PWR_STBL_TIMER			(PMUA_BASE+0x0084)	/* 32 bit	Power
														 *			Stable
														 *			Timer
														 *			Register
														 */
#define	PMUA_SRAM_PWR_DWN			(PMUA_BASE+0x008C)	/* 32 bit	Core SRAM
														 *			Power
														 *			Down
														 *			Register
														 */
#define	PMUA_CORE_STATUS			(PMUA_BASE+0x0090)	/* 32 bit	Core Status
														 *			Register
														 */
#define	PMUA_RES_FRM_SLP_CLR		(PMUA_BASE+0x0094)	/* 32 bit	Resume from
														 *			Sleep
														 *			Clear
														 *			Register
														 */
#define	PMUA_MOH_IMR				(PMUA_BASE+0x0098)	/* 32 bit	PMU <var
														 *			Processor:
														 *			Mohawk>
														 *			Interrupt
														 *			Mask
														 *			Register
														 */
#define	PMUA_MOH_IRWC				(PMUA_BASE+0x009C)	/* 32 bit	PMU <var
														 *			Processor:
														 *			Mohawk>
														 *			Interrupt
														 *			READ/WRITE
														 *			Clear
														 *			Register
														 */
#define	PMUA_MOH_ISR				(PMUA_BASE+0x00A0)	/* 32 bit	PMU <var
														 *			Processor:
														 *			Mohawk>
														 *			Interrupt
														 *			Status
														 *			Register
														 */
#define	PMUA_DTC_CLK_RES_CTRL		(PMUA_BASE+0x00AC)	/* 32 bit	DTC
														 *			Clock/Reset
														 *			Control
														 *			Register
														 */
#define	PMUA_MC_HW_SLP_TYPE			(PMUA_BASE+0x00B0)	/* 32 bit	Memory
														 *			Controller
														 *			Hardware
														 *			Sleep
														 *			Type
														 *			Register
														 */
#define	PMUA_MC_SLP_REQ_MOH			(PMUA_BASE+0x00B4)	/* 32 bit	Memory
														 *			Controller
														 *			<var
														 *			Processor:
														 *			Mohawk>
														 *			Sleep
														 *			Request
														 *			Register
														 */
#define	PMUA_MC_SLP_REQ_SEA			(PMUA_BASE+0x00B8)	/* 32 bit	Memory
														 *			Controller
														 *			<var
														 *			Processor:
														 *			Osprey>
														 *			Sleep
														 *			Request
														 *			Register
														 */
#define	PMUA_MC_SLP_REQ_MSA			(PMUA_BASE+0x00BC)	/* 32 bit	Memory
														 *			Controller
														 *			MSA Sleep
														 *			Request
														 *			Register
														 */
#define	PMUA_MC_SW_SLP_TYPE			(PMUA_BASE+0x00C0)	/* 32 bit	Memory
														 *			Controller
														 *			Software
														 *			Sleep
														 *			Type
														 *			Register
														 */
#define	PMUA_PLL_SEL_STATUS			(PMUA_BASE+0x00C4)	/* 32 bit	PLL Clock
														 *			Select
														 *			Status
														 *			Register
														 */
#define	PMUA_GC_CLK_RES_CTRL		(PMUA_BASE+0x00CC)	/* 32 bit	2D/3D
														 *			Graphics
														 *			Controller
														 *			Clock/Reset
														 *			Control
														 *			Register
														 */
#define	PMUA_GC_PWRDWN				(PMUA_BASE+0x00D0)	/* 32 bit	2D/3D
														 *			Graphics
														 *			Controller
														 *			Power
														 *			Down
														 *			Register
														 */
#define	PMUA_SMC_CLK_RES_CTRL		(PMUA_BASE+0x00D4)	/* 32 bit	SMC
														 *			Clock/Reset
														 *			Control
														 *			Register
														 */

/*
 *
 *	THE BIT DEFINES
 *
 */
/*	PMUA_CC_SEA					0x0000	<var Processor: Osprey> Clock Control
 *										Register
 */
#define	PMUA_CC_SEA_SEA_RD_ST_CLEAR			BIT_31			/* RD_ST Clear */
/* Dynamic ACLK Clock Change */
#define	PMUA_CC_SEA_ACLK_DYN_FC				BIT_30
/* Dynamic DCLK Clock Change */
#define	PMUA_CC_SEA_DCLK_DYN_FC				BIT_29
/* Dynamic Core Clock Change */
#define	PMUA_CC_SEA_CORE_DYN_FC				BIT_28
/* <var Processor: Osprey> Speed Change Voting */
#define	PMUA_CC_SEA_SEA_ALLOW_SPD_CHG		BIT_27
/* ACLK Frequency Change Request */
#define	PMUA_CC_SEA_BUS_FREQ_CHG_REQ		BIT_26
/* DCLK Frequency Change Request */
#define	PMUA_CC_SEA_DDR_FREQ_CHG_REQ		BIT_25
/* <var Processor: Osprey> Frequency Change Request */
#define	PMUA_CC_SEA_SEA_FREQ_CHG_REQ		BIT_24
/* <var Processor: Mohawk> Bus Interface Sync with Bus Interface */
#define	PMUA_CC_SEA_ASYNC5					BIT_23
/* <var Processor: Osprey> Bus Interface Sync with Bus Interface */
#define	PMUA_CC_SEA_ASYNC4					BIT_22
/* AXI Bus Interface Sync with DDR Controller */
#define	PMUA_CC_SEA_ASYNC3_1				BIT_21
/* AXI Bus Interface Sync with DDR Controller */
#define	PMUA_CC_SEA_ASYNC3					BIT_20
/* <var Processor: Mohawk> Bus Interface Sync with DDR Controller */
#define	PMUA_CC_SEA_ASYNC2					BIT_19
/* <var Processor: Osprey> Bus Interface Sync with DDR Controller */
#define	PMUA_CC_SEA_ASYNC1					BIT_18
/* Clock Divider Selection for ACLK */
#define	PMUA_CC_SEA_BUS_CLK_DIV_MSK			SHIFT15(0x7)
#define	PMUA_CC_SEA_BUS_CLK_DIV_BASE		15
/* Clock Divider Selection for DCLK */
#define	PMUA_CC_SEA_DDR_CLK_DIV_MSK			SHIFT12(0x7)
#define	PMUA_CC_SEA_DDR_CLK_DIV_BASE		12
/* Clock Divider Selection for XPCLK */
#define	PMUA_CC_SEA_XP_CLK_DIV_MSK			SHIFT9(0x7)
#define	PMUA_CC_SEA_XP_CLK_DIV_BASE			9
/* Clock Divider Selection for BACLK1 */
#define	PMUA_CC_SEA_BIU_CLK_DIV_MSK			SHIFT6(0x7)
#define	PMUA_CC_SEA_BIU_CLK_DIV_BASE		6
/* Clock Divider Selection for PDCLK1 */
#define	PMUA_CC_SEA_BUS_MC_CLK_DIV_MSK		SHIFT3(0x7)
#define	PMUA_CC_SEA_BUS_MC_CLK_DIV_BASE		3
/* Clock Divider Selection for PCLK */
#define	PMUA_CC_SEA_CORE_CLK_DIV_MSK		SHIFT0(0x7)
#define	PMUA_CC_SEA_CORE_CLK_DIV_BASE		0

/*	PMUA_CC_MOH					0x0004	<var Processor: Mohawk> Clock Control
 *										Register
 */
#define	PMUA_CC_MOH_MOH_RD_ST_CLEAR			BIT_31			/* RD_ST Clear */
/* Dynamic ACLK Clock Change */
#define	PMUA_CC_MOH_ACLK_DYN_FC				BIT_30
/* Dynamic DCLK Clock Change */
#define	PMUA_CC_MOH_DCLK_DYN_FC				BIT_29
/* Dynamic Core Clock Change */
#define	PMUA_CC_MOH_CORE_DYN_FC				BIT_28
/* <var Processor: Mohawk> Speed Change Voting */
#define	PMUA_CC_MOH_MOH_ALLOW_SPD_CHG		BIT_27
/* ACLK Frequency Change Request */
#define	PMUA_CC_MOH_BUS_FREQ_CHG_REQ		BIT_26
/* DCLK Frequency Change Request */
#define	PMUA_CC_MOH_DDR_FREQ_CHG_REQ		BIT_25
/* <var Processor: Mohawk> Frequency Change Request */
#define	PMUA_CC_MOH_MOH_FREQ_CHG_REQ		BIT_24
/* <var Processor: Mohawk> Bus Interface Sync with Bus Interface */
#define	PMUA_CC_MOH_ASYNC5					BIT_23
/* <var Processor: Osprey> Bus Interface Sync with Bus Interface */
#define	PMUA_CC_MOH_ASYNC4					BIT_22
/* AXI Bus Interface Sync with DDR Controller */
#define	PMUA_CC_MOH_ASYNC3_1				BIT_21
/* AXI Bus Interface Sync with DDR Controller */
#define	PMUA_CC_MOH_ASYNC3					BIT_20
/* <var Processor: Mohawk> Bus Interface Sync with DDR Controller */
#define	PMUA_CC_MOH_ASYNC2					BIT_19
/* <var Processor: Osprey> Bus Interface Sync with DDR Controller */
#define	PMUA_CC_MOH_ASYNC1					BIT_18
/* Clock Divider Selection for ACLK */
#define	PMUA_CC_MOH_BUS_CLK_DIV_MSK			SHIFT15(0x7)
#define	PMUA_CC_MOH_BUS_CLK_DIV_BASE		15
/* Clock Divider Selection for DCLK */
#define	PMUA_CC_MOH_DDR_CLK_DIV_MSK			SHIFT12(0x7)
#define	PMUA_CC_MOH_DDR_CLK_DIV_BASE		12
/* Clock Divider Selection for XPCLK */
#define	PMUA_CC_MOH_XP_CLK_DIV_MSK			SHIFT9(0x7)
#define	PMUA_CC_MOH_XP_CLK_DIV_BASE			9
/* Clock Divider Selection for BACLK1 */
#define	PMUA_CC_MOH_BIU_CLK_DIV_MSK			SHIFT6(0x7)
#define	PMUA_CC_MOH_BIU_CLK_DIV_BASE		6
/* Clock Divider Selection for PDCLK1 */
#define	PMUA_CC_MOH_BUS_MC_CLK_DIV_MSK		SHIFT3(0x7)
#define	PMUA_CC_MOH_BUS_MC_CLK_DIV_BASE		3
/* Clock Divider Selection for PCLK */
#define	PMUA_CC_MOH_CORE_CLK_DIV_MSK		SHIFT0(0x7)
#define	PMUA_CC_MOH_CORE_CLK_DIV_BASE		0

/*	PMUA_DM_CC_SEA				0x0008	<var Processor: Osprey> Clock Control
 *										Status Register
 */
/*		Bit(s) PMUA_DM_CC_SEA_RSRV_31_26 reserved */
/* <var Processor: Mohawk> Read Status */
#define	PMUA_DM_CC_SEA_MOH_RD_STATUS			BIT_25
/* <var Processor: Osprey> Read Status */
#define	PMUA_DM_CC_SEA_SEA_RD_STATUS			BIT_24
/* <var Processor: Mohawk> Bus Interface Sync with Bus Interface */
#define	PMUA_DM_CC_SEA_ASYNC5					BIT_23
/* <var Processor: Osprey> Bus Interface Sync with Bus Interface */
#define	PMUA_DM_CC_SEA_ASYNC4					BIT_22
/* AXI Bus Interface Sync with DDR Controller */
#define	PMUA_DM_CC_SEA_ASYNC3_1					BIT_21
/* AXI Bus Interface Sync with DDR Controller */
#define	PMUA_DM_CC_SEA_ASYNC3					BIT_20
/* <var Processor: Mohawk> Bus Interface Sync with DDR Controller */
#define	PMUA_DM_CC_SEA_ASYNC2					BIT_19
/* <var Processor: Osprey> Bus Interface Sync with DDR Controller */
#define	PMUA_DM_CC_SEA_ASYNC1					BIT_18
/* Clock Divider Selection for ACLK */
#define	PMUA_DM_CC_SEA_BUS_CLK_DIV_MSK			SHIFT15(0x7)
#define	PMUA_DM_CC_SEA_BUS_CLK_DIV_BASE			15
/* Clock Divider Selection for DCLK */
#define	PMUA_DM_CC_SEA_DDR_CLK_DIV_MSK			SHIFT12(0x7)
#define	PMUA_DM_CC_SEA_DDR_CLK_DIV_BASE			12
/* Clock Divider Selection for XPCLK */
#define	PMUA_DM_CC_SEA_XP_CLK_DIV_MSK			SHIFT9(0x7)
#define	PMUA_DM_CC_SEA_XP_CLK_DIV_BASE			9
/* Clock Divider Selection for BACLK1 */
#define	PMUA_DM_CC_SEA_BIU_CLK_DIV_MSK			SHIFT6(0x7)
#define	PMUA_DM_CC_SEA_BIU_CLK_DIV_BASE			6
/* Clock Divider Selection for PDCLK1 */
#define	PMUA_DM_CC_SEA_BUS_MC_CLK_DIV_MSK		SHIFT3(0x7)
#define	PMUA_DM_CC_SEA_BUS_MC_CLK_DIV_BASE		3
/* Clock Divider Selection for PCLK */
#define	PMUA_DM_CC_SEA_CORE_CLK_DIV_MSK			SHIFT0(0x7)
#define	PMUA_DM_CC_SEA_CORE_CLK_DIV_BASE		0

/*	PMUA_DM_CC_MOH				0x000C	<var Processor: Mohawk> Clock Control
 *										Status Register
 */
/*		Bit(s) PMUA_DM_CC_MOH_RSRV_31_26 reserved */
/* <var Processor: Mohawk> Read Status */
#define	PMUA_DM_CC_MOH_MOH_RD_STATUS			BIT_25
/* <var Processor: Osprey> Read Status */
#define	PMUA_DM_CC_MOH_SEA_RD_STATUS			BIT_24
/* <var Processor: Mohawk> Bus Interface Sync with Bus Interface */
#define	PMUA_DM_CC_MOH_ASYNC5					BIT_23
/* <var Processor: Osprey> Bus Interface Sync with Bus Interface */
#define	PMUA_DM_CC_MOH_ASYNC4					BIT_22
/* AXI Bus Interface Sync with DDR Controller */
#define	PMUA_DM_CC_MOH_ASYNC3_1					BIT_21
/* AXI Bus Interface Sync with DDR Controller */
#define	PMUA_DM_CC_MOH_ASYNC3					BIT_20
/* <var Processor: Mohawk> Bus Interface Sync with DDR Controller */
#define	PMUA_DM_CC_MOH_ASYNC2					BIT_19
/* <var Processor: Osprey> Bus Interface Sync with DDR Controller */
#define	PMUA_DM_CC_MOH_ASYNC1					BIT_18
/* Clock Divider Selection for ACLK */
#define	PMUA_DM_CC_MOH_BUS_CLK_DIV_MSK			SHIFT15(0x7)
#define	PMUA_DM_CC_MOH_BUS_CLK_DIV_BASE			15
/* Clock Divider Selection for DCLK */
#define	PMUA_DM_CC_MOH_DDR_CLK_DIV_MSK			SHIFT12(0x7)
#define	PMUA_DM_CC_MOH_DDR_CLK_DIV_BASE			12
/* Clock Divider Selection for XPCLK */
#define	PMUA_DM_CC_MOH_XP_CLK_DIV_MSK			SHIFT9(0x7)
#define	PMUA_DM_CC_MOH_XP_CLK_DIV_BASE			9
/* Clock Divider Selection for BACLK1 */
#define	PMUA_DM_CC_MOH_BIU_CLK_DIV_MSK			SHIFT6(0x7)
#define	PMUA_DM_CC_MOH_BIU_CLK_DIV_BASE			6
/* Clock Divider Selection for PDCLK1 */
#define	PMUA_DM_CC_MOH_BUS_MC_CLK_DIV_MSK		SHIFT3(0x7)
#define	PMUA_DM_CC_MOH_BUS_MC_CLK_DIV_BASE		3
/* Clock Divider Selection for PCLK */
#define	PMUA_DM_CC_MOH_CORE_CLK_DIV_MSK			SHIFT0(0x7)
#define	PMUA_DM_CC_MOH_CORE_CLK_DIV_BASE		0

/*	PMUA_FC_TIMER				0x0010	Frequency Change Timer Register */
/*		Bit(s) PMUA_FC_TIMER_RSRV_31_24 reserved */
#define	PMUA_FC_TIMER_FC_CLK_PRE_MSK		SHIFT19(0x1f)	/* Clock Prescaler */
#define	PMUA_FC_TIMER_FC_CLK_PRE_BASE		19
/* Frequency Change Timer */
#define	PMUA_FC_TIMER_FC_TIMER_MSK			SHIFT3(0xffff)
#define	PMUA_FC_TIMER_FC_TIMER_BASE			3
#define	PMUA_FC_TIMER_FC_TIMER_SEL_MSK		SHIFT1(0x3)		/* Timer Select */
#define	PMUA_FC_TIMER_FC_TIMER_SEL_BASE		1
#define	PMUA_FC_TIMER_FC_TIMER_EN			BIT_0			/* Timer Enable */

/*	PMUA_SEA_IDLE_CFG			0x0014	<var Processor: Osprey> Idle
 *										Configuration Register
 */
/*		Bit(s) PMUA_SEA_IDLE_CFG_RSRV_31_22 reserved */
/* <var Processor: Osprey> Disable MC SW REQ */
#define	PMUA_SEA_IDLE_CFG_SEA_DIS_MC_SW_REQ			BIT_21
/* <var Processor: Osprey> MC Wake Enable */
#define	PMUA_SEA_IDLE_CFG_SEA_MC_WAKE_EN			BIT_20
/* <var Processor: Osprey> L2 Power Switch */
#define	PMUA_SEA_IDLE_CFG_SEA_L2_PWR_SW_MSK			SHIFT18(0x3)
#define	PMUA_SEA_IDLE_CFG_SEA_L2_PWR_SW_BASE		18
/* <var Processor: Osprey> Core Power Switch */
#define	PMUA_SEA_IDLE_CFG_SEA_PWR_SW_MSK			SHIFT16(0x3)
#define	PMUA_SEA_IDLE_CFG_SEA_PWR_SW_BASE			16
/* <var Processor: Osprey> L2 Disable Sleep 2 */
#define	PMUA_SEA_IDLE_CFG_SEA_DIS_L2_SLP2			BIT_15
/* <var Processor: Osprey> L2 Disable Sleep 1 */
#define	PMUA_SEA_IDLE_CFG_SEA_DIS_L2_SLP1			BIT_14
/* <var Processor: Osprey> Disable Sleep 2 */
#define	PMUA_SEA_IDLE_CFG_SEA_DIS_SLP2				BIT_13
/* <var Processor: Osprey> Disable Sleep 1 */
#define	PMUA_SEA_IDLE_CFG_SEA_DIS_SLP1				BIT_12
/* <var Processor: Osprey> Mask JTAG Idle */
#define	PMUA_SEA_IDLE_CFG_SEA_MASK_JTAG_IDLE		BIT_11
/* <var Processor: Osprey> L2 Controller Clock Enable/Disable */
#define	PMUA_SEA_IDLE_CFG_SEA_L2_CLK_DIS			BIT_10
/* <var Processor: Osprey> L2 Controller Reset */
#define	PMUA_SEA_IDLE_CFG_SEA_L2_RESETN				BIT_9
/* <var Processor: Osprey> L2 Isolation Enable */
#define	PMUA_SEA_IDLE_CFG_SEA_L2_ISOB				BIT_8
/* <var Processor: Osprey> L2 Controller SRAM Power Off */
#define	PMUA_SEA_IDLE_CFG_SEA_L2_PWR_OFF			BIT_7
/* <var Processor: Osprey> SRAM Power Down */
#define	PMUA_SEA_IDLE_CFG_SEA_SRAM_PWRDWN			BIT_6
/* <var Processor: Osprey> Power Down */
#define	PMUA_SEA_IDLE_CFG_SEA_PWRDWN				BIT_5
/*		Bit(s) PMUA_SEA_IDLE_CFG_RSRV_4_0 reserved */

/*	PMUA_MOH_IDLE_CFG			0x0018	<var Processor: Mohawk> Idle
 *										Configuration Register
 */
/*		Bit(s) PMUA_MOH_IDLE_CFG_RSRV_31_22 reserved */
/* <var Processor: Mohawk> Disable MC SW REQ */
#define	PMUA_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ			BIT_21
/* <var Processor: Mohawk> MC Wake Enable */
#define	PMUA_MOH_IDLE_CFG_MOH_MC_WAKE_EN			BIT_20
/* <var Processor: Mohawk> L2 Power Switch */
#define	PMUA_MOH_IDLE_CFG_MOH_L2_PWR_SW_MSK			SHIFT18(0x3)
#define	PMUA_MOH_IDLE_CFG_MOH_L2_PWR_SW_BASE		18
/* <var Processor: Mohawk> Core Power Switch */
#define	PMUA_MOH_IDLE_CFG_MOH_PWR_SW_MSK			SHIFT16(0x3)
#define	PMUA_MOH_IDLE_CFG_MOH_PWR_SW_BASE			16
/* <var Processor: Mohawk> L2 Disable Sleep 2 */
#define	PMUA_MOH_IDLE_CFG_MOH_DIS_L2_SLP2			BIT_15
/* <var Processor: Mohawk> L2 Disable Sleep 1 */
#define	PMUA_MOH_IDLE_CFG_MOH_DIS_L2_SLP1			BIT_14
/* <var Processor: Mohawk> Disable Sleep 2 */
#define	PMUA_MOH_IDLE_CFG_MOH_DIS_SLP2				BIT_13
/* <var Processor: Mohawk> Disable Sleep 1 */
#define	PMUA_MOH_IDLE_CFG_MOH_DIS_SLP1				BIT_12
/* <var Processor: Mohawk> Mask JTAG Idle */
#define	PMUA_MOH_IDLE_CFG_MOH_MASK_JTAG_IDLE		BIT_11
/* <var Processor: Mohawk> L2 Clock Enable/Disable */
#define	PMUA_MOH_IDLE_CFG_MOH_L2_CLK_DIS			BIT_10
/* <var Processor: Mohawk> L2 Controller Reset */
#define	PMUA_MOH_IDLE_CFG_MOH_L2_RESETN				BIT_9
/* <var Processor: Mohawk> L2 Controller Isolation Enable */
#define	PMUA_MOH_IDLE_CFG_MOH_L2_ISOB				BIT_8
/* <var Processor: Mohawk> L2 Controller SRAM Power Off */
#define	PMUA_MOH_IDLE_CFG_MOH_L2_PWR_OFF			BIT_7
/* <var Processor: Mohawk> SRAM Power Down */
#define	PMUA_MOH_IDLE_CFG_MOH_SRAM_PWRDWN			BIT_6
/* <var Processor: Mohawk> Power Down */
#define	PMUA_MOH_IDLE_CFG_MOH_PWRDWN				BIT_5
/*		Bit(s) PMUA_MOH_IDLE_CFG_RSRV_4_2 reserved */
/* <var Processor: Mohawk> Idle */
#define	PMUA_MOH_IDLE_CFG_MOH_IDLE					BIT_1
/*		Bit(s) PMUA_MOH_IDLE_CFG_RSRV_0 reserved */

/*	PMUA_SQU_CLK_GATE_CTRL		0x001C	SQU Dynamic Clock Gate Control Register */
/* SQU Dynamic Clock Gate Control */
#define	PMUA_SQU_CLK_GATE_CTRL_SQU_CLK_GATE_CTRL_MSK		SHIFT0(0xffffffff)
#define	PMUA_SQU_CLK_GATE_CTRL_SQU_CLK_GATE_CTRL_BASE		0

/*	PMUA_IRE_CLK_GATE_CTRL		0x0020	IRE Dynamic Clock Gate Control Register */
/*		Bit(s) PMUA_IRE_CLK_GATE_CTRL_RSRV_31_8 reserved */
/* IRE Dynamic Clock Gate Control */
#define	PMUA_IRE_CLK_GATE_CTRL_IRE_CLK_GATE_CTRL_MSK		SHIFT0(0xff)
#define	PMUA_IRE_CLK_GATE_CTRL_IRE_CLK_GATE_CTRL_BASE		0

/*	PMUA_CCIC_CLK_GATE_CTRL		0x0028	CCIC Dynamic Clock Gate Control
 *										Register
 */
/*		Bit(s) PMUA_CCIC_CLK_GATE_CTRL_RSRV_31_16 reserved */
/* CCIC Dynamic Clock Gate Control */
#define	PMUA_CCIC_CLK_GATE_CTRL_CCIC_CLK_GATE_CTRL_MSK		SHIFT0(0xffff)
#define	PMUA_CCIC_CLK_GATE_CTRL_CCIC_CLK_GATE_CTRL_BASE		0

/*	PMUA_FBRC1_CLK_GATE_CTRL	0x002C	Fabric 1 Dynamic Clock Gate Control
 *										Register
 */
/* Fabric 1 Dynamic Clock Gate Control */
#define	PMUA_FBRC1_CLK_GATE_CTRL_FBRC1_CLK_GATE_CTRL_MSK			SHIFT0(0xffffffff)
#define	PMUA_FBRC1_CLK_GATE_CTRL_FBRC1_CLK_GATE_CTRL_BASE			0

/*	PMUA_FBRC2_CLK_GATE_CTRL	0x0030	Fabric 2 Dynamic Clock Gate Control
 *										Register
 */
/* Fabric 2 Dynamic Clock Gate Control */
#define	PMUA_FBRC2_CLK_GATE_CTRL_FBRC2_CLK_GATE_CTRL_MSK		SHIFT0(0xffffffff)
#define	PMUA_FBRC2_CLK_GATE_CTRL_FBRC2_CLK_GATE_CTRL_BASE		0

/*	PMUA_USB_CLK_GATE_CTRL		0x0034	USB Dynamic Clock Gate Control Register */
/*		Bit(s) PMUA_USB_CLK_GATE_CTRL_RSRV_31_16 reserved */
/* USB Dynamic Clock Gate Control */
#define	PMUA_USB_CLK_GATE_CTRL_USB_CLK_GATE_CTRL_MSK		SHIFT0(0xffff)
#define	PMUA_USB_CLK_GATE_CTRL_USB_CLK_GATE_CTRL_BASE		0

/*	PMUA_PMU_CLK_GATE_CTRL		0x0040	PMU Dynamic Clock Gate Control Register */
/*		Bit(s) PMUA_PMU_CLK_GATE_CTRL_RSRV_31_24 reserved */
/* PMU Dynamic Clock Gate Control */
#define	PMUA_PMU_CLK_GATE_CTRL_PMU_CLK_GATE_CTRL_MSK		SHIFT0(0xffffff)
#define	PMUA_PMU_CLK_GATE_CTRL_PMU_CLK_GATE_CTRL_BASE		0

/*	PMUA_IRE_CLK_RES_CTRL		0x0048	IRE Clock/Reset Control Register */
/*		Bit(s) PMUA_IRE_CLK_RES_CTRL_RSRV_31_4 reserved */
/* IRE AXI Clock Enable */
#define	PMUA_IRE_CLK_RES_CTRL_IRE_AXICLK_EN			BIT_3
/*		Bit(s) PMUA_IRE_CLK_RES_CTRL_RSRV_2_1 reserved */
/* IRE AXI Reset */
#define	PMUA_IRE_CLK_RES_CTRL_IRE_AXI_RST			BIT_0

/*	PMUA_LCD_CLK_RES_CTRL		0x004C	LCD Clock/Reset Control Register */
/*		Bit(s) PMUA_LCD_CLK_RES_CTRL_RSRV_31_7 reserved */
/* LCD Controller Clock Select */
#define	PMUA_LCD_CLK_RES_CTRL_LCD_CLK_SEL			BIT_6
/*		Bit(s) PMUA_LCD_CLK_RES_CTRL_RSRV_5 reserved */
/* LCD Peripheral Clock Enable */
#define	PMUA_LCD_CLK_RES_CTRL_LCD_CLK_EN			BIT_4
/* LCD AXI Clock Enable */
#define	PMUA_LCD_CLK_RES_CTRL_LCD_AXICLK_EN			BIT_3
/*		Bit(s) PMUA_LCD_CLK_RES_CTRL_RSRV_2 reserved */
/* LCD Peripheral Reset */
#define	PMUA_LCD_CLK_RES_CTRL_LCD_RST				BIT_1
/* LCD AXI Reset */
#define	PMUA_LCD_CLK_RES_CTRL_LCD_AXI_RST			BIT_0

/*	PMUA_CCIC_CLK_RES_CTRL		0x0050	CCIC Clock/Reset Control Register */
/*		Bit(s) PMUA_CCIC_CLK_RES_CTRL_RSRV_31_15 reserved */
/* CCIC PHY Slow Clock Prescaler */
#define	PMUA_CCIC_CLK_RES_CTRL_CCIC_PHYSLOW_PRER_MSK		SHIFT10(0x1f)
#define	PMUA_CCIC_CLK_RES_CTRL_CCIC_PHYSLOW_PRER_BASE		10
/* CCIC PHY SLOW Clock Enable */
#define	PMUA_CCIC_CLK_RES_CTRL_CCIC_PHYSLOWCLK_EN			BIT_9
/* CCIC PHY Slow Reset */
#define	PMUA_CCIC_CLK_RES_CTRL_CCIC_PHYSLOW_RST				BIT_8
/* CCIC PHY Clock Select */
#define	PMUA_CCIC_CLK_RES_CTRL_CCIC_PHYCLK_SEL				BIT_7
/* CCIC Clock Select */
#define	PMUA_CCIC_CLK_RES_CTRL_CCIC_CLK_SEL					BIT_6
/* CCIC PHY Clock Enable */
#define	PMUA_CCIC_CLK_RES_CTRL_CCIC_PHYCLK_EN				BIT_5
/* CCIC Peripheral Clock Enable */
#define	PMUA_CCIC_CLK_RES_CTRL_CCIC_CLK_EN					BIT_4
/* CCIC AXI Clock Enable */
#define	PMUA_CCIC_CLK_RES_CTRL_CCIC_AXICLK_EN				BIT_3
/* CCIC PHY Reset */
#define	PMUA_CCIC_CLK_RES_CTRL_CCIC_PHY_RST					BIT_2
/* CCIC Peripheral Reset */
#define	PMUA_CCIC_CLK_RES_CTRL_CCIC_RST						BIT_1
/* CCIC AXI Reset */
#define	PMUA_CCIC_CLK_RES_CTRL_CCIC_AXI_RST					BIT_0

/*	PMUA_SDH0_CLK_RES_CTRL		0x0054	SDIO Host 0 Clock/Reset Control
 *										Register
 */
/*		Bit(s) PMUA_SDH0_CLK_RES_CTRL_RSRV_31_7 reserved */
/* SDIO Host 0 Clock Select */
#define	PMUA_SDH0_CLK_RES_CTRL_SDH0_CLK_SEL			BIT_6
/*		Bit(s) PMUA_SDH0_CLK_RES_CTRL_RSRV_5 reserved */
/* SDIO Host 0 Peripheral Clock Enable */
#define	PMUA_SDH0_CLK_RES_CTRL_SDH0_CLK_EN			BIT_4
/* SDIO Host 0 AXI Clock Enable */
#define	PMUA_SDH0_CLK_RES_CTRL_SDH0_AXICLK_EN		BIT_3
/*		Bit(s) PMUA_SDH0_CLK_RES_CTRL_RSRV_2 reserved */
/* SDIO Host 0 Peripheral Reset */
#define	PMUA_SDH0_CLK_RES_CTRL_SDH0_RST				BIT_1
/* SDIO Host 0 AXI Reset */
#define	PMUA_SDH0_CLK_RES_CTRL_SDH0_AXI_RST			BIT_0

/*	PMUA_SDH1_CLK_RES_CTRL		0x0058	SDIO Host 1 Clock/Reset Control
 *										Register
 */
/*		Bit(s) PMUA_SDH1_CLK_RES_CTRL_RSRV_31_7 reserved */
/* SDIO Host 1 Clock Select */
#define	PMUA_SDH1_CLK_RES_CTRL_SDH1_CLK_SEL			BIT_6
/*		Bit(s) PMUA_SDH1_CLK_RES_CTRL_RSRV_5 reserved */
/* SDIO Host 1 Peripheral Clock Enable */
#define	PMUA_SDH1_CLK_RES_CTRL_SDH1_CLK_EN			BIT_4
/* SDIO Host 1 AXI Clock Enable */
#define	PMUA_SDH1_CLK_RES_CTRL_SDH1_AXICLK_EN		BIT_3
/*		Bit(s) PMUA_SDH1_CLK_RES_CTRL_RSRV_2 reserved */
/* SDIO Host 1 Peripheral Reset */
#define	PMUA_SDH1_CLK_RES_CTRL_SDH1_RST				BIT_1
/* SDIO Host 1 AXI Reset */
#define	PMUA_SDH1_CLK_RES_CTRL_SDH1_AXI_RST			BIT_0

/*	PMUA_USB_CLK_RES_CTRL		0x005C	USB Clock/Reset Control Register */
/*		Bit(s) PMUA_USB_CLK_RES_CTRL_RSRV_31_5 reserved */
/* USB SPH AXI Clock Enable */
#define	PMUA_USB_CLK_RES_CTRL_USB_SPH_AXICLK_EN		BIT_4
/* USB AXI Clock Enable */
#define	PMUA_USB_CLK_RES_CTRL_USB_AXICLK_EN			BIT_3
/*		Bit(s) PMUA_USB_CLK_RES_CTRL_RSRV_2 reserved */
/* USB SPH AXI Reset */
#define	PMUA_USB_CLK_RES_CTRL_USB_SPH_AXI_RST		BIT_1
/* USB AXI Reset */
#define	PMUA_USB_CLK_RES_CTRL_USB_AXI_RST			BIT_0

/*	PMUA_NF_CLK_RES_CTRL		0x0060	NAND Flash Clock/Reset Control Register */
/*		Bit(s) PMUA_NF_CLK_RES_CTRL_RSRV_31_9 reserved */
/* NAND Flash ECC Reset */
#define	PMUA_NF_CLK_RES_CTRL_NF_ECC_RES			BIT_8
/* NAND Flash ECC Clock Enable */
#define	PMUA_NF_CLK_RES_CTRL_NF_ECC_CLK_EN		BIT_7
/* NAND Flash Clock Select */
#define	PMUA_NF_CLK_RES_CTRL_NF_CLK_SEL			BIT_6
/*		Bit(s) PMUA_NF_CLK_RES_CTRL_RSRV_5 reserved */
/* NAND Flash Peripheral Clock Enable */
#define	PMUA_NF_CLK_RES_CTRL_NF_CLK_EN			BIT_4
/* NAND Flash AXI Clock Enable */
#define	PMUA_NF_CLK_RES_CTRL_NF_AXICLK_EN		BIT_3
/*		Bit(s) PMUA_NF_CLK_RES_CTRL_RSRV_2 reserved */
/* NAND Flash Peripheral Reset */
#define	PMUA_NF_CLK_RES_CTRL_NF_RST				BIT_1
/* NAND Flash AXI Reset */
#define	PMUA_NF_CLK_RES_CTRL_NF_AXI_RST			BIT_0

/*	PMUA_DMA_CLK_RES_CTRL		0x0064	DMA Clock/Reset Control Register */
/*		Bit(s) PMUA_DMA_CLK_RES_CTRL_RSRV_31_4 reserved */
/* DMA AXI Clock Enable */
#define	PMUA_DMA_CLK_RES_CTRL_DMA_AXICLK_EN			BIT_3
/*		Bit(s) PMUA_DMA_CLK_RES_CTRL_RSRV_2_1 reserved */
/* DMA AXI Reset */
#define	PMUA_DMA_CLK_RES_CTRL_DMA_AXI_RST			BIT_0

/*	PMUA_GEU_CLK_RES_CTRL		0x0068	GEU Clock/Reset Control Register */
/*		Bit(s) PMUA_GEU_CLK_RES_CTRL_RSRV_31_4 reserved */
/* GEU AXI Clock Enable */
#define	PMUA_GEU_CLK_RES_CTRL_GEU_AXICLK_EN			BIT_3
/*		Bit(s) PMUA_GEU_CLK_RES_CTRL_RSRV_2_1 reserved */
/* GEU AXI Reset */
#define	PMUA_GEU_CLK_RES_CTRL_GEU_AXI_RST			BIT_0

/*	PMUA_BUS_CLK_RES_CTRL		0x006C	Bus Clock/Reset Control Register */
/*		Bit(s) PMUA_BUS_CLK_RES_CTRL_RSRV_31_2 reserved */
/* Bus Reset */
#define	PMUA_BUS_CLK_RES_CTRL_BUS_RST				BIT_1
/* Memory Controller Reset */
#define	PMUA_BUS_CLK_RES_CTRL_MC_RST				BIT_0

/*	PMUA_SEA_IMR				0x0070	PMU <var Processor: Osprey> Interrupt
 *										Mask Register
 */
/*		Bit(s) PMUA_SEA_IMR_RSRV_31_2 reserved */
/* Frequency Change done by <var Processor: Mohawk> Interrupt Mask */
#define	PMUA_SEA_IMR_MOH_FC_INTR_MASK				BIT_1
/* Frequency Change done by <var Processor: Osprey> Interrupt Mask */
#define	PMUA_SEA_IMR_SEA_FC_INTR_MASK				BIT_0

/*	PMUA_SEA_IRWC				0x0074	PMU <var Processor: Osprey> Interrupt
 *										READ/WRITE Clear Register
 */
/*		Bit(s) PMUA_SEA_IRWC_RSRV_31_2 reserved */
/* <var Processor: Mohawk> Frequency Change Interrupt Read Clear */
#define	PMUA_SEA_IRWC_MOH_FC_INTR_IRST				BIT_1
/* <var Processor: Osprey> Frequency Change Interrupt Read Clear */
#define	PMUA_SEA_IRWC_SEA_FC_INTR_IRST				BIT_0

/*	PMUA_SEA_ISR				0x0078	PMU <var Processor: Osprey> Interrupt
 *										Status Register
 */
/*		Bit(s) PMUA_SEA_ISR_RSRV_31_2 reserved */
/* <var Processor: Mohawk> Frequency Change Interrupt Status */
#define	PMUA_SEA_ISR_MOH_FC_ISR					BIT_1
/* <var Processor: Osprey> Frequency Change Interrupt Status */
#define	PMUA_SEA_ISR_SEA_FC_ISR					BIT_0

/*	PMUA_SD_ROT_WAKE_CLR		0x007C	SDIO/Rotary Wake Clear Register */
/*		Bit(s) PMUA_SD_ROT_WAKE_CLR_RSRV_31_3 reserved */

/* Vbus Detect */
#define	VBUS_DETECT                             BIT_15
/* Usb ID wakeup */
#define	USB_ID_WK_EN                            BIT_12
/* Usb Vbus valid wakeup */
#define	VBUS_VALID_WK_EN                        BIT_11
/* Usb linestate1 wakeup */
#define	LINEST1_WK_EN                           BIT_10
/* Usb linestate0 wakeup */
#define	LINEST0_WK_EN                           BIT_9
/* Usb linestate wakeup Clear */
#define	USB_LINEST_WK_CLR                       BIT_7
/* SDIO Host 2 Wake Clear */
#define	SDH2_WK_CLR		                        BIT_6
/* Usb VBUS Wake Clear */
#define	USB_VBUS_WK_CLR		                    BIT_4
/* Keypad Wake Clear */
#define	KB_WK_CLR			                    BIT_3
/* SDIO Host 1 Wake Clear */
#define	SDH1_WK_CLR		                        BIT_1
/* SDIO Host 0 Wake Clear */
#define	SDH0_WK_CLR		                        BIT_0

/*	PMUA_PWR_STBL_TIMER			0x0084	Power Stable Timer Register */
/*		Bit(s) PMUA_PWR_STBL_TIMER_RSRV_31_24 reserved */
/* Clock Prescaler */
#define	PMUA_PWR_STBL_TIMER_PWR_CLK_PRE_MSK				SHIFT16(0xff)
#define	PMUA_PWR_STBL_TIMER_PWR_CLK_PRE_BASE			16
/* Power up Stable Timer */
#define	PMUA_PWR_STBL_TIMER_PWR_UP_STBL_TIMER_MSK		SHIFT8(0xff)
#define	PMUA_PWR_STBL_TIMER_PWR_UP_STBL_TIMER_BASE		8
/* Power Down Stable Timer */
#define	PMUA_PWR_STBL_TIMER_PWR_DWN_STBL_TIMER_MSK		SHIFT0(0xff)
#define	PMUA_PWR_STBL_TIMER_PWR_DWN_STBL_TIMER_BASE		0

/*	PMUA_DEBUG					0x0088	PMU Debug Register */

/*	PMUA_SRAM_PWR_DWN			0x008C	Core SRAM Power Down Register */
/* SRAM Power Down */
#define	PMUA_SRAM_PWR_DWN_SRAM_PWRDWN_MSK		SHIFT0(0xffffffff)
#define	PMUA_SRAM_PWR_DWN_SRAM_PWRDWN_BASE		0

/*	PMUA_CORE_STATUS			0x0090	Core Status Register */
/*		Bit(s) PMUA_CORE_STATUS_RSRV_31_4 reserved */
/* <var Processor: Mohawk> <q>core idle mode</q> Indication */
#define	PMUA_CORE_STATUS_MOH_IDLE			BIT_3
/* <var Processor: Mohawk> <q>WFI idle mode</q> Indication */
#define	PMUA_CORE_STATUS_MOH_WFI			BIT_2
/* <var Processor: Osprey><q>core idle mode</q> Indication */
#define	PMUA_CORE_STATUS_SEA_IDLE			BIT_1
/* <var Processor: Osprey><q>WFI idle mode</q> Indication */
#define	PMUA_CORE_STATUS_SEA_WFI			BIT_0

/*	PMUA_RES_FRM_SLP_CLR		0x0094	Resume from Sleep Clear Register */
/*		Bit(s) PMUA_RES_FRM_SLP_CLR_RSRV_31_1 reserved */
/* Clear Resume from Sleep Indication */
#define	PMUA_RES_FRM_SLP_CLR_CLR_RSM_FRM_SLP		BIT_0

/*	PMUA_MOH_IMR				0x0098	PMU <var Processor: Mohawk> Interrupt
 *										Mask Register
 */
/*		Bit(s) PMUA_MOH_IMR_RSRV_31_2 reserved */
/* Frequency Change done by <var Processor: Mohawk> Interrupt Mask */
#define	PMUA_MOH_IMR_MOH_FC_INTR_MASK				BIT_1
/* Frequency Change done by <var Processor: Osprey>Interrupt Mask */
#define	PMUA_MOH_IMR_SEA_FC_INTR_MASK				BIT_0

/*	PMUA_MOH_IRWC				0x009C	PMU <var Processor: Mohawk> Interrupt
 *										READ/WRITE Clear Register
 */
/*		Bit(s) PMUA_MOH_IRWC_RSRV_31_2 reserved */
/* <var Processor: Mohawk> FC Interrupt Read Clear */
#define	PMUA_MOH_IRWC_MOH_FC_INTR_IRST				BIT_1
/* <var Processor: Osprey>FC Interrupt Read Clear */
#define	PMUA_MOH_IRWC_SEA_FC_INTR_IRST				BIT_0

/*	PMUA_MOH_ISR				0x00A0	PMU <var Processor: Mohawk> Interrupt
 *										Status Register
 */
/*		Bit(s) PMUA_MOH_ISR_RSRV_31_2 reserved */
/* <var Processor: Mohawk> Frequency Change Interrupt Status */
#define	PMUA_MOH_ISR_MOH_FC_ISR					BIT_1
/* <var Processor: Osprey> Frequency Change Interrupt Status */
#define	PMUA_MOH_ISR_SEA_FC_ISR					BIT_0

/*	PMUA_DTC_CLK_RES_CTRL		0x00AC	DTC Clock/Reset Control Register */
/*		Bit(s) PMUA_DTC_CLK_RES_CTRL_RSRV_31_4 reserved */
/* DTC AXI Clock Enable */
#define	PMUA_DTC_CLK_RES_CTRL_DTC_AXICLK_EN			BIT_3
/*		Bit(s) PMUA_DTC_CLK_RES_CTRL_RSRV_2_1 reserved */
/* DTC AXI Reset */
#define	PMUA_DTC_CLK_RES_CTRL_DTC_AXI_RST			BIT_0

/*	PMUA_MC_HW_SLP_TYPE			0x00B0	Memory Controller Hardware Sleep Type
 *										Register
 */
/*		Bit(s) PMUA_MC_HW_SLP_TYPE_RSRV_31_3 reserved */
/* Memory Controller Hardware Sleep Type */
#define	PMUA_MC_HW_SLP_TYPE_MC_HW_SLP_TYPE_MSK		SHIFT0(0x7)
#define	PMUA_MC_HW_SLP_TYPE_MC_HW_SLP_TYPE_BASE		0

/*	PMUA_MC_SLP_REQ_MOH			0x00B4	Memory Controller <var Processor:
 *										Mohawk> Sleep Request Register
 */
/*		Bit(s) PMUA_MC_SLP_REQ_MOH_RSRV_31_2 reserved */
/* Memory Controller Low Power Acknowledge */
#define	PMUA_MC_SLP_REQ_MOH_MC_SLP_ACK			BIT_1
/* Memory Controller <var Processor: Mohawk> Sleep Request */
#define	PMUA_MC_SLP_REQ_MOH_MC_SLP_REQ_MOH		BIT_0

/*	PMUA_MC_SLP_REQ_SEA			0x00B8	Memory Controller <var Processor:
 *										Osprey> Sleep Request Register
 */
/*		Bit(s) PMUA_MC_SLP_REQ_SEA_RSRV_31_2 reserved */
/* Memory Controller Low Power Acknowledge */
#define	PMUA_MC_SLP_REQ_SEA_MC_SLP_ACK			BIT_1
/* Memory Controller <var Processor: Osprey> Sleep Request */
#define	PMUA_MC_SLP_REQ_SEA_MC_SLP_REQ_SEA		BIT_0

/*	PMUA_MC_SLP_REQ_MSA			0x00BC	Memory Controller MSA Sleep Request
 *										Register
 */
/*		Bit(s) PMUA_MC_SLP_REQ_MSA_RSRV_31_2 reserved */
/* Memory Controller Low Power Acknowledge */
#define	PMUA_MC_SLP_REQ_MSA_MC_SLP_ACK			BIT_1
/* Memory Controller MSA Sleep Request */
#define	PMUA_MC_SLP_REQ_MSA_MC_SLP_REQ_MSA		BIT_0

/*	PMUA_MC_SW_SLP_TYPE			0x00C0	Memory Controller Software Sleep Type
 *										Register
 */
/*		Bit(s) PMUA_MC_SW_SLP_TYPE_RSRV_31_3 reserved */
/* Software Controlled Sleep Type for Memory Controller */
#define	PMUA_MC_SW_SLP_TYPE_MC_SW_SLP_TYPE_MSK		SHIFT0(0x7)
#define	PMUA_MC_SW_SLP_TYPE_MC_SW_SLP_TYPE_BASE		0

/*	PMUA_PLL_SEL_STATUS			0x00C4	PLL Clock Select Status Register */
/*		Bit(s) PMUA_PLL_SEL_STATUS_RSRV_31_8 reserved */
/* BUS Clock PLL Select */
#define	PMUA_PLL_SEL_STATUS_ACLK_PLL_SEL_MSK		SHIFT6(0x3)
#define	PMUA_PLL_SEL_STATUS_ACLK_PLL_SEL_BASE		6
/* Memory Clock PLL Select */
#define	PMUA_PLL_SEL_STATUS_DCLK_PLL_SEL_MSK		SHIFT4(0x3)
#define	PMUA_PLL_SEL_STATUS_DCLK_PLL_SEL_BASE		4
/* <var Processor: Mohawk> PLL Select */
#define	PMUA_PLL_SEL_STATUS_MOH_PLL_SEL_MSK			SHIFT2(0x3)
#define	PMUA_PLL_SEL_STATUS_MOH_PLL_SEL_BASE		2
/* <var Processor: Osprey> PLL Select */
#define	PMUA_PLL_SEL_STATUS_SEA_PLL_SEL_MSK			SHIFT0(0x3)
#define	PMUA_PLL_SEL_STATUS_SEA_PLL_SEL_BASE		0

/*	PMUA_SYNC_MODE_BYPASS		0x00C8	SYNC MODE BYPASS Register */

/*	PMUA_GC_CLK_RES_CTRL		0x00CC	2D/3D Graphics Controller Clock/Reset
 *										Control Register
 */
/*		Bit(s) PMUA_GC_CLK_RES_CTRL_RSRV_31_7 reserved */
/*		Bit(s) PMUA_GC_CLK_RES_CTRL_RSRV_5 reserved */
/* 2D/3D Graphics Controller Peripheral Clock Enable */
#define	PMUA_GC_CLK_RES_CTRL_GC_CLK_EN				BIT_4
/* 2D/3D Graphics Controller AXI Clock Enable */
#define	PMUA_GC_CLK_RES_CTRL_GC_AXICLK_EN			BIT_3
/*		Bit(s) PMUA_GC_CLK_RES_CTRL_RSRV_2 reserved */
/* 2D/3D Graphics Controller Peripheral Reset 1 */
#define	PMUA_GC_CLK_RES_CTRL_GC_RST1				BIT_1
/* 2D/3D Graphics Controller AXI Reset */
#define	PMUA_GC_CLK_RES_CTRL_GC_AXI_RST				BIT_0

/*	PMUA_GC_PWRDWN				0x00D0	2D/3D Graphics Controller Power Down
 *										Register
 */
/*		Bit(s) PMUA_GC_PWRDWN_RSRV_31_5 reserved */
/* 2D/3D Graphics Controller Isolation Enable */
#define	PMUA_GC_PWRDWN_GC_ISB				BIT_4
/* 2D/3D Graphics Controller 3D Power Up */
#define	PMUA_GC_PWRDWN_GC3D_PWRUP_MSK		SHIFT2(0x3)
#define	PMUA_GC_PWRDWN_GC3D_PWRUP_BASE		2
/* 2D/3D Graphics Controller Power Up */
#define	PMUA_GC_PWRDWN_GC_PWRUP_MSK			SHIFT0(0x3)
#define	PMUA_GC_PWRDWN_GC_PWRUP_BASE		0

/*	PMUA_SMC_CLK_RES_CTRL		0x00D4	SMC Clock/Reset Control Register */
/*		Bit(s) PMUA_SMC_CLK_RES_CTRL_RSRV_31_7 reserved */
/* SMC Peripheral Clock Select */
#define	PMUA_SMC_CLK_RES_CTRL_SMC_CLK_SEL			BIT_6
/*		Bit(s) PMUA_SMC_CLK_RES_CTRL_RSRV_5 reserved */
/* SMC Peripheral Clock Enable */
#define	PMUA_SMC_CLK_RES_CTRL_SMC_CLK_EN			BIT_4
/* SMC AXI Clock Enable */
#define	PMUA_SMC_CLK_RES_CTRL_SMC_AXICLK_EN			BIT_3
/*		Bit(s) PMUA_SMC_CLK_RES_CTRL_RSRV_2 reserved */
/* SMC Peripheral Reset */
#define	PMUA_SMC_CLK_RES_CTRL_SMC_RST				BIT_1
/* SMC AXI Reset */
#define	PMUA_SMC_CLK_RES_CTRL_SMC_AXI_RST			BIT_0



/* -------------------- */

#define COEL_APB_GSM_WB_CHOOSE 0xD4070010
#define COEL_APB_RTU_CLKEN 0xD4070014

/*
 *
 *
 *  EDEN B0 CPMU register definition
 *
 *
 */
#define CPMU_CSWER              0xD02500A8
#define CPMU_CSWCR              0xD02500AC
#define CPMU_CPSR               0xD02500BC
#define CPMU_CPRR               0xD02500C0
#define CPMU_CPCR               0xD02500C4
#define CPMU_CCGR               0xD02500C8
#define CPMU_CWUCRM             0xD02500CC
#define CPMU_CWUCRS             0xD02500D0
#define CPMU_CRSR               0xD02500D4
#define CPMU_MCCR               0xD02500D8
#define CPMU_CUCCR              0xD02500DC



#define NEZHA3_CPMU_STIKY_CLR0                 0xD0250000
#define NEZHA3_CPMU_STIKY_CLR1                 0xD0250004
#define NEZHA3_CPMU_EDGE_OR_LEVEL0             0xD0250008
#define NEZHA3_CPMU_EDGE_OR_LEVEL1             0xD025000C
#define NEZHA3_CPMU_EDGE_OR_LEVEL2             0xD0250010
#define NEZHA3_CPMU_STIKY_CLR2                 0xD0250018
#define NEZHA3_CPMU_DDR_REQ_CTRL_SG            0xD0250020
#define NEZHA3_CPMU_SG_SLEEP_CTRL              0xD0250024
#define NEZHA3_CPMU_MSA_RST                    0xD0250028
#define NEZHA3_CPMU_SG_INT_REG                 0xD025002C
#define NEZHA3_CPMU_CPSS_HW_GATE_CTL_SG        0xD0250034
#define NEZHA3_CPMU_AP_STATUS                  0xD0250038
#define NEZHA3_CPMU_SG_TIMER                   0xD0250048
#define NEZHA3_CPMU_SG_IDLE_CFG                0xD025004C
#define NEZHA3_CPMU_GB_CLK_CTRL                0xD025005C
#define NEZHA3_CPMU_SG_CLK_CTRL                0xD0250060
#define NEZHA3_CPMU_ACLK_CTRL                  0xD0250064
#define NEZHA3_CPMU_CPSS_CLK_GATE_CTRL         0xD0250068
#define NEZHA3_CPMU_CPSS_RST_CTRL              0xD025006C
#define NEZHA3_CPMU_AXISD_HW                   0xD0250070
#define NEZHA3_CPMU_DVC_CP                     0xD0250080
#define NEZHA3_CPMU_DVC_STATUS                 0xD0250088
#define NEZHA3_CPMU_DFC_CP                     0xD0250090
#define NEZHA3_CPMU_DFC_DP                     0xD0250094
#define NEZHA3_CPMU_DFC_STATUS                 0xD0250098
#define NEZHA3_CPMU_DEBUG                      0xD025009C
#define NEZHA3_CPMU_CP_S_GATE_CTRL             0xD02500A0
#define NEZHA3_CPMU_CSWER                      0xD02500A8
#define NEZHA3_CPMU_CSWCR                      0xD02500AC
#define NEZHA3_CPMU_SPH_USB_WK                 0xD02500B0
#define NEZHA3_CPMU_CPSR                       0xD02500BC
#define NEZHA3_CPMU_CPRR                       0xD02500C0
#define NEZHA3_CPMU_CPCR                       0xD02500C4
#define NEZHA3_CPMU_CCGR                       0xD02500C8
#define NEZHA3_CPMU_CWUCRM                     0xD02500CC
#define NEZHA3_CPMU_CWUCRS                     0xD02500D0
#define NEZHA3_CPMU_CRSR                       0xD02500D4
#define NEZHA3_CPMU_CUCCR                      0xD02500DC
#define NEZHA3_CPMU_DMA_INT_MSK                0xD02500E0
#define NEZHA3_CPMU_DMA_INT_STATUS             0xD02500E4
#define NEZHA3_CPMU_DMA_XTC_CTRL               0xD02500E8
#define NEZHA3_CPMU_DYN_CLK_GATE_CTRL          0xD02500F0
#define NEZHA3_CPMU_FABRIC_QOS_CTRL            0xD02500F4
#define NEZHA3_CPMU_DDR_REQ_CTRL_GB            0xD0250100
#define NEZHA3_CPMU_CPSS_HW_GATE_CTRL_GB       0xD0250110
#define NEZHA3_CPMU_CPSS_CLK_GATE_CTRL_GB      0xD0250114
#define NEZHA3_CPMU_CP_S_GATE_CTRL_GB          0xD0250118

//#endif

#endif /* _CPMU_DEF_H */