/*------------------------------------------------------------
(C) Copyright [2006-2008] Marvell International Ltd.
All Rights Reserved
------------------------------------------------------------*/

/************************************************************************/
/*  COPYRIGHT (C) 2002 Intel Corporation.                               */
/*                                                                      */
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/*                                                                      */
/* Title: Communication Subsystem Power Management Unit HW Header File  */
/*                                                                      */
/* Filename: cpmu_hw.h                                                  */
/*                                                                      */
/* Author:   Arik Chikvashvili                                          */
/*                                                                      */
/* Project, Target, subsystem: Tavor, Arbel, HOP     					*/
/*																		*/
/* Remarks: Note that this code controls all of Grayback's registers	*/
/*			eventhough it runs from Arbel !!!							*/
/*			The purpose is to provide with a TEMPORARY tool that will   */
/*			turn all the clocks on.										*/
/*    													                */
/* Created: 8/11/2004                                                   */
/*                                                                      */
/* Modified:                                                            */
/************************************************************************/

#ifndef _CPMU_HW_H_
#define _CPMU_HW_H_

#include "global_types.h"    //  needed for the UINT32 definition.

#define CPMU_BASE_ADDRESS         0xF00E0100L


// Defines the Grayback CCU HW-Structure 
	/** (See GB IAS for special limitaions regarding reserved bits and other remarks) **/
typedef volatile struct 
{
    UINT32      CPCR;	//Communication Subsystem Power Control Register            R/W
    UINT32      CL1CR;	//Communication Subsystem L1 Memory Configuration Register  R/W     N O T E: Does not exists in TAVOR_P products
    UINT32      CL2CR;	//Communication Subsystem L2 Memory Configuration Register  R/W     N O T E: Does not exists in TAVOR_P products
    UINT32      CL2DR;	//Communication Subsystem L2 Memory Detection Register      R/S     N O T E: Does not exists in TAVOR_P products
    UINT32      CL2SR;	//Communication Subsystem L2 Memory Status Register	         R      N O T E: Does not exists in TAVOR_P products
    UINT32      CMCR;	//Communication Subsystem Miscellaneous Counters Register   R/W
    UINT32      CPSR;	//Communication Subsystem Power Status Register             R/W or R
    UINT32      CPR;	//Communication Subsystem PMIC Register                     R/S
    UINT32      CWER;	//Communication Subsystem Wakeup Enable Register            R/W
    UINT32      CGPDR;	//Communication Subsystem General Purpose Detector Register R/W
    UINT32      CWESR;	//Communication Subsystem Wakeup Events Status Register     R/W
    UINT32      CRAR;	//Communication Subsystem Reset Assertion Register          R/W
    UINT32      CIER;	//Communication Subsystem Interrupt Enable Register         R/W
    UINT32      CISR;	//Communication Subsystem Interrupt Status Register         R/W
    UINT32      CGRAR;	//Communication Grayback Core Reset Address Register        R/W
    UINT32      CCRAR;	//Communication Controller Reset Address Register           R/W
    UINT32      CGDES;	//Communication Grayback D2 Entry Status                    R/W
    UINT32      CCDES;	//Communication Controller D2 Entry Status                  R/W
    UINT32      CGDEC;	//Communication Grayback Core D2 Entry Control
    UINT32      CCDEC;	//Communication Controller D2 Entry Control
    UINT32   reserved [(0x200-0x150)/sizeof(UINT32)];  // 0x150...0x1FC reserved
    UINT32      CSSR;	//Communication Subsystem Spare Register                    R/W only half
} CPMU_HW_Registers;

// additional registers 
#define      CPMU_GPBLCSR_REG_ADDR      0xF0260010
#define      CPMU_WRST_WR_REG_ADDR		0xF0240000
#define      CPMU_WRST_RD_REG_ADDR		0xF0240004
#define      CPMU_MCSR_GPB_REG_ADDR     0xF024000C
#define      CPMU_MVT_CTL_REG_ADDR		0xF0203030


#define 	 CISR_FC_IS_MASK  		    0x00000001

//acording to CPCR definitions
#define CPCR_FREQ_52MHZ_MASK        0x000000C0UL   //bits 6,7
#define	CPCR_FREQ_104MHZ_MASK       0x00000300UL   //bits 8,9
#define	CPCR_FREQ_156MHZ_MASK       0x00000C00UL   //bits 10,11
#define	CPCR_FREQ_208MHZ_MASK       0x00003000UL   //bits 12,13
#define	CPCR_FREQ_312MHZ_MASK       0x00030000UL   //bits 16,17

#define CPCR_FREQ_52MHZ_OFFSET		6
#define	CPCR_FREQ_104MHZ_OFFSET	    8
#define	CPCR_FREQ_156MHZ_OFFSET		10
#define	CPCR_FREQ_208MHZ_OFFSET		12
#define	CPCR_FREQ_312MHZ_OFFSET     16

#endif /* _CPMU_HW_H_ */