#ifndef _PIMC_H_ #define _PIMC_H_ #include "quec_cust_feature.h"//QUECTEL ADD #include "I2C.h" /************************** MACROS ***************************************/ void usticaInit(void); #define PMIC_UNAVAILABLE 0xFF //UNAVAILABLE /* PMIC ID: [7:3]=PID, [2:0]=VID */ #define PMIC_812 0xC /* PM812: 0x64 */ #define PMIC_813 0x6 /* PM813: 0x30(A0), 0x31(A1)... */ #define PMIC_813A3 0x7 #define PMIC_813_A0 0x30 #define PMIC_813_A1 0x31 #define PMIC_813_A2 0x32 #define PMIC_813_A3 0x3B #define PMIC_802 0x2 /* PM802: 0x12(B0), 0x13(B1)... */ #define PMIC_803 0x3 /* PM803: 0x18(A0) */ #define PMIC_813S 0x4 /* PM813S: 0x20(A0) */ #define PMIC_813S_A0 0x20 #define PMIC_802S 0x1 /* PM802S: 0x08(A0) */ #define PMIC_803L 0xB /* PM803L: 0x58(A0) */ #define PMIC_813L 0x9 /* PM813L: 0x48(A0) */ #define PMIC_807 0xD /* PM807: 0x68(A0)?? */ // The I2C registers offset #define I2C_IWCR_REG 0x0030 // Wait Count Register #define I2C_ILCR_REG 0x0028 // Load Count Register #define I2C_ISAR_REG 0x0020 // Slave Address Register #define I2C_ISR_REG 0x0018 // Status Register #define I2C_ICR_REG 0x0010 // Control Register #define I2C_IDBR_REG 0x0008 // Data Byte Register #define I2C_IBMR_REG 0x0000 // Bus Monitor Register #define I2C_OWN_SLAVE_ADDRESS 0xFF /* response */ /********************* Sub-Package Definitions ********************/ #define I2C_REG_CLEAR_VALUE 0x0000 #define I2C_ICR_CLEAR_ALL_CONTROL_BITS 0xfff0 // Clear the TB, STOP, START, ACK bits in the ICR register /** bit map of the ICR register **/ #define I2C_ICR_BUS_RESET_BIT 28 #define I2C_ICR_FAST_MODE 15 #define I2C_ICR_UNIT_RESET_BIT 14 #define I2C_ICR_IDBR_RECEIVE_FULL_INT_ENABLE_BIT 9 #define I2C_ICR_UNIT_ENABLE_BIT 6 #define I2C_ICR_SCLEA_ENABLE_BIT 5 #define I2C_ICR_MASTER_ABORT_BIT 4 #define I2C_ICR_TRANSFER_BYTE_BIT 3 #define I2C_ICR_ACK_NACK_CONTROL_BIT 2 #define I2C_ICR_STOP_BIT 1 #define I2C_ICR_START_BIT 0 #define I2C_ICR_BUS_RESET (1 << I2C_ICR_BUS_RESET_BIT) #define I2C_ICR_UNIT_RESET (1 << I2C_ICR_UNIT_RESET_BIT) #define I2C_ICR_IDBR_RECEIVE_FULL_INT_ENABLE (1 << I2C_ICR_IDBR_RECEIVE_FULL_INT_ENABLE_BIT) #define I2C_ICR_UNIT_ENABLE (1 << I2C_ICR_UNIT_ENABLE_BIT) #define I2C_ICR_SCLEA_ENABLE (1 << I2C_ICR_SCLEA_ENABLE_BIT) #define I2C_ICR_MASTER_ABORT (1 << I2C_ICR_MASTER_ABORT_BIT) #define I2C_ICR_TRANSFER_BYTE (1 << I2C_ICR_TRANSFER_BYTE_BIT) #define I2C_ICR_ACK_NACK_CONTROL (1 << I2C_ICR_ACK_NACK_CONTROL_BIT) #define I2C_ICR_STOP (1 << I2C_ICR_STOP_BIT) #define I2C_ICR_START (1 << I2C_ICR_START_BIT) /** bit map of the ISR register **/ #define I2C_ISR_UNEXPECTED_INTERRUPTS_REPORT 0xff #define I2C_ISR_UNEXPECTED_INTERRUPTS 0x00000310 #define I2C_ISR_CLEAR_ALL_INTERRUPTS 0x000007f0 #define I2C_ISR_EARLY_IC_BUS_BUSY_BIT 11 #define I2C_ISR_BUS_ERROR_DETECTED_BIT 10 #define I2C_ISR_SLAVE_ADDRESS_DETECTED_BIT 9 #define I2C_ISR_GENERAL_CALL_ADDRESS_DETECTED_BIT 8 #define I2C_ISR_IDBR_RECEIVE_FULL_BIT 7 #define I2C_ISR_IDBR_TRANSMIT_EMPTY_BIT 6 #define I2C_ISR_ARBITRATION_LOSS_DETECTED_BIT 5 #define I2C_ISR_SLAVE_STOP_DETECTED_BIT 4 #define I2C_ISR_I2C_BUS_BUSY_BIT 3 #define I2C_ISR_UNIT_BUSY_BIT 2 #define I2C_ISR_ACK_NACK_STATUS_BIT 1 #define I2C_ISR_READ_WRITE_MODE_BIT 0 /** bit map of the IBMR register **/ #define I2C_IBMR_SDA_BIT 0 #define I2C_IBMR_SCL_BIT 1 #define I2C_IBMR_SCL_AND_SDA_LINES_HIGH 0x3 #define I2C_IBMR_SDA_STATUS_BIT (1 << I2C_IBMR_SDA_BIT) #define I2C_IBMR_SCL_STATUS_BIT (1 << I2C_IBMR_SCL_BIT) /***************** macros ***********************/ #define I2C_REG_WRITE(reg,wval) \ ( (* ( (volatile UINT32*)(I2C_REGISTER_BASE_ADDR + (reg)) ) ) = wval); #define I2C_REG_READ(reg,rval) \ rval = (* ( (volatile UINT32*)(I2C_REGISTER_BASE_ADDR + (reg)) ) ); #define I2C_REG_BIT_WRITE(reg,btNm,sc) \ { UINT32 regVl; \ I2C_REG_READ(reg,regVl); \ sc ? ( regVl = (1 << btNm) | regVl ) : (regVl = ((regVl) & (~(1 << btNm)))); \ I2C_REG_WRITE(reg,regVl); \ } #define I2C_STATUS_REG_CLEAR_BIT(bitNum) \ { UINT32 regVal; \ regVal = (1 << bitNum); \ I2C_REG_WRITE(I2C_ISR_REG,regVal); \ } #define I2C_REG_BIT_READ(regVl,btNm) ( (regVl >> btNm) & 0x00000001 ) #define I2C_REG_BIT(btNm) (((UINT32)1)<<(btNm)) #define I2C_SLAVE_WRITE(slv) ( (slv) | 0x00000000 ) /* Master is writing to the slave */ #define I2C_SLAVE_READ(slv) ( (slv) | 0x00000001 ) /* Master is reading from the slave */ #define TIME_TO_SAMPLE 15 //MicroSec /*********************** Sub-Package Parameters *************************/ #define CHECK_IF_CHIP_BUSY(st) \ { UINT32 rv; \ I2C_REG_READ(I2C_ISR_REG,rv); \ st = I2C_REG_BIT_READ(rv,I2C_ISR_UNIT_BUSY_BIT) ? TRUE : FALSE; \ } /****** USTICA BASE REGISTER *********/ #define USTICA_ID_REG 0x00 #define USTICA_STATUS_1_REG 0x01 #define USTICA_STATUS_2_REG 0x02 #define USTICA_INT_STATUS_1_REG 0x05 #define USTICA_INT_STATUS_2_REG 0x06 #define USTICA_INT_STATUS_3_REG 0x07 #define USTICA_INT_STATUS_4_REG 0x08 #define USTICA_INT_ENABLE_1_REG 0x09 #define USTICA_INT_ENABLE_2_REG 0x0a #define USTICA_INT_ENABLE_3_REG 0x0b #define USTICA_INT_ENABLE_4_REG 0x0c #define USTICA_WAKEUP_1_REG 0x0d #define USTICA_WAKEUP_2_REG 0x0e #define USTICA_WATCHDOG_REG 0x1d #define USTICA_OSC_CONTROL_1_REG 0x50 #define USTICA_OSC_CONTROL_2_REG 0x51 #define USTICA_OSC_CONTROL_3_REG 0x52 #define USTICA_OSC_CONTROL_4_REG 0x53 #define USTICA_OSC_CONTROL_5_REG 0x54 #define USTICA_OSC_CONTROL_6_REG 0x55 #define USTICA_OSC_CONTROL_7_REG 0x56 #define USTICA_OSC_CONTROL_8_REG 0x57 #define USTICA_OSC_CONTROL_9_REG 0x58 #define USTICA_OSC_CONTROL_10_REG 0x59 #define USTICA_OSC_CONTROL_11_REG 0x5a #define USTICA_OSC_CONTROL_12_REG 0x5b #define USTICA_OSC_CONTROL_13_REG 0x5c #define USTICA_OSC_CONTROL_14_REG 0x5d #define USTICA_RTC_CONTROL_1_REG 0xd0 #define USTICA_RTC_COUNT_1_REG 0xd1 #define USTICA_RTC_COUNT_2_REG 0xd2 #define USTICA_RTC_COUNT_3_REG 0xd3 #define USTICA_RTC_COUNT_4_REG 0xd4 #define USTICA_RTC_EXPIRE1_1_REG 0xd5 #define USTICA_RTC_EXPIRE1_2_REG 0xd6 #define USTICA_RTC_EXPIRE1_3_REG 0xd7 #define USTICA_RTC_EXPIRE1_4_REG 0xd8 #define USTICA_RTC_EXPIRE2_1_REG 0xdd #define USTICA_RTC_EXPIRE2_2_REG 0xde #define USTICA_RTC_EXPIRE2_3_REG 0xdf #define USTICA_RTC_EXPIRE2_4_REG 0xe0 #define USTICA_RTC_MISC_1_REG 0xe1 #define USTICA_RTC_MISC_2_REG 0xe2 #define USTICA_RTC_MISC_3_REG 0xe3 #define USTICA_RTC_MISC_4_REG 0xe4 #define USTICA_RTC_MISC_5_REG 0xe7 #define USTICA_RTC_MISC_6_REG 0xe8 /****** USTICA POWER REGISTER *********/ #define USTICA_BUCK_POWER_GOOD_STATUS_REG 0x01 #define USTICA_LDO_POWER_GOOD_STATUS_1_REG 0x02 #define USTICA_LDO_POWER_GOOD_STATUS_2_REG 0x03 #define USTICA_LDO_POWER_GOOD_STATUS_3_REG 0x04 #define USTICA_LDO_POWER_LAST_GROUP_REG 0x05 ???? #define USTICA_LDO_1_VOUT_1_REG 0x08 #define USTICA_LDO_1_VOUT_2_REG 0x09 #define USTICA_LDO_1_VOUT_3_REG 0x0a #define USTICA_LDO_2_VOUT_REG 0x0b #define USTICA_LDO_3_VOUT_REG 0x0c #define USTICA_LDO_4_VOUT_REG 0x0d #define USTICA_LDO_5_VOUT_REG 0x0e #define USTICA_LDO_6_VOUT_REG 0x0f #define USTICA_LDO_7_VOUT_REG 0x10 #define USTICA_LDO_8_VOUT_REG 0x11 #define USTICA_LDO_9_VOUT_REG 0x12 #define USTICA_LDO_10_VOUT_REG 0x13 #define USTICA_LDO_11_VOUT_REG 0x14 #define USTICA_LDO_12_VOUT_REG 0x15 #define USTICA_LDO_13_VOUT_REG 0x16 #define USTICA_LDO_14_VOUT_REG 0x17 #define USTICA_LDO_15_VOUT_REG 0x18 #define USTICA_LDO_16_VOUT_REG 0x19 #define USTICA_LDO_17_VOUT_REG 0x1a #define USTICA_LDO_18_VOUT_REG 0x1b #define USTICA_LDO_19_VOUT_REG 0x1c #define USTICA_LE_LDO_3_VOUT_REG 0x16 #define USTICA_LE_LDO_2_VOUT_REG 0x0e #define USTICA_VBUCK_1_SET_SLEEP_REG 0x30 #define USTICA_VBUCK_2_SET_SLEEP_REG 0x31 #define USTICA_VBUCK_3_SET_SLEEP_REG 0x32 #define USTICA_VBUCK_4_SET_SLEEP_REG 0x33 #define USTICA_VBUCK_5_SET_SLEEP_REG 0x34 #define USTICA_VAUDIO_MODE_CONFIG_REG 0x38 #define USTICA_VBUCK_1_SET_0_REG 0x3c #define USTICA_VBUCK_1_SET_1_REG 0x3d #define USTICA_VBUCK_1_SET_2_REG 0x3e #define USTICA_VBUCK_1_SET_3_REG 0x3f #define USTICA_VBUCK_2_SET_REG 0x40 #define USTICA_VBUCK_3_SET_REG 0x41 #define USTICA_VBUCK_4_SET_REG 0x42 #define USTICA_VBUCK_5_SET_0_REG 0x43 #define USTICA_VBUCK_5_SET_1_REG 0x44 #define USTICA_VBUCK_5_SET_2_REG 0x45 #define USTICA_VBUCK_5_SET_3_REG 0x46 #define USTICA_BUCK_ENABLE_REG 0x50 #define USTICA_LDO_ENABLE_1_REG 0x51 #define USTICA_LDO_ENABLE_2_REG 0x52 #define USTICA_LDO_ENABLE_3_REG 0x53 #define USTICA_BUCK_ENABLE_2_REG 0x55 #define USTICA_LDO_ENABLE_2_1_REG 0x56 #define USTICA_LDO_ENABLE_2_2_REG 0x57 #define USTICA_LDO_ENABLE_2_3_REG 0x58 #define USTICA_BUCK_SLEEP_MODE_1_REG 0x5a #define USTICA_BUCK_SLEEP_MODE_2_REG 0x5b #define USTICA_LDO_SLEEP_MODE_1_REG 0x5c #define USTICA_LDO_SLEEP_MODE_2_REG 0x5d #define USTICA_LDO_SLEEP_MODE_3_REG 0x5e #define USTICA_LDO_SLEEP_MODE_4_REG 0x5f #define USTICA_LDO_SLEEP_MODE_5_REG 0x60 #define USTICA_BUCK_GROUP_1_REG 0x64 #define USTICA_BUCK_GROUP_2_REG 0x65 #define USTICA_BUCK_GROUP_3_REG 0x66 #define USTICA_LDO_GROUP_1_REG 0x68 #define USTICA_LDO_GROUP_2_REG 0x69 #define USTICA_LDO_GROUP_3_REG 0x6a #define USTICA_LDO_GROUP_4_REG 0x6b #define USTICA_LDO_GROUP_5_REG 0x6c #define USTICA_LDO_GROUP_6_REG 0x6d #define USTICA_LDO_GROUP_7_REG 0x6e #define USTICA_LDO_GROUP_8_REG 0x6f #define USTICA_LDO_GROUP_9_REG 0x70 #define USTICA_LDO_GROUP_10_REG 0x71 #define USTICA_BUCK1_MISC_2_REG 0x79 #define USTICA_BUCK4_MISC_2_REG 0x82 #define USTICA_GPADC_MEAS_ENABLE_1_REG 0x01 #define USTICA_GPADC_MEAS_ENABLE_2_REG 0x02 #define USTICA_GPADC_MISC_CONGIG_2_REG 0x06 #define USTICA_GP_BIAS_ENABLE_1_REG 0x14 #define USTICA_GPADC_MEAS_VBAT_1_REG 0x42 #define USTICA_GPADC_MEAS_VBAT_2_REG 0x43 #define USTICA_GPADC_MEAS_GPADC0_1_REG 0x54 #define USTICA_GPADC_MEAS_GPADC0_2_REG 0x55 #define USTICA_GPADC_MEAS_GPADC2_1_REG 0x58 #define USTICA_GPADC_MEAS_GPADC2_2_REG 0x59 #define USTICA_BUCK5_MISC_1_REG 0x84 #define USTICA_BUCK5_MISC_2_REG 0x85 #define USTICA_BUCK5_MISC_3_REG 0x86 #define GPIO2_CONTROL_REG 0x32 #define PM801_LDO_3_VOUT_REG 0x16 #define PM801_LDO_6_VOUT_REG 0x1C #define PM801_LDO_ENABLE_1_3_REG 0x53 #define PM801_LDO_ENABLE_2_2_REG 0x57 #define PM801_LDO_ENABLE_2_3_REG 0x58 #define PMC_I2C_WRITE_BASE_SLAVE_ADDRESS 0x60 #define PMC_I2C_READ_BASE_SLAVE_ADDRESS 0x61 #define PMC_I2C_WRITE_POWER_SLAVE_ADDRESS 0x62 #define PMC_I2C_READ_POWER_SLAVE_ADDRESS 0x63 #define PMC_I2C_WRITE_GPADC_SLAVE_ADDRESS 0x64 #define PMC_I2C_READ_GPADC_SLAVE_ADDRESS 0x65 #define PMC_I2C_WRITE_TEST_SLAVE_ADDRESS 0x6E #define PMC_I2C_READ_TEST_SLAVE_ADDRESS 0x6F #define PMC_I2C_WRITE_AUDIO_SLAVE_ADDRESS 0x70 #define PMC_I2C_READ_AUDIO_SLAVE_ADDRESS 0x71 #define PM812_BASE_PAGE_WRITE_SLAVE_ADDR 0x60 #define PM812_BASE_PAGE_READ_SLAVE_ADDR 0x61 #define PM812_POWER_PAGE_WRITE_SLAVE_ADDR 0x62 #define PM812_POWER_PAGE_READ_SLAVE_ADDR 0x63 #define PM812_GPADC_PAGE_WRITE_SLAVE_ADDR 0x64 #define PM812_GPADC_PAGE_READ_SLAVE_ADDR 0x65 void ustica_I2CInit(void); void ustica_I2CEnableclockandPin(void); void ustica_I2CConfigureDi( void ); void USTICAI2CWriteDi_base(unsigned char I2CRegAddr, unsigned char I2CRegData); unsigned char USTICAI2CReadDi_base(unsigned char I2CRegAddr); void USTICAI2CWriteDi_power(unsigned char I2CRegAddr, unsigned char I2CRegData); unsigned char USTICAI2CReadDi_power(unsigned char I2CRegAddr); void USTICAI2CWriteDi_GPADC(unsigned char I2CRegAddr, unsigned char I2CRegData); unsigned char USTICAI2CReadDi_GPADC(unsigned char I2CRegAddr); void usticaPMICReadVBatTask(void *u); void ustica_vbuck1_0_set(unsigned long value); void ustica_USB_shutdown(void); void usticaInit(void); unsigned char GetPMICID(void); //************ PM812 ****************** #define PM812_STATUS_1_REG 0x01 #define PM812_ONKEY_STATUS_BIT (0x01<<0) #define PM812_EXTON_STATUS_BIT (0x01<<1) #define PM812_VCHG_STATUS_BIT (0x01<<2) #define PM812_VBAT_STATUS_BIT (0x01<<3) #define PM812_VBUS_STATUS_BIT (0x01<<4) #define PM812_STATUS_2_REG 0x02 #define PM812_RTC_ALARM_STATUS_BIT (0x01<<0) #define PM812_INT_STATUS_1_REG 0x05 #define PM812_INT_STATUS_2_REG 0x06 #define PM812_INT_STATUS_3_REG 0x07 #define PM812_INT_STATUS_4_REG 0x08 #define PM812_INT_ENABLE_REG_1 0x09 #define PM812_INT_ENABLE_REG_2 0x0a #define PM812_INT_ENABLE_REG_3 0x0b #define PM812_INT_ENABLE_REG_4 0x0c #define PM812_WAKEUP_1_REG 0x0d #define PM812_RESET_PMIC_BIT (0x01<<6) #define PM812_PWM_REG1 0x40 #define PM812_PWM_REG4 0x43 #define PM812_WD_MODE_BIT (0x01<<0) #define PM812_WD_RST_BIT (0x01<<4) #define PM812_SW_PDOWN_BIT (0x01<<5) #define PM812_WAKEUP_2_REG 0x0e #define PM812_WD_TIMER_8s (0x3<<3) #define PM812_WD_TIMER_16s (0x4<<3) #define PM812_WD_TIMER_32s (0x5<<3) #define PM812_WD_TIMER_64s (0x6<<3) #define PM812_WD_TIMER_256s (0x7<<3) #define PM812_WD_TIMER_SLP_BITS (0x1<<6|0x1<<7) #define PM812_WD_TIMER_ACT_BITS (0x1<<3|0x1<<4|0x1<<5) #define PM812_WD_ENABLE_REG 0x1d #define PM812_RTC_CONTROL_REG 0xd0 #define PM812_RTC_ALARM_WU_BIT (0x01<<4) #define PM812_RTC_ALARM_BIT (0x01<<5) #define PM812_RTC_USE_XO_BIT (0x01<<7) #define PM812_RTC_ALARM_SET1_BIT (0x01<<0) #define PM812_RTC_ALARM_SET2_BIT (0x01<<1) #define PM812_RTC_COUNT_1_REG 0xd1 #define PM812_RTC_COUNT_2_REG 0xd2 #define PM812_RTC_COUNT_3_REG 0xd3 #define PM812_RTC_COUNT_4_REG 0xd4 #define PM812_RTC_EXPIRE1_1_reg 0xd5 #define PM812_RTC_EXPIRE1_2_reg 0xd6 #define PM812_RTC_EXPIRE1_3_reg 0xd7 #define PM812_RTC_EXPIRE1_4_reg 0xd8 #define PM812_RTC_EXPIRE2_1_reg 0xdd #define PM812_RTC_EXPIRE2_2_reg 0xde #define PM812_RTC_EXPIRE2_3_reg 0xdf #define PM812_RTC_EXPIRE2_4_reg 0xe0 #define PM812_RTC_MISC_3_REG 0xe3 #define PM812_RTC_MISC_4_REG 0xe4 #define PM812_LONGKEY_1 0 #define PM812_LONGKEY_2 1 #define PM812_RTC_LONGKEY1_EN_BIT (0x01<= 17)?PM812_LDO17_TO_LDO19_ENABLE_REG_1:((LDO_X >= 9)?PM812_LDO9_TO_LDO16_ENABLE_REG_1:PM812_LDO1_TO_LDO8_ENABLE_REG_1)) #define PM812_LDO_ENABLE_REG_2(LDO_X) ((LDO_X >= 17)?PM812_LDO17_TO_LDO19_ENABLE_REG_2:((LDO_X >= 9)?PM812_LDO9_TO_LDO16_ENABLE_REG_2:PM812_LDO1_TO_LDO8_ENABLE_REG_2)) #define PM812_LDO_ENABLE_BIT(LDO_X) (0x1 << ((LDO_X - 1)%8)) //=============GPADC PAGE #define PM812_GPADC_MEAS_ENABLE_1_REG 0x01 #define PM812_GPADC_MEAS_ENABLE_2_REG 0x02 #define PM812_GPADC_MISC_CONGIG_2_REG 0x06 #define PM812_GPADC_TIME_2_REG 0x08 #define PM812_GPADC_SW_TRIG_BIT (0x01 << 2) #define PM812_GPADC_NON_STOP (0x01 << 1) /* Enable NON_STOP GPADC operation mode. */ #define PM812_GPADC_GPADC_EN (0x01 << 0) /* Enable the GPADC periodic modes. */ #define PM812_GP_BIAS_ENABLE_1_REG 0x14 #define PM812_VCHG_LOW_TH (0x1a) #define PM812_VCHG_HIGH_TH (0x2a) #define PM812_GPADC_MEAS_VBAT_1_REG 0x42 #define PM812_GPADC_MEAS_VBAT_2_REG 0x43 #define PM812_GPADC_MEAS_VCHG_1_REG 0x46 #define PM812_GPADC_MEAS_VCHG_2_REG 0x47 #define PM812_GPADC_MEAS_GPADC1_1_REG 0x56 #define PM812_GPADC_MEAS_GPADC1_2_REG 0x57 #define PM812_GPADC_BAT_BD_GP3_EN_BIT (0x01<<7) #define PM812_GPADC_BAT_BD_GP1_EN_BIT (0x01<<6) #define PM812_GPADC_BAT_BD_EN_BIT (0x01<<5) #define DIVIDE_5V6_12BIT_MV(meas) (meas*5600/4095) #define DIVIDE_1V4_12BIT_MV(meas) (meas*1400/4095) #define DIVIDE_5V6_MV_12BIT(vol) (vol*4095/5600) #define DIVIDE_1V4_MV_12BIT(vol) (vol*4095/1400) void PM812_bk4clkfll_set_2m(void); void PM812_vbuck3_set_1_25(void); void PM812_vbuck4_set_1_85(void); void PM812_vbuck4_set_2_00(void); void PM812_APT_enable(void); void PM812_BUCK5_Enable(void); static void PM812_LDO_Enable(int ldo_num,BOOL OnOff); static void PM812_LDO_VOUT_CFG(int addr,int act_vol,int slp_vol); void PM812_Ldo_4_set_1_8(void); void PM812_Ldo_4_set_3_0(void); void PM812_Ldo_4_set(BOOL OnOff); void PM812_Ldo_10_set_1_8(void); void PM812_Ldo_10_set_3_0(void); void PM812_Ldo_10_set(BOOL OnOff); void PM812_Ldo_12_set_1_8(void); void PM812_Ldo_12_set_2_8(void); void PM812_Ldo_12_set_3_0(void); void PM812_Ldo_12_set(BOOL OnOff); unsigned int PM812_REG_DUMP(unsigned char page, unsigned char addr);//page must be PM812_BASE_PAGE_READ_SLAVE_ADDR \ PM812_POWER_PAGE_READ_SLAVE_ADDR\ PM812_GPADC_PAGE_READ_SLAVE_ADDR void PM812_Ldo_5_set_3_1(void); void PM812_Ldo_5_set(BOOL OnOff); void PM812_Ldo_6_set_1_8(void); void PM812_Ldo_6_set_2_8(void); void PM812_Ldo_6_set(BOOL OnOff); void PM812_Ldo_8_set_2_8(void); void PM812_Ldo_8_set(BOOL OnOff); void PM812_Ldo_9_set_1_8(void); void PM812_Ldo_9_set(BOOL OnOff); void PM812_Ldo_11_set_2_8(void); void PM812_Ldo_11_set(BOOL OnOff); void PM812_Ldo_13_set_2_8(void); void PM812_Ldo_13_set(BOOL OnOff); void PM812_Ldo_15_set_2_8(void); void PM812_Ldo_15_set(BOOL OnOff); void PM812_Ldo_16_set_2_8(void); void PM812_Ldo_16_set(BOOL OnOff); void PM812_Ldo_17_set_2_8(void); void PM812_Ldo_17_set(BOOL OnOff); void PM812_Ldo_18_set_1_8(void); void PM812_Ldo_18_set(BOOL OnOff); void PM812SetLDO3OffOnSleep(void); void PM812_32K_OUT2_Enable(void); typedef union CNT_32{ UINT8 cnt_8[4]; UINT32 cnt_32; } COUNTER_32; typedef void (*PmicCallback)(void); typedef struct { BOOL pmic_intc_enabled; PmicCallback pmic_isr; }Pmic_Int_Handler; typedef enum { //INT ENABLE REG 4 addr=0x0c PM812_GPIO0_INT=0, PM812_GPIO1_INT, PM812_GPIO2_INT, PM812_GPIO3_INT, PM812_GPIO4_INT, //INT ENABLE REG 3 addr=0x0b PM812_GPADC0_INT=8, PM812_GPADC1_INT, PM812_GPADC2_INT, PM812_GPADC3_INT, PM812_GPADC4_INT, //INT ENABLE REG 2 addr=0x0a PM812_VBAT_INT=16, PM812_VSYS_INT, PM812_VCHG_INT, PM812_TINT_INT, //INT ENABLE REG 1 addr=0x09 PM812_ONKEY_INT =24, PM812_EXTON_INT, PM812_CHG_INT, PM812_BAT_INT, PM812_RTC_INT, PM812_CLASSD_OC_INT } PM812_INTC ; #define PM812_INTC_MAX 31 #define PM812_INTC_TO_STATUS_BIT(intc) (0x01< PM812_VBBAT_MEAS_EN) ? PM812_GPADC_MEAS_ENABLE_1_REG : PM812_GPADC_MEAS_ENABLE_2_REG) #define PM812_MEAS_TO_ENABLE_BIT(meas_en) (0x01<<(meas_en%8)) void PMIC_WRITE_REG_GPADC(UINT8 addr, UINT8 value); UINT8 PMIC_READ_REG_GPADC(UINT8 addr); void PMIC_WRITE_REG_POWER(UINT8 addr, UINT8 value); UINT8 PMIC_READ_REG_POWER(UINT8 addr); void PMIC_WRITE_REG_BASE(UINT8 addr, UINT8 value); UINT8 PMIC_READ_REG_BASE(UINT8 addr); void PMIC_WRITE_REG_TEST(UINT8 addr, UINT8 value); UINT8 PMIC_READ_REG_TEST(UINT8 addr); void PMIC_WRITE_REG_AUDIO(UINT8 addr, UINT8 value); UINT8 PMIC_READ_REG_AUDIO(UINT8 addr); static void PM812_LDO_Enable(int ldo_num,BOOL OnOff); static void PM812_LDO_VOUT_CFG(int addr,int act_vol,int slp_vol); static void PM812_WRITE_REG_BASE(UINT8 addr, UINT8 value); static UINT8 PM812_READ_REG_BASE(UINT8 addr); static UINT32 PM812_GET_RTC_REG_32(UINT8 start); static void PM812_SET_RTC_REG_32(UINT8 start,UINT32 data); static UINT8 PM812_GET_POWER_UP_LOG(void); static void PM812_CLR_POWER_UP_LOG(UINT8 tmp); static UINT8 PM812_GET_POWER_DOWN_LOG(void); static void PM812_CLR_POWER_DOWN_LOG(UINT8 tmp); static UINT8 PM812_GET_POWER_DOWN_LOG2(void); static void PM812_CLR_POWER_DOWN_LOG2(UINT8 tmp); static UINT32 PM812_GET_INT_TO_HOST_ENABLE_REG(void); static UINT32 PM812_GET_INT_TO_HOST_STATUS_REG(void); static void PM812_CLEAR_INT_TO_HOST_STATUS_REG(void); static void PM812_PRE_REG_SNAPSHOT(void); static void PM812_INT_TO_HOST_ENABLE(PM812_INTC intc); static void PM812_INT_TO_HOST_DISABLE(PM812_INTC intc); static void PM812_POWER_UP_ACTIONS(void); void PM812_SW_RESET(void); void PM812_SW_PDOWN(void); void PM812_DUMP_STATE(void); void PM812_SET_WD_TIMEOUT_ACT(UINT8 timeout); void PM812_WD_RESET(void); void PM812_WD_ENABLE(BOOL enable); UINT8 PM812_RTC_GET_CONTROL_REG(void); void PM812_RTC_SET_CONTROL_REG(UINT8 ctl); UINT32 PM812_RTC_GET_32B_COUNTER(void); UINT32 PM812_RTC_GET_32B_OFFSET(void); void PM812_RTC_SET_32B_OFFSET(UINT32 offset); UINT32 PM812_RTC_GET_32B_EXPIR_1(void); UINT32 PM812_RTC_GET_32B_EXPIR_2(void); void PM812_RTC_SET_32B_EXPIR_1(UINT32 expir); void PM812_RTC_SET_32B_EXPIR_2(UINT32 expir); void PM812_RTC_ENABLE_EXPIR_1(void); void PM812_RTC_ENABLE_EXPIR_2(void); void PM812_RTC_DISABLE_EXPIR_1(void); void PM812_RTC_DISABLE_EXPIR_2(void); void PM812_RTC_USE_XO(void); BOOL PM812_IS_ALARM_TRIGGERD_POWERUP(void); BOOL PMIC_ID_GET(void); BOOL PMIC_COMP_ID_GET(void); BOOL PMIC_IS_PM812(void); BOOL PMIC_IS_PM813(void); BOOL PMIC_IS_PM813_A1(void); BOOL PMIC_IS_PM813_A2(void); BOOL PMIC_IS_PM813_A3(void); BOOL PMIC_IS_PM802(void); BOOL PMIC_IS_PM803(void); BOOL PMIC_IS_PM813S(void); BOOL PMIC_IS_PM813S_A0(void); BOOL PMIC_IS_PM802S(void); BOOL PMIC_IS_PM803L(void); BOOL PMIC_IS_PM807(void); BOOL PMIC_IS_PM813L(void); void PMIC_Phase1Init(void); void PMIC_Phase2Init(void); void PMIC_Phase3Init(void); void PM812_INT_DISABLE(PM812_INTC intc); void PM812_INT_ENABLE(PM812_INTC intc); void PM812_INT_CALLBACK_REGISTER(PM812_INTC intc,PmicCallback isr); static void PMIC_HISR_FUNC(void); static void PMIC_LISR_FUNC(UINT32 isr); BOOL PM812_CHARGER_IS_DETECTED(void); BOOL PM812_VBUS_IS_AVAILABLE(void); UINT32 PM812_GET_VCHG_LOW_TH(void); UINT32 PM812_GET_VCHG_UPP_TH(void); void PM812_SET_VCHG_LOW_TH(UINT8 low); void PM812_SET_VCHG_UPP_TH(UINT8 upp); UINT16 PM812_GPADC_READ_VOL_MEAS(UINT8 meaReg); void PM812_BIAS_ENABLE(PM812_BIAS_EN bias_en); void PM812_BIAS_DISABLE(PM812_BIAS_EN bias_en); void PM812_BIAS_OUT_ON(PM812_BIAS_OUT bias_out); void PM812_BIAS_OUT_OFF(PM812_BIAS_OUT bias_out); void PM812_MEAS_ENABLE(PM812_MEAS_EN meas_en); void PM812_MEAS_DISABLE(PM812_MEAS_EN meas_en); void PM812_GPADC_SW_TRIG(void); BOOL PM812_EXTON_IS_DETECTED(void); BOOL PM812_BATTERY_IS_DETECTED(void); void PM812_BD_ENABLE(UINT8 bit); void PM812_BD_DISABLE(UINT8 bit); UINT8 PM812_GET_POWER_UP_REASON(void); UINT8 PM812_GET_POWER_DOWN_REASON(void); UINT8 PM812_GET_POWER_DOWN_REASON2(void); BOOL PM812_ONKEY_IS_DETECTED(void); void PM812_LONKEY_ENABLE_SET(UINT8 LONGKEY_NUM,BOOL enable); void PM812_SET_LONKEY_PRESS_TIME(UINT8 sec); void PM812_VBUCK1_CFG(UINT8 value); //Refer to PMIC_BUCK_T for "value" void PM812_VBUCK2_CFG(UINT8 value); //Refer to PMIC_BUCK_T for "value" void PM812_PwmSetLevel(UINT8 level); //0 for PMIC PWM off, 1 for on. void PM812_SW_PDOWN(void); void PM812_SW_RESET(void); typedef enum { CAM_VDD_1V20 = 0x0, CAM_VDD_1V25, CAM_VDD_1V70, /* PM813 IOVdd suported point */ CAM_VDD_1V80, /* PM813 IOVdd suported point */ CAM_VDD_1V85, CAM_VDD_1V90, /* PM813 IOVdd suported point */ CAM_VDD_2V50, /* PM813 IOVdd suported point */ CAM_VDD_2V60, CAM_VDD_2V70, CAM_VDD_2V75, CAM_VDD_2V80, /* PM813 IOVdd suported point */ CAM_VDD_2V85, CAM_VDD_2V90, /* PM813 IOVdd suported point */ CAM_VDD_3V00, CAM_VDD_3V10, /* PM813 IOVdd suported point */ CAM_VDD_3V30, /* PM813 IOVdd suported point */ CAM_VDD_MAX = CAM_VDD_3V30 }Camera_Pwr_Val ; void Camera_Avdd_Power_set(Camera_Pwr_Val ldoVal); void Camera_Dvdd_Power_set(Camera_Pwr_Val ldoVal); void Camera_IOvdd_Power_set(Camera_Pwr_Val ldoVal); void Camera_IOvdd_Power_off(void); void Camera_Avdd_Power_off(void); #define PMIC_REG_FOR_USR_DEF_FLAGS_STR 0xE8 #define PMIC_REG_FOR_SW_RESTART_REASON_STR 0xE9 #define PM802_REG_FOR_USR_DEF_FLAGS_STR 0xEC #define PM802S_REG_FOR_USR_DEF_FLAGS_STR 0xCF #define PM803L_REG_FOR_USR_DEF_FLAGS_STR 0xCF #define PM807_REG_FOR_USR_DEF_FLAGS_STR 0xCF #if QUECTEL_PROJECT_CUST //QUECTEL ADD FIX 因为CP和 boot测读取pmic 的寄存器地址不统一导致,在cp侧设置C8区域，但是在boot侧读取的却是cf区域 //特地添加的兼容方案,同时写入 C8 CF 这样无论boot读取那一个地址的值都是正常的 #define PM807_REG_FOR_USR_DEF_FLAGS_STR_BACK_UP 0xC8 //DON'T delete #endif typedef enum { RSTREASON_POWEROFF_CHARGE = 'C', //Charging in "powering off" mode RSTREASON_RD_PRODUCTION = 'R', //Rd production mode RSTREASON_RTC_ALARM = 'A', //rtc Alarm RSTREASON_NORMAL_POWERON = 'N', //Normal powering on RSTREASON_ERROR_CONDITION = 'E', //Error reset, eg. watchdog reset triggered by system hang or silent reset RSTREASON_ENTER_DOWNLOAD = 'D', //image Download mode } SW_RESTART_REASON ; void SysRestartReasonSet(SW_RESTART_REASON reason); UINT8 SysRestartReasonGet(void); UINT8 isSysRestartByCharging(void); UINT8 isSysRestartByRdProduction(void); UINT8 isSysRestartByAlarm(void); UINT8 isSysRestartByNormal(void); UINT8 isSysRestartByError(void); void set_calib_production_mode(UINT32 val); void pmic_user_defined_flags_set(UINT8 flag); UINT8 pmic_user_defined_flags_get(void); //fix build warnning UINT32 PM812_RTC_GET_32B_APP_OFFSET(void); UINT32 PM812_RTC_GET_32B_SYS_OFFSET(void); void PM812_RTC_SET_32B_APP_OFFSET(UINT32 offset); UINT32 PM812_RTC_GET_32B_SYS_OFFSET(void); void PM812_RTC_SET_32B_SYS_OFFSET(UINT32 offset); void PM812_RESET_ALL(void); void PM812_GPADC_NONSTOP_TRIG_ENABLE(void); void PM812_GPADC_NONSTOP_TRIG_DISABLE(void); BOOL PM812_LONKEY_ENABLE_GET(UINT8 LONGKEY_NUM); UINT8 PM812_GET_LONKEY_PRESS_TIME(void); BOOL PMIC_ID_GET(void); unsigned char USTICAI2CReadDi_TEST(unsigned char I2CRegAddr); void USTICAI2CWriteDi_TEST(unsigned char I2CRegAddr, unsigned char I2CRegData); void PMIC_PowerDown(void); BOOL PMIC_IS_ALARM_TRIGGERD_POWERUP(void); UINT32 PMIC_readVbat(void); void PM812_FAULT_WU_EN_ENABLE(void); void PM812_FAULT_WU_ENABLE(void); void PlatformRfSwitchPowerConfig(void); void PlatformBuckAptConfig(void); #define PMIC_RTC_SETTING_FILE "PMIC_RTC_SETTING.nvm" #define DEFAULT_TIMEZONE (8) //UTC+8 (Beijing) as default #define TIMEZONE_TO_COUNT(x) ((x)*60*60) #define COUNT_TO_TIMEZONE(y) ((y)/(60*60)) //ICAT EXPORTED STRUCT typedef struct { UINT32 pmic_rtc_setting_sys_offset; UINT32 pmic_rtc_setting_app_offset; INT32 pmic_rtc_setting_timezone; }PMIC_RTC_Setting; typedef enum { PMIC_RTC_SETTING_AVAILABLE = (0x1<<0),//to detect whether PMIC into state POWER_DONE_2, then {PMIC_RTC_SETTING} should be reset APP_OFFSET_EVER_CFGED = (0x1<<1),//to mark app_offset ever configed }PMIC_RTC_FUNC_BIT; typedef enum { PMIC_RTC_OFFSET_NULL, PMIC_RTC_OFFSET_IN_NVM, PMIC_RTC_OFFSET_IN_PMIC_REG, }PMIC_RTC_OFFSET_STORAGE; #ifdef SCS_BUT_WITHOUT_ALARM_IO_PAD void no_alarm_io_rtc_signal_clear(void); void no_alarm_rtc_alarm_enable(BOOL onoff); static void no_alarm_io_PMIC_HISR_FUNC(void); static void no_alarm_io_PMIC_LISR_FUNC(UINT32 isr); #endif//SCS_BUT_WITHOUT_ALARM_IO_PAD BOOL PMIC_RTC_CFG_INIT_FLAG_GET(void); BOOL pmic_userdata_get_app_lcd_ever_configed(void); #endif /* _PIMC_H_ */