/** ****************************************************************************** * @file quec_gpio.h * @author Chavis.Chen * @version V1.0.0 * @date 26-Sep-2018 * @brief This file contains the common definitions, macros and functions to * be shared throughout the project. ****************************************************************************** * * The MIT License * Copyright (c) 2014 QUECTEL Inc. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is furnished * to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR * IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ****************************************************************************** */ /*================================================================ Copyright (c) 2018 Quectel Wireless Solution, Co., Ltd. All Rights Reserved. Quectel Wireless Solution Proprietary and Confidential. =================================================================*/ /*================================================================= EDIT HISTORY FOR MODULE This section contains comments describing changes made to the module. Notice that changes are listed in reverse chronological order. WHEN WHO WHAT, WHERE, WHY ------------ ------- ------------------------------------------------------------------------------- 10/11/2018 Chaim Init version 04/16/2022 Sharon.li 整理不同项目需要配置的引脚 =================================================================*/ #ifndef _QUEC_GPIO_H #define _QUEC_GPIO_H #include "quec_mfpr_api.h" #include "gpio.h" #include "cgpio.h" #include "gpio_config.h" #include "Gpio_Hw.h" #include "cgpio_HW.h" #include "quec_include.h" #ifdef __cplusplus extern "C" { #endif #define GPIO_TOTAL_INTERRUPT_REG (0XD4282000+55*4) //Chaim 2018.11.22 mfpr register edge_clear bit #define QUEC_MFPR_REG_EDGE_CLEAR_SHIFT 6 //chaim 2018.10.24 gpio log enable #define QUEC_GPIO_LOG_ENABLE #ifdef QUEC_CUSTOM_LAST_GASP_FEATURE #define QUEC_LAST_GASP_TRIGGER_GPIO (GPIO_PIN_36) // trigger #endif typedef enum GPIO_PIN_NUMBER_ENUM { GPIO_PIN_NO_NOT_ASSIGNED = -1, GPIO_PIN_NO_0=0,GPIO_PIN_NO_1, GPIO_PIN_NO_2, GPIO_PIN_NO_3, GPIO_PIN_NO_4, GPIO_PIN_NO_5, GPIO_PIN_NO_6, GPIO_PIN_NO_7, GPIO_PIN_NO_8, GPIO_PIN_NO_9, GPIO_PIN_NO_10, GPIO_PIN_NO_11, GPIO_PIN_NO_12, GPIO_PIN_NO_13, GPIO_PIN_NO_14, GPIO_PIN_NO_15, GPIO_PIN_NO_16, GPIO_PIN_NO_17, GPIO_PIN_NO_18, GPIO_PIN_NO_19, GPIO_PIN_NO_20, GPIO_PIN_NO_21, GPIO_PIN_NO_22, GPIO_PIN_NO_23, GPIO_PIN_NO_24, GPIO_PIN_NO_25, GPIO_PIN_NO_26, GPIO_PIN_NO_27, GPIO_PIN_NO_28, GPIO_PIN_NO_29, GPIO_PIN_NO_30, GPIO_PIN_NO_31, GPIO_PIN_NO_32, GPIO_PIN_NO_33, GPIO_PIN_NO_34, GPIO_PIN_NO_35, GPIO_PIN_NO_36, GPIO_PIN_NO_37, GPIO_PIN_NO_38, GPIO_PIN_NO_39, GPIO_PIN_NO_40, GPIO_PIN_NO_41, GPIO_PIN_NO_42, GPIO_PIN_NO_43, GPIO_PIN_NO_44, GPIO_PIN_NO_45, GPIO_PIN_NO_46, GPIO_PIN_NO_47, GPIO_PIN_NO_48, GPIO_PIN_NO_49, GPIO_PIN_NO_50, GPIO_PIN_NO_51, GPIO_PIN_NO_52, GPIO_PIN_NO_53, GPIO_PIN_NO_54, GPIO_PIN_NO_55, GPIO_PIN_NO_56, GPIO_PIN_NO_57, GPIO_PIN_NO_58, GPIO_PIN_NO_59, GPIO_PIN_NO_60, GPIO_PIN_NO_61, GPIO_PIN_NO_62, GPIO_PIN_NO_63, GPIO_PIN_NO_64, GPIO_PIN_NO_65, GPIO_PIN_NO_66, GPIO_PIN_NO_67, GPIO_PIN_NO_68, GPIO_PIN_NO_69, GPIO_PIN_NO_70, GPIO_PIN_NO_71, GPIO_PIN_NO_72, GPIO_PIN_NO_73, GPIO_PIN_NO_74, GPIO_PIN_NO_75, GPIO_PIN_NO_76, GPIO_PIN_NO_77, GPIO_PIN_NO_78, GPIO_PIN_NO_79, GPIO_PIN_NO_80, GPIO_PIN_NO_81, GPIO_PIN_NO_82, GPIO_PIN_NO_83, GPIO_PIN_NO_84, GPIO_PIN_NO_85, GPIO_PIN_NO_86, GPIO_PIN_NO_87, GPIO_PIN_NO_88, GPIO_PIN_NO_89, GPIO_PIN_NO_90, GPIO_PIN_NO_91, GPIO_PIN_NO_92, GPIO_PIN_NO_93, GPIO_PIN_NO_94, GPIO_PIN_NO_95, GPIO_PIN_NO_96, GPIO_PIN_NO_97, GPIO_PIN_NO_98, GPIO_PIN_NO_99, GPIO_PIN_NO_100, GPIO_PIN_NO_101, GPIO_PIN_NO_102, GPIO_PIN_NO_103, GPIO_PIN_NO_104, GPIO_PIN_NO_105, GPIO_PIN_NO_106, GPIO_PIN_NO_107, GPIO_PIN_NO_108, GPIO_PIN_NO_109, GPIO_PIN_NO_110, GPIO_PIN_NO_111, GPIO_PIN_NO_112, GPIO_PIN_NO_113, GPIO_PIN_NO_114, GPIO_PIN_NO_115, GPIO_PIN_NO_116, GPIO_PIN_NO_117, GPIO_PIN_NO_118, GPIO_PIN_NO_119, GPIO_PIN_NO_120, GPIO_PIN_NO_121, GPIO_PIN_NO_122, GPIO_PIN_NO_123, GPIO_PIN_NO_124, GPIO_PIN_NO_125, GPIO_PIN_NO_126, GPIO_PIN_NO_127, GPIO_PIN_NO_MAX, }GPIO_PIN_NUMBER_E; typedef enum PIN_DIRECTION_ENUM { PIN_DIRECTION_IN = 0, PIN_DIRECTION_OUT, }PIN_DIRECTION_E; typedef enum PIN_LEVEL_ENUM { PIN_LEVEL_LOW = 0, PIN_LEVEL_HIGH, }PIN_LEVEL_E; typedef enum PIN_PULL_ENUM { PIN_PULL_DISABLE = 0, PIN_PULL_PU, PIN_PULL_PD, }PIN_PULL_E; typedef enum PIN_EDGE_ENUM { PIN_NO_EDGE = 0, PIN_RISING_EDGE, PIN_FALLING_EDGE, PIN_BOTH_EDGE, }PIN_EDGE_E; typedef enum PIN_DRIVE_LEVEL_ENUM { GPIO_DRV_LEVEL_VERY_SLOW = 0, GPIO_DRV_LEVEL_SLOW, GPIO_DRV_LEVEL_MED, GPIO_DRV_LEVEL_FAST }QL_PIN_DRIVE_LEVEL_E; typedef enum QL_LDO_VOL_ENUM { QL_LDO_1_8V, QL_LDO_2_8V, }QL_LDO_VOL_E; typedef struct quec_gpio_cfg_struct { GPIO_PIN_NUMBER_E gpio_pin_num; PIN_DIRECTION_E pin_dir; PIN_EDGE_E pin_edge; PIN_PULL_E pin_pull; PIN_LEVEL_E pin_level; }quec_gpio_cfg_t; typedef enum QL_PIMC_GPIO_ENUM{ PMIC_GPIO_PIN_209, PMIC_GPIO_PIN_210, PMIC_GPIO_PIN_217, }QL_PIMC_GPIO_E; typedef enum QL_USIM2_IO_ENUM{ USIM2_IO_VOL_1_8V, USIM2_IO_VOL_3_3V, }QL_USIM2_IO_E; #if QUEC_AT_QGPIOEXT_SUPPORT typedef enum quec_gpio_function { GPIO_FUNC_NONE = 0, //default function GPIO_FUNC_PA_CTL = 1, //support for PA control GPIO_FUNC_OPTIONAL = 2, //for further using GPIO_FUNC_MAX = 3 //the max function num }quec_gpio_func_t; #endif typedef enum { QUEC_GPIO_DISABLED = QUEC_DISABLE, QUEC_GPIO_ENABLED = QUEC_ENABLE } quec_gpio_state; typedef enum { QUEC_GPIO_DRV_LEVEL_VERY_SLOW = 0, //DRV_VERY_SLOW_C QUEC_GPIO_DRV_LEVEL_SLOW , //DRV_SLOW_C QUEC_GPIO_DRV_LEVEL_MED, //DRV_MED_C QUEC_GPIO_DRV_LEVEL_FAST //DRV_FAST_C } quec_gpio_drv_level; typedef enum { QUEC_PIN_LEVEL_LOW=0, QUEC_PIN_LEVEL_HIGH }quec_pin_level_value_e; #define QUEC_GENUS_DEBOUNCE_INTERVAL_MS 200 #define QUEC_GENUS_DEBOUNCE_INTERVAL_COUNT 5 #ifdef QUEC_SLEEP_AP_READY #define QUEC_GPIO_APREADY_DEBOUNCE_INTERVAL_MS 10 #define QUEC_GPIO_APREADY_DEBOUNCE_INTERVAL_COUNT 2 #endif #define QUEC_GPIO_DEBOUNCE_INTERVAL_MS 10 #define QUEC_GPIO_DEBOUNCE_INTERVAL_COUNT 2 #ifndef QUEC_AIR_PLANE_CTRL_ENABLE #ifdef QUEC_SLEEP_AP_READY #define QUEC_DEBOUNCE_GPIO_NUM 4 #else #define QUEC_DEBOUNCE_GPIO_NUM 3 #endif #else #ifdef QUEC_SLEEP_AP_READY #define QUEC_DEBOUNCE_GPIO_NUM 5 #else #define QUEC_DEBOUNCE_GPIO_NUM 4 #endif #endif typedef enum { USIM_DEBOUNCE =0, DTR_DEBOUNCE, CTS_DEBOUNCE, AIR_PLAN_DEBOUNCE, #ifdef QUEC_SLEEP_AP_READY APREADY_DEBOUNCE, #endif MAX_DEBOUNCE }quec_pin_debounce_e; #define QUEC_DEBOUNCE_TIME_OUT_MIN 5 #define QUEC_DEBOUNCE_TIME_OUT_MAX 65535 #define QUEC_DEBOUNCE_COUNT_MIN 0 #define QUEC_DEBOUNCE_COUNT_MAX 255 #ifdef QUEC_SLEEP_AP_READY #define APREADY_DISABLE_FLAG 0 #define APREADY_ENABLE_FLAG 1 #define APREADY_LEVEL_LOW_ACTION 3 #define APREADY_LEVEL_HIGH_ACTION 4 #endif typedef struct { uint16 time_out; uint16 count; }quec_debounce_param_s; typedef struct { quec_pin_debounce_e pin_usage; quec_debounce_param_s debounce_param; }quec_gpio_debounce_param_s; typedef struct { GPIO_PinConfiguration config; unsigned long mfprReg_data; void (*GPIOCallback)(void); }quec_pin_config_s; extern GPIO_PinConfiguration gpio_output_dvl; #ifdef QUEC_AIR_PLANE_CTRL_ENABLE extern OS_HISR air_plane_pin_hisr; #endif extern uint8 g_inter_log; #define interrupt_log(msg,...) if(TRUE == g_inter_log) \ { \ custom_log("DEBOUNCE",msg,##__VA_ARGS__); \ } \ extern int quec_gpio_init(GPIO_PIN_NUMBER_E gpio_num, PIN_DIRECTION_E pin_dir, PIN_PULL_E pin_pull, PIN_LEVEL_E pin_level); extern int quec_gpio_deinit(GPIO_PIN_NUMBER_E gpio_num); extern int quec_gpio_set_level(GPIO_PIN_NUMBER_E gpio_num, PIN_LEVEL_E pin_level); extern int quec_gpio_get_level(GPIO_PIN_NUMBER_E gpio_num, PIN_LEVEL_E *p_pin_level); extern int quec_gpio_set_direction(GPIO_PIN_NUMBER_E gpio_num, PIN_DIRECTION_E pin_dir); extern int quec_gpio_get_direction(GPIO_PIN_NUMBER_E gpio_num, PIN_DIRECTION_E *p_pin_dir); extern int quec_gpio_set_pull(GPIO_PIN_NUMBER_E gpio_num, PIN_PULL_E pin_pull); extern int quec_gpio_get_pull(GPIO_PIN_NUMBER_E gpio_num, PIN_PULL_E *p_pin_pull); extern int quec_pin_set_func(GPIO_PIN_NUMBER_E gpio_num, unsigned char func_sel); extern int quec_gpio_set_drive_level(GPIO_PIN_NUMBER_E gpio_num, QL_PIN_DRIVE_LEVEL_E drive_level); extern int quec_gpio_get_drive_level(GPIO_PIN_NUMBER_E gpio_num, QL_PIN_DRIVE_LEVEL_E *drive_level); extern int quec_eint_register(GPIO_PIN_NUMBER_E gpio_num, PIN_EDGE_E pin_edge, PIN_PULL_E pin_pull, void *eint_cb, void *wakeup_eint_cb); extern int quec_eint_unregister(GPIO_PIN_NUMBER_E gpio_num); extern int quec_eint_enable(GPIO_PIN_NUMBER_E gpio_num, PIN_EDGE_E pin_edge); extern int quec_eint_disable(GPIO_PIN_NUMBER_E gpio_num); extern int quec_eint_enable_wakeup(GPIO_PIN_NUMBER_E gpio_num, PIN_EDGE_E pin_edge); extern int quec_eint_disable_wakeup(GPIO_PIN_NUMBER_E gpio_num); extern int quec_set_pmic_gpio_level(QL_PIMC_GPIO_E PINx,unsigned char level); extern void quec_active_gpio_hisr(unsigned int gpio_num); extern int quec_set_usim2_io_vol(char onoff, QL_USIM2_IO_E vol); extern int quec_gpio_map_clock(GPIO_PIN_NUMBER_E gpio_num); extern int quec_set_gpio_mfprReg(GPIO_PIN_NUMBER_E pin_num,unsigned long mfprReg_data ); extern QuecOSStatus quec_gpio_get_mfprReg(GPIO_PinNumbers pin_num, unsigned long *p_mfprReg_data); extern int quec_get_lcc_index(int lcc_num); extern QuecOSStatus quec_reconfig_gpio(int llc_num, int pin_num); extern QuecOSStatus quec_debounce_timer_read(void); extern QuecOSStatus quec_debounce_timer_get(quec_gpio_debounce_param_s *p_debounce); extern QuecOSStatus quec_debounce_timer_set(quec_gpio_debounce_param_s *p_debounce); extern QuecOSStatus quec_write_usim_presence_sclk_cfg(uint8 set_value); extern uint8 quec_get_usim_presence_sclk_cfg(void); extern QuecOSStatus quec_gpio_cust_config(void); //destin 2020.09.24 add for "AT+QCFG="csqgpiodisp" #ifdef QUEC_CSQ_GPIO_DISPLAY_ENABLE extern QuecOSStatus quec_csq_gpio_display_deinit(void); extern void quec_csq_gpio_display_state(void); #endif #if QUEC_QSLEEP_IND_CTL extern void quec_sleep_ind_light(void); extern void quec_sleep_ind_dark(void); #endif #ifdef QUEC_SLEEP_AP_READY void quec_apready_init(void); #endif //特殊功能引脚配置唤醒中断 int quec_sfp_eint_register(GPIO_PIN_NUMBER_E gpio_num, void *wakeup_eint_cb); int quec_sfp_eint_unregister(GPIO_PIN_NUMBER_E gpio_num); int quec_peripherals_pin_not_config(GPIO_PIN_NUMBER_E pin_num); #if defined(QUEC_DUAL_SINGLE_PS_SUPPORT) extern void quec_simslotswitch_init(void); #if defined (__QUECTEL_PROJECT_EG600AKCN_90LC__) || defined (__QUECTEL_PROJECT_EG600AKCN_91LC__) #define QUEC_USIM2_RST_PIN_AF (MFP_AF3) //USIM_RST--SIM2 #define QUEC_USIM2_RST_PIN (GPIO_PIN_55) //USIM_RST--SIM2 #define QUEC_USIM2_CLK_PIN_AF (MFP_AF2) //USIM_CLK--SIM2 #define QUEC_USIM2_CLK_PIN (GPIO_PIN_73) //USIM_CLK--SIM2 #define QUEC_USIM2_DAT_PIN_AF (MFP_AF2) //USIM_DATA--SIM2 #define QUEC_USIM2_DAT_PIN (GPIO_PIN_74) //USIM_DATA--SIM2 #elif defined (__QUECTEL_PROJECT_EG800AKCN_91LC__) || defined (__QUECTEL_PROJECT_EG800AKCN_90LC__)|| defined (__QUECTEL_PROJECT_EG800AKCN_11LG__) #define QUEC_USIM2_RST_PIN_AF (MFP_AF3) //USIM_RST--SIM2 #define QUEC_USIM2_RST_PIN (GPIO_PIN_55) //USIM_RST--SIM2 #define QUEC_USIM2_CLK_PIN_AF (MFP_AF2) //USIM_CLK--SIM2 #define QUEC_USIM2_CLK_PIN (GPIO_PIN_73) //USIM_CLK--SIM2 #define QUEC_USIM2_DAT_PIN_AF (MFP_AF2) //USIM_DATA--SIM2 #define QUEC_USIM2_DAT_PIN (GPIO_PIN_74) //USIM_DATA--SIM2 #elif defined (__QUECTEL_PROJECT_EG800WCN_11LG__) #define QUEC_USIM2_RST_PIN_AF (MFP_AF7) //USIM_RST--SIM2 #define QUEC_USIM2_RST_PIN (GPIO_PIN_57) //USIM_RST--SIM2 #define QUEC_USIM2_CLK_PIN_AF (MFP_AF7) //USIM_CLK--SIM2 #define QUEC_USIM2_CLK_PIN (GPIO_PIN_73) //USIM_CLK--SIM2 #define QUEC_USIM2_DAT_PIN_AF (MFP_AF7) //USIM_DATA--SIM2 #define QUEC_USIM2_DAT_PIN (GPIO_PIN_74) //USIM_DATA--SIM2 #else //1605/1607外,使用默认值解决编译问题，实际并不使用 #define QUEC_USIM2_RST_PIN_AF (MFP_AF3) //USIM_RST--SIM2 #define QUEC_USIM2_RST_PIN (GPIO_PIN_55) //USIM_RST--SIM2 #define QUEC_USIM2_CLK_PIN_AF (MFP_AF2) //USIM_CLK--SIM2 #define QUEC_USIM2_CLK_PIN (GPIO_PIN_73) //USIM_CLK--SIM2 #define QUEC_USIM2_DAT_PIN_AF (MFP_AF2) //USIM_DATA--SIM2 #define QUEC_USIM2_DAT_PIN (GPIO_PIN_74) //USIM_DATA--SIM2 #endif #endif #ifdef __cplusplus } /*"C" */ #endif #endif