/****************************************************************************** * * (C)Copyright 2005 - 2011 Marvell. All Rights Reserved. * * THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MARVELL. * The copyright notice above does not evidence any actual or intended * publication of such source code. * This Module contains Proprietary Information of Marvell and should be * treated as Confidential. * The information in this file is provided for the exclusive use of the * licensees of Marvell. * Such users have the right to use, modify, and incorporate this code into * products for purposes authorized by the license agreement provided they * include this notice and the associated copyright notice with any such * product. * The information in this file is provided "AS IS" without warranty. ****************************************************************************** ** ** FILENAME: PlatformConfig.h ** ** PURPOSE: Platform specific header to set parameters ** ** ******************************************************************************/ #ifndef __platform_config_h #define __platform_config_h #include "common.h" #include "cpu.h" #include "guilin.h" #define QUEC_INSTRUCTION_MODE 1 #define QUECTEL_PROJECT_CUST #define __REG(x) (*((volatile unsigned int *)(x))) //some simple defines to clean up code a touch #define reg_read(reg) *(volatile unsigned int *)(reg) #define reg_write(reg, val) *(volatile unsigned int *)reg = val; *(volatile unsigned int *)reg; #define reg_bit_set(reg, val) *(volatile unsigned int *)reg |= val; *(volatile unsigned int *)reg; #define reg_bit_clr(reg, val) *(volatile unsigned int *)reg &= ~val; *(volatile unsigned int *)reg; /* * * THE BASE ADDRESSES * */ #define GPIO0_BASE 0xD4019000 #define GPIO1_BASE 0xD4019004 #define GPIO2_BASE 0xD4019008 #define GPIO3_BASE 0xD4019100 /* * * THE REGISTER DEFINES * */ #define GPIO_PLR (0x0000) /* 32 bit GPIO Pin-Level Register */ #define GPIO_PDR (0x000C) /* 32 bit GPIO Pin Direction Register */ #define GPIO_PSR (0x0018) /* 32 bit GPIO Pin Output Set Register */ #define GPIO_PCR (0x0024) /* 32 bit GPIO Pin Output Clear * Register */ #define GPIO_RER (0x0030) /* 32 bit GPIO Rising-Edge Detect * Enable Register */ #define GPIO_FERX (0x003C) /* 32 bit GPIO Falling-Edge Detect * Enable Register */ #define GPIO_EDR (0x0048) /* 32 bit GPIO Edge Detect Status * Register */ #define GPIO_SDR (0x0054) /* 32 bit Bit-wise Set of GPIO * Direction Register */ #define GPIO_CDR (0x0060) /* 32 bit Bit-wise Clear of GPIO * Direction Register */ #define GPIO_SRERX (0x006c) /* 32 bit Bit-wise Set of GPIO Rising * Edge Detect Enable * Register */ #define GPIO_CRERX (0x0078) /* 32 bit Bit-wise Clear of GPIO * Rising Edge Detect Enable * Register */ #define GPIO_SFER (0x0084) /* 32 bit Bit-wise Set of GPIO * Falling Edge Detect * Enable Register */ #define GPIO_CFER (0x0090) /* 32 bit Bit-wise Clear of GPIO * Falling Edge Detect * Enable Register */ #define APMASK (0x009c) /* 32 bit AP Bit-wise Mask of GPIO * Edge Detect Register */ #define CPMASK (0x00a8) /* 32 bit CP Bit-wise Mask of GPIO * Edge Detect Register */ #define APPS_PAD_BASE 0xd401e000 #define NET_MODE_GPIO (2) #define SLEEP_IND_GPIO (5) #define NET_STATUS_GPIO (6) #define OFFSET_NET_MODE_GPIO (0x0E4) #define OFFSET_SLEEP_IND_GPIO (0x0F0) #define OFFSET_NET_STATUS_GPIO (0x0F4) #define CP_UART_BASE 0xd4017000 //const int quec_gpio_map_pin_table_size = sizeof(quec_gpio_map_pin_table)/sizeof(quec_gpio_map_pin_s); #define SerialDATA __REG(CP_UART_BASE+0x00) /* Receive Buffer Register (read only) */ #define SerialFIFO __REG(CP_UART_BASE+0x08) /* FIFO Control Register (write only) */ #define SerialLCR __REG(CP_UART_BASE+0x0c) /* Line Control Register (read/write) */ #define SerialMCR __REG(CP_UART_BASE+0x10) /* Modem Control Register (read/write) */ #define SerialLSR __REG(CP_UART_BASE+0x14) /* Line Status Register (read only) */ #define SerialMSR __REG(CP_UART_BASE+0x18) /* Modem Status Register (read only) */ #define SerialSCR __REG(CP_UART_BASE+0x1c) /* Scratchpad Register*/ #define SerialIER __REG(CP_UART_BASE+0x04) /* Interrupt Enable Register (read/write) */ #define SerialABR __REG(CP_UART_BASE+0x28) #define GPIO_MFPR_BASE1 0xD401E0DC #define GPIO_MFPR_BASE2 0xD401E1A0 #define GPIO_MFPR_BASE3 0xD401E304 #define GPIO_MFPR_BASE4 0xD401E1B8 #ifdef QUECTEL_PROJECT_CUST //Chaim 20191113 base addr is error,fixd it #define GPIO_MFPR_BASE5 0xD401E1E0 #else #define GPIO_MFPR_BASE5 0xD401E1F0 #endif #define GPIO_MFPR_BASE6 0xD401E0D0 #define GPIO_MFPR_BASE7 0xD401E2EC #define GPIO_MFPR_BASE8 0xD401E2E4 #define GPIO_MFPR_BASE9 0xD401E2BC #define GPIO_MFPR_BASE10 0xD401E32C #define INVALID_GPIO_MFPR_ADDR 0xFFFFFFFF #ifdef QUECTEL_PROJECT_CUST #define GPIO_MFPR_BASE11 0xD401E0C8 #define GPIO_MFPR_ADDR(n) ( n <= 36 ? GPIO_MFPR_BASE1 + (n << 2): \ ((n <= 54) &&(n >=49)) ? GPIO_MFPR_BASE2 + ((n-49) << 2): \ ((n <= 66)&&(n >=60) ) ? GPIO_MFPR_BASE3 + ((n-60) << 2): \ ((n <= 78)&&(n>=71)) ? GPIO_MFPR_BASE4 + ((n-71)<<2): \ ((n <= 86)&&(n>=81) ) ? GPIO_MFPR_BASE5 + ((n-81) << 2): \ (n == 124)? GPIO_MFPR_BASE6 : \ (n == 122)? GPIO_MFPR_BASE11 : \ (n == 48 )? GPIO_MFPR_BASE7 : \ (n == 121 )? GPIO_MFPR_BASE10 : \ ((n <= 80)&&(n >=79)) ? GPIO_MFPR_BASE8 + ((n-79)<<2) : \ ((n <= 70)&&(n >=69)) ? GPIO_MFPR_BASE9 + ((n-69)<<2) :INVALID_GPIO_MFPR_ADDR) #else #define GPIO_MFPR_ADDR(n) ( n <= 36 ? GPIO_MFPR_BASE1 + (n << 2): \ ((n <= 54) &&(n >=49)) ? GPIO_MFPR_BASE2 + ((n-49) << 2): \ ((n <= 66)&&(n >=60) ) ? GPIO_MFPR_BASE3 + ((n-60) << 2): \ ((n <= 78)&&(n>=71)) ? GPIO_MFPR_BASE4 + ((n-71)<<2): \ ((n <= 86)&&(n>=81) ) ? GPIO_MFPR_BASE5 + ((n-81) << 2): \ ((n == 124)|| (n == 122))? GPIO_MFPR_BASE6 : \ (n == 48 )? GPIO_MFPR_BASE7 : \ (n == 121 )? GPIO_MFPR_BASE10 : \ ((n <= 80)&&(n >=79)) ? GPIO_MFPR_BASE8 + ((n-79)<<2) : \ ((n <= 70)&&(n >=69)) ? GPIO_MFPR_BASE9 + ((n-69)<<2) :INVALID_GPIO_MFPR_ADDR) #endif typedef struct { volatile int * registerAddr; unsigned int regValue; unsigned int defaultValue; }CS_REGISTER_PAIR_S, *P_CS_REGISTER_PAIR_S; typedef struct { int pin; int gpio; CS_REGISTER_PAIR_S reg_config; }quec_gpio_map_pin_s; void quec_instruction_mode(void); int serial_read_byte(void); void timerDelay_us(UINT32 us); extern void cp_uart_putc(const char ch); extern int GuilinWrite( Guilin_Reg_Type guilin_reg_type, unsigned char reg, unsigned char value ); #endif