/******************************************************************************
**
**  COPYRIGHT (C) 2001, 2002 Intel Corporation.
**
**  This software as well as the software described in it is furnished under
**  license and may only be used or copied in accordance with the terms of the
**  license. The information in this file is furnished for informational use
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**  this document. 
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by
**  any means without the express written consent of Intel Corporation. 
**
**  FILENAME:       xllp_dmac.h
**
**  PURPOSE: contains all DMA Controller specific macros, typedefs, and prototypes.
**           Declares no storage.
**                  
**
******************************************************************************/
/******************************************************************************
 *
 *  (C)Copyright 2005 - 2011 Marvell. All Rights Reserved.
 *
 *  THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MARVELL.
 *  The copyright notice above does not evidence any actual or intended
 *  publication of such source code.
 *  This Module contains Proprietary Information of Marvell and should be
 *  treated as Confidential.
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 *  include this notice and the associated copyright notice with any such
 *  product.
 *  The information in this file is provided "AS IS" without warranty.
 
 ******************************************************************************
**
**  FILENAME:       xllp_dmac.c
**
**  PURPOSE: contains all primitive functions for Bulverde DMA Controller register
**           access and control
**
******************************************************************************/

#ifndef __DMAC_H__
#define __DMAC_H__


#define MAX_DMA_CHANNELS  			32
#define DMA_STATUS_INTERRUPTS_MASK	0x01000217

/**
 * DCSR Register 
 **/
#define XLLP_DMAC_DCSR_BUS_ERR_INTR		 (1U<<0)
#define XLLP_DMAC_DCSR_START_INTR		 (1U<<1)
#define XLLP_DMAC_DCSR_END_INTR			 (1U<<2)
#define XLLP_DMAC_DCSR_STOP_INTR		 (1U<<3)
#define XLLP_DMAC_DCSR_RAS_INTR          (1U<<4)
#define XLLP_DMAC_DCSR_REQ_PEND			 (1U<<8)
#define XLLP_DMAC_DCSR_EOR_INTR			 (1U<<9)
#define XLLP_DMAC_DCSR_CMP_ST 			 (1U<<10)
#define XLLP_DMAC_DCSR_MASK_RUN          (1U<<22)
#define XLLP_DMAC_DCSR_RAS_EN            (1U<<23)
#define XLLP_DMAC_DCSR_CLR_CMP_ST		 (1U<<24)
#define XLLP_DMAC_DCSR_SET_CMP_ST		 (1U<<25)
#define XLLP_DMAC_DCSR_EOR_STOP_EN		 (1U<<26)
#define XLLP_DMAC_DCSR_EOR_JMP_ENT		 (1U<<27)
#define XLLP_DMAC_DCSR_EOR_IRQ_EN		 (1U<<28)
#define XLLP_DMAC_DCSR_STOP_IRQ_EN		 (1U<<29)
#define XLLP_DMAC_DCSR_NO_DESC_FETCH	 (1U<<30)
#define XLLP_DMAC_DCSR_RUN 		  		 (1U<<31)
#define XLLP_DMAC_DCSR_WRITABLES_MSK	 0xFFC00617 

#endif //__DMAC_H__