508 lines
20 KiB
C
508 lines
20 KiB
C
#ifndef _SDIO_H_
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#define _SDIO_H_
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#include "common.h"
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//used for sd card
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#define SD1_HOST_CTRL_ADDR 0xD4280000
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/*Err code*/
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#define MMC_ERR_NONE 0
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#define MMC_ERR_CMD_TOUT 1
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#define MMC_ERR_DATA_TOUT 2
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#define MMC_ERR_DATA_CRC 3
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#define MMC_ERR_INVALID 4
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#define MMC_ERR_OUTRANGE 5
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#define MMC_ERR_IO 6
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#define MMC_ERR_INVALIDARG 7
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#define MMC_ERR_OUTMEMORY 8
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#define STATUS_FAILURE -1
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#define ERR_INT ((UINT16)1 << 15) /* Error Interrupt*/
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#define CARD_INT ((UINT16)1 << 8) /* Card Interrupt */
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#define CARD_REM ((UINT16)1 << 7) /* Card Removal Interrupt */
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#define CARD_INS ((UINT16)1 << 6) /* Card Insertion Interrupt */
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#define RX_RDY ((UINT16)1 << 5) /* Buffer Read Ready */
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#define TX_RDY ((UINT16)1 << 4) /* Buffer Write Ready */
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#define DMA_INT ((UINT16)1 << 3) /* DMA interupt */
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#define BLK_GAP_EVNT ((UINT16)1 << 2) /* Block Gap Event */
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#define XFER_COMP ((UINT16)1 << 1) /* Transfer Complete */
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#define CMD_COMP ((UINT16)1 << 0) /* Command Complete */
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#define CRC_STATUS_ERR ((UINT16)1 << 15) /* CRC Status Error Returned from Card in Write Transaction*/
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#define CPL_TO_ERR ((UINT16)1 << 14) /* Command Completion Signal Timeout Error, for CE-ATA mode only*/
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#define AXI_RESP_ERR ((UINT16)1 << 13) /* AXI Bus Response Error */
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#define SPI_ERR ((UINT16)1 << 12) /* SPI Mode Error*/
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#define ADMA_ERR ((UINT16)1 << 9) /* AMDA Error */
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#define AUTO_CMD12_ERR ((UINT16)1 << 8) /* Auto CMD12 Error*/
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#define CUR_LIMIT_ERR ((UINT16)1 << 7) /* Current Limit Error*/
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#define RD_DATA_END_ERR ((UINT16)1 << 6) /* Read Data End Bit Error*/
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#define RD_DATA_CRC_ERR ((UINT16)1 << 5) /* Read Data CRC Error*/
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#define DATA_TO_ERR ((UINT16)1 << 4) /* Data Timeout Error*/
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#define CMD_IDX_ERR ((UINT16)1 << 3) /* Command Index Error*/
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#define CMD_END_BIT_ERR ((UINT16)1 << 2) /* Command End Bit Error*/
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#define CMD_CRC_ERR ((UINT16)1 << 1) /* Command CRC Error*/
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#define CMD_TO_ERR ((UINT16)1 << 0) /* Command Timeout Error*/
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#define SD_ERR_INT_EN_RVD_MASK ((UINT16)0x0c00) /* Mask for SD_ERR_INT_EN/SD_ERR_I_STAT_EN Reserved Bits[11 :10] */
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#define SD_ERR_INT_DATA_ERR_MASK (DATA_TO_ERR | RD_DATA_CRC_ERR | RD_DATA_END_ERR) /*DATA Line Error*/
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#define SD_ERR_INT_CMD_ERR_MASK (CMD_TO_ERR | CMD_CRC_ERR | CMD_END_BIT_ERR | CMD_IDX_ERR) /* CMD Line Error*/
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#define SD0_HOST_PMU_AXI_CLOCK 0xd4282854
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#define SD1_HOST_PMU_AXI_CLOCK 0xd4282858
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#define SD2_HOST_PMU_AXI_CLOCK 0xd42828E0
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#define APB_CLOCK_UNIT_PHYSICAL_BASE 0xD4015000
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#define APBC_GPIO_CLK_RST_offset 0x0008
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#define SD_SYSADDR_LOW_offset 0x00
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#define SD_SYSADDR_HIGH_offset 0x02
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#define SD_BLOCK_SIZE_offset 0x04
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#define SD_BLOCK_COUNT_offset 0x06
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#define SD_ARG_LOW_offset 0x08
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#define SD_ARG_HIGH_offset 0x0A
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#define SD_TRANSFER_MODE_offset 0x0C
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#define SD_CMD_offset 0x0E
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#define SD_RESP_0_offset 0x10
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#define SD_RESP_1_offset 0x12
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#define SD_RESP_2_offset 0x14
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#define SD_RESP_3_offset 0x16
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#define SD_RESP_4_offset 0x18
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#define SD_RESP_5_offset 0x1A
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#define SD_RESP_6_offset 0x1C
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#define SD_RESP_7_offset 0x1E
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#define SD_BUF_PORT_0_offset 0x20
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#define SD_BUF_PORT_1_offset 0x22
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#define SD_PRESENT_STAT_0_offset 0x24
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#define SD_PRESENT_STAT_1_offset 0x26
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#define SD_HOST_CTRL_offset 0x28
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#define SDHCI_POWER_CONTROL 0x29
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#define SD_BGAP_CTRL_offset 0x2A
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#define SD_CLOCK_CTRL_offset 0x2C
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#define SD_SW_RESET_CTRL_offset 0x2E
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#define SD_NORM_INTR_STS_offset 0x30
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#define SD_ERR_INTR_STS_offset 0x32
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#define SD_NORM_INTR_STS_EBLE_offset 0x34
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#define SD_ERR_INTR_STS_EBLE_offset 0x36
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#define SD_NORM_INTR_STS_INTR_EBLE_offset 0x38
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#define SD_ERR_INTR_STS_INTR_EBLE_offset 0x3A
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#define SD_ADMA_SYS_ADDR_offset 0x58
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#define SD_ADMA_SYS_ADDR2_offset 0x5C
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#define SD_CE_ATA_1_offset 0xE8
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#define SD_PAD_IO_SETUP 0xEC
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#define SDHCI_WAKE_UP_CONTROL 0x2B
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#define SDHCI_ACMD12_ERR 0x3C
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#define SDHCI_SLOT_INT_STATUS 0xFC
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#define SDHCI_HOST_CTRL2 0X3E
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#define SDHCI_PRESET_VALUE_FOR_SDR50 0x6A
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#ifdef PLAT_NEZHAC
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#define SD_CLOCK_AND_BURST_SIZE_SETUP_offset 0x104
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#define SDHCI_TX_CFG 0X11C
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#define SDHCI_RX_CFG_REG 0x118
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#else
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#define SD_CLOCK_AND_BURST_SIZE_SETUP_offset 0x10A
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#define SD_FIFO_PARA_offset 0x104
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#define SDHCI_TX_CFG 0X118
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#define SDHCI_RX_CFG_REG 0x114
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#endif
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#define SDHCI_MAX_CURRENT 0x48
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#define SDHCI_HOST_VERSION 0xFE
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#define SDHCI_VENDOR_VER_MASK 0xFF00
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#define SDHCI_VENDOR_VER_SHIFT 8
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#define SDHCI_SPEC_VER_MASK 0x00FF
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#define SDHCI_SPEC_VER_SHIFT 0
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#define SDHCI_SPEC_100 0
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#define SDHCI_SPEC_200 1
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#define SDHCI_SPEC_300 2
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#define SDHCI_CLOCK_CARD_EN 0x0004
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#define SDHCI_CLOCK_INT_STABLE 0x0002
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#define SDHCI_CLOCK_INT_EN 0x0001
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#define SDHCI_CAPABILITIES 0x40
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#define SDHCI_CAPABILITIES2 0x42
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#define SDHCI_CAPABILITIES3 0x44
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#define SDHCI_CAPABILITIES4 0x46
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#define SDIO_CCCR_UHS 0x14
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#define SDR50_SUPPORT 1<<0
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#define SDR104_SUPPORT 1<<1
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#define DDR50_SUPPORT 1<<2
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#define SDIO_CCCR_DRIVE_STRENGTH 0x15
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#define SDIO_STTx_MASK 0x07
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#define SDIO_DRIVE_SDTA (1<<0)
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#define SDIO_DRIVE_SDTC (1<<1)
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#define SDIO_DRIVE_SDTD (1<<2)
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#define SDIO_DRIVE_DTSx_MASK 0x03
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#define SDIO_DRIVE_DTSx_SHIFT 4
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#define SDIO_DTSx_SET_TYPE_B (0<<SDIO_DRIVE_DTSx_SHIFT)
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#define SDIO_DTSx_SET_TYPE_A (1<<SDIO_DRIVE_DTSx_SHIFT)
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#define SDIO_DTSx_SET_TYPE_C (2<<SDIO_DRIVE_DTSx_SHIFT)
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#define SDIO_DTSx_SET_TYPE_D (3<<SDIO_DRIVE_DTSx_SHIFT)
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#define SD_DRIVER_TYPE_B 0x01
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#define SD_DRIVER_TYPE_A 0x02
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#define SD_DRIVER_TYPE_C 0x04
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#define SD_DRIVER_TYPE_D 0x08
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#define MMC_SET_DRIVER_TYPE_B 0
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#define MMC_SET_DRIVER_TYPE_A 1
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#define MMC_SET_DRIVER_TYPE_C 2
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#define MMC_SET_DRIVER_TYPE_D 3
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#define UHS_SDR12_BUS_SPEED 0
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#define HIGH_SPEED_BUS_SPEED 1
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#define UHS_SDR25_BUS_SPEED 1
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#define UHS_SDR50_BUS_SPEED 2
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#define UHS_SDR104_BUS_SPEED 3
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#define UHS_DDR50_BUS_SPEED 4
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#define SD_MODE_HIGH_SPEED (1<<HIGH_SPEED_BUS_SPEED)
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#define SD_MODE_UHS_SDR12 (1<<UHS_SDR12_BUS_SPEED)
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#define SD_MODE_UHS_SDR50 (1<<UHS_SDR50_BUS_SPEED)
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#define SD_MODE_UHS_SDR104 (1<<UHS_SDR104_BUS_SPEED)
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#define SD_MODE_UHS_DDR50 (1<<UHS_DDR50_BUS_SPEED)
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#define SD_DRIVER_A (1<<4)
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#define SD_DRIVER_C (1<<5)
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#define SD_DRIVER_D (1<<6)
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#define SDHCI_CTRL_VDD_180 0x0008
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#define SDHCI_DATA_LVL_MASK 0x00F00000
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#define SDHCI_DATA_LVL_SHIFT 20
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#define SDHCI_SIGNAL_VOLTAGE_330 0
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#define SDHCI_SIGNAL_VOLTAGE_180 1
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#define SDHCI_SIGNAL_VOLTAGE_120 2
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#define SDHCI_POWER_ON 0x01
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#define SDHCI_SOFTWARE_RESET 0x2F
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#define SDHCI_CMD_INHIBIT 0x00000001
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#define SDHCI_DATA_INHIBIT 0x00000002
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#define SDHCI_DOING_WRITE 0x00000100
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#define SDHCI_DOING_READ 0x00000200
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#define SDHCI_SPACE_AVAILABLE 0x00000400
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#define SDHCI_DATA_AVAILABLE 0x00000800
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#define SDHCI_CARD_PRESENT 0x00010000
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#define SDHCI_WRITE_PROTECT 0x00080000
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#define SDHCI_TRNS_DMA 0x01
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#define SDHCI_TRNS_BLK_CNT_EN 0x02
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#define SDHCI_TRNS_ACMD12 0x04
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#define SDHCI_TRNS_READ 0x10
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#define SDHCI_TRNS_MULTI 0x20
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#define SDHCI_CTRL_DMA_MASK 0x18
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#define SDHCI_CTRL_SDMA 0x00
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#define SDHCI_CTRL_ADMA1 0x08
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#define SDHCI_CTRL_ADMA32 0x10
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#define SDHCI_CTRL_ADMA64 0x18
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#define SDHCI_CTRL_4BITBUS 0x02
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#define SDHCI_CTRL_HISPD 0x04
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#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
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/* SD_TO_CTRL_SW_RST */
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#define SW_RST_DAT ((UINT16)1 << 10)
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#define SW_RST_CMD ((UINT16)1 << 9)
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#define SW_RST_ALL ((UINT16)1 << 8)
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#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
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#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
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#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
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#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
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#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
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#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
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#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
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#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
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#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
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#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
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#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
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#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
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#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
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#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
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#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
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#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
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#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
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#define MMC_OCR_AVAIL (MMC_VDD_26_27 | MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_30_31)
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#define _readl(p) (*(volatile unsigned long *)(p))
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#define _writel(v,p) (*(volatile unsigned long *)(p) = (v))
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#define xlli_TWSI_PHYSICAL_BASE 0xD4011000
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#define APBC_TWSI_CLK_RST (0xD4015000+0x002C)
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/*
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* I2C registers and bit definitions
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*/
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#define IBMR (0x00)
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#define IDBR (0x08)
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#define ICR (0x10)
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#define ISR (0x18)
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#define ISAR (0x20)
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#define ILCR (0x28)
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#define SCL (1 << 1)
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#define SDA (1 << 0)
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#define ICR_START (1 << 0) /* start bit */
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#define ICR_STOP (1 << 1) /* stop bit */
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#define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
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#define ICR_TB (1 << 3) /* transfer byte bit */
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#define ICR_MA (1 << 4) /* master abort */
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#define ICR_SCLE (1 << 5) /* master clock enable */
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#define ICR_IUE (1 << 6) /* unit enable */
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#define ICR_GCD (1 << 7) /* general call disable */
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#define ICR_ITEIE (1 << 8) /* enable tx interrupts */
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#define ICR_IRFIE (1 << 9) /* enable rx interrupts */
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#define ICR_BEIE (1 << 10) /* enable bus error ints */
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#define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
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#define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
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#define ICR_SADIE (1 << 13) /* slave address detected int enable */
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#define ICR_UR (1 << 14) /* unit reset */
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#define ICR_FM (1 << 15) /* fast mode */
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#define ISR_RWM (1 << 0) /* read/write mode */
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#define ISR_ACKNAK (1 << 1) /* ack/nak status */
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#define ISR_UB (1 << 2) /* unit busy */
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#define ISR_IBB (1 << 3) /* bus busy */
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#define ISR_SSD (1 << 4) /* slave stop detected */
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#define ISR_ALD (1 << 5) /* arbitration loss detected */
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#define ISR_ITE (1 << 6) /* tx buffer empty */
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#define ISR_IRF (1 << 7) /* rx buffer full */
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#define ISR_GCAD (1 << 8) /* general call address detected */
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#define ISR_SAD (1 << 9) /* slave address detected */
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#define ISR_BED (1 << 10) /* bus error no ACK/NAK */
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#define ICR_MODE_100 0x0000 //100kbps standard mode
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#define ICR_MODE_400 0x8000 //400kbps fast mode
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#define ICR_MODE_HS 0x10000 //high speed mode
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#define I2C_QUICK 0
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#define I2C_BYTE 1
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#define I2C_BYTE_DATA 2
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#define I2C_WORD_DATA 3
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#define I2C_PROC_CALL 4
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#define I2C_BLOCK_BYTE 5
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#define I2C_BLOCK_BROKEN 6
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#define I2C_BLOCK_PROC_CALL 7 /* SMBus 2.0 */
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#define I2C_BLOCK_DATA 8
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union i2c_data
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{
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UINT8 byte;
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UINT16 word;
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UINT8 block[32]; /* block[0] is used for length */
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};
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/*
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* Card Common Control Registers (CCCR)
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*/
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#define SDIO_CCCR_CCCR 0x00
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#define SDIO_CCCR_REV_1_00 0 /* CCCR/FBR Version 1.00 */
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#define SDIO_CCCR_REV_1_10 1 /* CCCR/FBR Version 1.10 */
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#define SDIO_CCCR_REV_1_20 2 /* CCCR/FBR Version 1.20 */
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#define SDIO_CCCR_REV_3_00 3 /* CCCR/FBR Version 3.00 */
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#define SDIO_SDIO_REV_1_00 0 /* SDIO Spec Version 1.00 */
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#define SDIO_SDIO_REV_1_10 1 /* SDIO Spec Version 1.10 */
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#define SDIO_SDIO_REV_1_20 2 /* SDIO Spec Version 1.20 */
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#define SDIO_SDIO_REV_2_00 3 /* SDIO Spec Version 2.00 */
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#define SDIO_SDIO_REV_3_00 4 /* SDIO Spec Version 3.00 */
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#define SDIO_CCCR_SD 0x01
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#define SDIO_SD_REV_1_01 0 /* SD Physical Spec Version 1.01 */
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#define SDIO_SD_REV_1_10 1 /* SD Physical Spec Version 1.10 */
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#define SDIO_SD_REV_2_00 2 /* SD Physical Spec Version 2.00 */
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#define SDIO_CCCR_IOEx 0x02
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#define SDIO_CCCR_IORx 0x03
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#define SDIO_CCCR_IENx 0x04 /* Function/Master Interrupt Enable */
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#define SDIO_CCCR_INTx 0x05 /* Function Interrupt Pending */
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#define SDIO_CCCR_ABORT 0x06 /* function abort/card reset */
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#define SDIO_CCCR_IF 0x07 /* bus interface controls */
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#define SDIO_BUS_WIDTH_1BIT 0x00
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#define SDIO_BUS_WIDTH_4BIT 0x02
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#define SDIO_BUS_CD_DISABLE 0x80 /* disable pull-up on DAT3 (pin 1) */
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#define SDIO_CCCR_CAPS 0x08
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#define SDIO_CCCR_CAP_SDC 0x01 /* can do CMD52 while data transfer */
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#define SDIO_CCCR_CAP_SMB 0x02 /* can do multi-block xfers (CMD53) */
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#define SDIO_CCCR_CAP_SRW 0x04 /* supports read-wait protocol */
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#define SDIO_CCCR_CAP_SBS 0x08 /* supports suspend/resume */
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#define SDIO_CCCR_CAP_S4MI 0x10 /* interrupt during 4-bit CMD53 */
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#define SDIO_CCCR_CAP_E4MI 0x20 /* enable ints during 4-bit CMD53 */
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#define SDIO_CCCR_CAP_LSC 0x40 /* low speed card */
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#define SDIO_CCCR_CAP_4BLS 0x80 /* 4 bit low speed card */
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#define SDIO_CCCR_CIS 0x09 /* common CIS pointer (3 bytes) */
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/* Following 4 regs are valid only if SBS is set */
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#define SDIO_CCCR_SUSPEND 0x0c
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#define SDIO_CCCR_SELx 0x0d
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#define SDIO_CCCR_EXECx 0x0e
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#define SDIO_CCCR_READYx 0x0f
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#define SDIO_CCCR_BLKSIZE 0x10
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#define SDIO_CCCR_POWER 0x12
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#define SDIO_POWER_SMPC 0x01 /* Supports Master Power Control */
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#define SDIO_POWER_EMPC 0x02 /* Enable Master Power Control */
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#define SDIO_CCCR_SPEED 0x13
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#define SDIO_SPEED_SHS 0x01 /* Supports High-Speed mode */
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#define SDIO_SPEED_EHS 0x02 /* Enable High-Speed mode */
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#define SDIO_SPEED_BSS_SHIFT 1
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#define SDIO_SPEED_BSS_MASK (7<<SDIO_SPEED_BSS_SHIFT)
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#define SDIO_SPEED_SDR12 (0<<SDIO_SPEED_BSS_SHIFT)
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#define SDIO_SPEED_SDR25 (1<<SDIO_SPEED_BSS_SHIFT)
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#define SDIO_SPEED_SDR50 (2<<SDIO_SPEED_BSS_SHIFT)
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#define SDIO_SPEED_SDR104 (3<<SDIO_SPEED_BSS_SHIFT)
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#define SDIO_SPEED_DDR50 (4<<SDIO_SPEED_BSS_SHIFT)
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#define MMC_TIMING_LEGACY 0
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#define MMC_TIMING_MMC_HS 1
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#define MMC_TIMING_SD_HS 2
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#define MMC_TIMING_UHS_SDR12 MMC_TIMING_LEGACY
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#define MMC_TIMING_UHS_SDR25 MMC_TIMING_SD_HS
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#define MMC_TIMING_UHS_SDR50 3
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#define MMC_TIMING_UHS_SDR104 4
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#define MMC_TIMING_UHS_DDR50 5
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#define MMC_TIMING_MMC_HS200 6
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#define HIGHT_SPEED_MAX_DTR 50000000
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#define UHS_SDR104_MAX_DTR 208000000
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#define UHS_SDR50_MAX_DTR 100000000
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#define UHS_DDR50_MAX_DTR 50000000
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#define UHS_SDR25_MAX_DTR UHS_DDR50_MAX_DTR
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#define UHS_SDR12_MAX_DTR 25000000
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/*
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* Function Basic Registers (FBR)
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*/
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#define SDIO_FBR_BASE(f) ((f) * 0x100) /* base of function f's FBRs */
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#define SDIO_FBR_STD_IF 0x00
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#define SDIO_FBR_SUPPORTS_CSA 0x40 /* supports Code Storage Area */
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#define SDIO_FBR_ENABLE_CSA 0x80 /* enable Code Storage Area */
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#define SDIO_FBR_STD_IF_EXT 0x01
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#define SDIO_FBR_POWER 0x02
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#define SDIO_FBR_POWER_SPS 0x01 /* Supports Power Selection */
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#define SDIO_FBR_POWER_EPS 0x02 /* Enable (low) Power Selection */
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#define SDIO_FBR_CIS 0x09 /* CIS pointer (3 bytes) */
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#define SDIO_FBR_CSA 0x0C /* CSA pointer (3 bytes) */
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#define SDIO_FBR_CSA_DATA 0x0F
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#define SDIO_FBR_BLKSIZE 0x10 /* block size (2 bytes) */
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#define SDIO_CIS_BASE 0x1000 /* base of CIS Area */
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|
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/*
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*R5 is reponse of cmd52 and cmd53
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|
*/
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#define R5_COM_CRC_ERROR (1 << 15) /* er, b */
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#define R5_ILLEGAL_COMMAND (1 << 14) /* er, b */
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#define R5_ERROR (1 << 11) /* erx, c */
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#define R5_FUNCTION_NUMBER (1 << 9) /* er, c */
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#define R5_OUT_OF_RANGE (1 << 8) /* er, c */
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|
|
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#define R4_18V_PRESENT (1<<24)
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|
#define R4_MEMORY_PRESENT (1<<27)
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|
//#ifndef __max_min__
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|
//#define __max_min__
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|
//#define max(a, b) (((a) > (b)) ? (a) : (b))
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//#define min(a, b) (((a) < (b)) ? (a) : (b))
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//#endif
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typedef struct _sdio_cccr
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|
{
|
|
unsigned int sdio_vsn;
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|
unsigned int multi_block:1,
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|
low_speed:1,
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|
wide_bus:1,
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|
high_power:1,
|
|
high_speed:1;
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}sdio_cccr;
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|
|
|
/*
|
|
* SDIO function CIS tuple (unknown to the core)
|
|
*/
|
|
struct sdio_func_tuple
|
|
{
|
|
struct sdio_func_tuple *next;
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|
unsigned char code;
|
|
unsigned char size;
|
|
// unsigned char data[0];
|
|
unsigned char data;
|
|
};
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|
|
|
typedef int (tpl_parse_t)(UINT8, const unsigned char *, unsigned);
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|
|
|
struct cis_tpl
|
|
{
|
|
unsigned char code;
|
|
unsigned char min_size;
|
|
tpl_parse_t *parse;
|
|
};
|
|
#if 0
|
|
int cistpl_manfid(UINT8, const unsigned char *buf, unsigned size);
|
|
int cistpl_funce(UINT8, const unsigned char *buf, unsigned size);
|
|
|
|
static const struct cis_tpl cis_tpl_list[] =
|
|
{
|
|
{ 0x15, 3, 0/*cistpl_vers_1*/ },
|
|
{ 0x20, 4, cistpl_manfid },
|
|
{ 0x21, 2, 0/*cistpl_funcid*/ },
|
|
{ 0x22, 0, cistpl_funce },
|
|
};
|
|
#endif
|
|
struct sdio_func
|
|
{
|
|
unsigned int num; /* function number */
|
|
unsigned max_blksize; /* maximum block size */
|
|
unsigned cur_blksize; /* current block size */
|
|
unsigned char class; /* standard interface class */
|
|
unsigned int vendor; /* vendor id */
|
|
unsigned int device; /* device id */
|
|
};
|
|
|
|
#define FUNCTION_BLOCKSIZE 256
|
|
|
|
#define MAXFUNCTION 8
|
|
#define VENDORID (0x02df)
|
|
|
|
#define SINGLE_BLOCK_SIZE_SHIFT 9
|
|
#define SINGLE_BLOCK_SIZE 0x200
|
|
|
|
extern UINT32 SD_CTRL_BASE_ADDR;
|
|
|
|
int sdio_init(void);
|
|
int sdcard_init(void);
|
|
UINT32 sdcard_read_multiblks(UINT32 base, UINT32 buffer, UINT32 loop, UINT32 blk_cnt);
|
|
UINT32 sdcard_write_multiblks(UINT32 base, UINT32 buffer, UINT32 loop, UINT32 blk_cnt);
|
|
UINT32 sdcard_write_mass_storage(UINT32 buffer, UINT32 loop, UINT32 blk_cnt);
|
|
UINT32 sdcard_read_mass_storage(UINT32 buffer, UINT32 loop, UINT32 blk_cnt);
|
|
BOOL sdcard_is_ready(void);
|
|
|
|
#endif //_SDIO_H_
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