417 lines
15 KiB
C
417 lines
15 KiB
C
/******************************************************************************
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*
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* Name: ssp_reg.h
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* Project: Hermon-2
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* Purpose: Testing
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*
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******************************************************************************/
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/******************************************************************************
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*
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* (C)Copyright 2005 - 2011 Marvell. All Rights Reserved.
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*
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* THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MARVELL.
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* The copyright notice above does not evidence any actual or intended
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* publication of such source code.
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* This Module contains Proprietary Information of Marvell and should be
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* treated as Confidential.
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* The information in this file is provided for the exclusive use of the
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* licensees of Marvell.
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* Such users have the right to use, modify, and incorporate this code into
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* products for purposes authorized by the license agreement provided they
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* include this notice and the associated copyright notice with any such
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* product.
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* The information in this file is provided "AS IS" without warranty.
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*
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******************************************************************************/
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/******************************************************************************
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*
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* This file was automatically generated by reg.pl using * SSP.csv
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*
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******************************************************************************/
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/******************************************************************************
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*
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* History:
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*
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********* PLEASE INSERT THE CVS HISTORY OF THE PREVIOUS VERSION HERE. *********
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*******************************************************************************/
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#ifndef __INC_SSP_H
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#define __INC_SSP_H
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/*
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*
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* THE BASE ADDRESSES
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*
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*/
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#define SSP0_BASE 0xD401B000
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#define SSP1_BASE 0xD401B800
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#define SSP2_BASE 0xD401C000
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#define APBC_SSP0_CLK_RST (0xD4015000 + 0x001C) //Clock/Reset Control Register for SSP 0
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#define APBC_SSP1_CLK_RST (0xD4015000 + 0x0020) //Clock/Reset Control Register for SSP 1
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#define APBC_SSP2_CLK_RST (0xD4015000 + 0x004C) //Clock/Reset Control Register for SSP 2
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#define GPIO0_BASE 0xD4019000
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#define GPIO1_BASE 0xD4019004
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#define GPIO2_BASE 0xD4019008
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#define GPIO3_BASE 0xD4019100
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#define GPIO_PLR (0x0000) /* 32 bit GPIO Pin-Level Register */
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#define GPIO_PDR (0x000C) /* 32 bit GPIO Pin Direction Register */
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#define GPIO_PSR (0x0018) /* 32 bit GPIO Pin Output Set Register */
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#define GPIO_PCR (0x0024) /* 32 bit GPIO Pin Output Clear Register */
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#define GPIO_RER (0x0030) /* 32 bit GPIO Rising-Edge Detect Enable Register*/
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#define GPIO_FERX (0x003C) /* 32 bit GPIO Falling-Edge Detect Enable Register*/
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#define GPIO_EDR (0x0048) /* 32 bit GPIO Edge Detect Status Register */
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#define GPIO_SDR (0x0054) /* 32 bit Bit-wise Set of GPIO Direction Register */
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#define GPIO_CDR (0x0060) /* 32 bit Bit-wise Clear of GPIO Direction Register */
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#define GPIO_SRERX (0x006c) /* 32 bit Bit-wise Set of GPIO Rising Edge Detect Enable Register */
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#define GPIO_CRERX (0x0078) /* 32 bit Bit-wise Clear of GPIO Rising Edge Detect Enable Register */
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#define GPIO_SFER (0x0084) /* 32 bit Bit-wise Set of GPIO Falling Edge Detect Enable Register */
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#define GPIO_CFER (0x0090) /* 32 bit Bit-wise Clear of GPIO Falling Edge Detect Enable Register */
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#define APMASK (0x009c) /* 32 bit AP Bit-wise Mask of GPIO Edge Detect Register */
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#define CPMASK (0x00a8) /* 32 bit CP Bit-wise Mask of GPIO Edge Detect Register */
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#define FlashAddrOutOfRange 0x3d
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#define SSPWaitTxEmptyTimeOutError 0x80
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#define SSPRdStatusTimeOutError 0x81
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#define SSPWelWaitTxEmptyTimeOutError 0x82
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#define SSPWaitForWELTimeOutError 0x83
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#define SSPWaitCompleteTimeOutError 0x84
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#define SSPRxChannelTimeOutError 0x85
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#define SSPTxChannelTimeOutError 0x86
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#define SSPNOTREADY 0x87
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/*
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*
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* THE REGISTER DEFINES
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*
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*/
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#define SSP_SSCR0 (0x0000) /* 32 bit SSP Control Register 0 */
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#define SSP_SSCR1 (0x0004) /* 32 bit SSP Control Register 1 */
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#define SSP_SSSR (0x0014) /* 32 bit SSP Status Register */
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#define SSP_SSITR (0x000C) /* 32 bit SSP Interrupt Test
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* Register
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*/
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#define SSP_SSDR (0x0010) /* 32 bit SSP Data Register */
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#define SSP_SSTO (0x0028) /* 32 bit SSP Time Out Register */
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#define SSP_SSPSP (0x002C) /* 32 bit SSP Programmable Serial
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* Protocol Register
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*/
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#define SSP_SSTSA (0x0030) /* 32 bit SSP TX Time Slot Active
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* Register
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*/
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#define SSP_SSRSA (0x0034) /* 32 bit SSP RX Time Slot Active
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* Register
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*/
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#define SSP_SSTSS (0x0038) /* 32 bit SSP Time Slot Status
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* Register
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*/
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#define SSP_SSACD (0x003C) /* 32 bit SSP Audio Clock Divider
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* Register
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*/
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#define SSP_SSACDD (0x0040) /* 32 bit SSP Audio Clock Dither
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* Divider Register
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*/
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#define DUMMY_REGISTER (0x0000) /* 32 bit This is a Dummy Register */
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/*
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*
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* THE BIT DEFINES
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*
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*/
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/* SSP_SSCR0 0x0000 SSP Control Register 0 */
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#define SSP_SSCR0_MOD BIT_31 /* Mode */
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#define SSP_SSCR0_ACS BIT_30 /* Audio Clock Select */
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#define SSP_SSCR0_FPCKE BIT_29 /* FIFO Packing Enable */
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/* Bit(s) SSP_SSCR0_RSRV_28 reserved */
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#define SSP_SSCR0_52MM BIT_27 /* 52M[bps] M[ode */
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#define SSP_SSCR0_FRDC_MSK SHIFT24(0x7) /* Frame Rate Divider Control */
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#define SSP_SSCR0_FRDC_BASE 24
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/* Transmit FIFO Underrun Interrupt Mask */
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#define SSP_SSCR0_TIM BIT_23
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/* Receive FIFO Overrun Interrupt Mask */
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#define SSP_SSCR0_RIM BIT_22
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#define SSP_SSCR0_NCS BIT_21 /* Network Clock Select */
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#define SSP_SSCR0_EDSS BIT_20 /* Extended Data Size Select */
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#define SSP_SSCR0_SCR_MSK SHIFT8(0xfff) /* Serial Clock Rate */
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#define SSP_SSCR0_SCR_BASE 8
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#define SSP_SSCR0_SSE BIT_7 /* Synchronous Serial Port Enable */
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#define SSP_SSCR0_ECS BIT_6 /* External Clock Select */
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#define SSP_SSCR0_FRF_MSK SHIFT4(0x3) /* Frame Format */
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#define SSP_SSCR0_FRF_BASE 4
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#define SSP_SSCR0_DSS_MSK SHIFT0(0xf) /* Data Size Select */
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#define SSP_SSCR0_DSS_BASE 0
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/* SSP_SSCR1 0x0004 SSP Control Register 1 */
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/* TXD Three-state Enable On Last Phase */
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#define SSP_SSCR1_TTELP BIT_31
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#define SSP_SSCR1_TTE BIT_30 /* TXD Three-State Enable */
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#define SSP_SSCR1_EBCEI BIT_29 /* Enable Bit Count Error Interrupt */
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#define SSP_SSCR1_SCFR BIT_28 /* Slave Clock Free Running */
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#define SSP_SSCR1_ECRA BIT_27 /* Enable Clock Request A */
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#define SSP_SSCR1_ECRB BIT_26 /* Enable Clock Request B */
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/* SSP Serial Bit Rate Clock (SSPSCLKx) Direction */
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#define SSP_SSCR1_SCLKDIR BIT_25
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#define SSP_SSCR1_SFRMDIR BIT_24 /* SSP Frame (SSPSFRMx) Direction */
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#define SSP_SSCR1_RWOT BIT_23 /* Receive Without Transmit */
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#define SSP_SSCR1_TRAIL BIT_22 /* Trailing Byte */
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#define SSP_SSCR1_TSRE BIT_21 /* Transmit Service Request Enable */
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#define SSP_SSCR1_RSRE BIT_20 /* Receive Service Request Enable */
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/* Receiver Time-out Interrupt Enable */
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#define SSP_SSCR1_TINTE BIT_19
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/* Peripheral Trailing Byte Interrupt Enable */
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#define SSP_SSCR1_PINTE BIT_18
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/* Bit(s) SSP_SSCR1_RSRV_17 reserved */
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#define SSP_SSCR1_IFS BIT_16 /* Invert Frame Signal */
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#define SSP_SSCR1_STRF BIT_15 /* Select FIFO For Efwr */
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#define SSP_SSCR1_EFWR BIT_14 /* Enable FIFO Write/read */
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#define SSP_SSCR1_RFT_MSK SHIFT10(0xf) /* RXFIFO Trigger Threshold */
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#define SSP_SSCR1_RFT_BASE 10
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#define SSP_SSCR1_TFT_MSK SHIFT6(0xf) /* TXFIFO Trigger Threshold */
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#define SSP_SSCR1_TFT_BASE 6
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/* Motorola SPI SSPSCLK phase setting */
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#define SSP_SSCR1_SPH BIT_4
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/* Motorola SPI SSPSCLK Polarity Setting */
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#define SSP_SSCR1_SPO BIT_3
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#define SSP_SSCR1_LBM BIT_2 /* Loopback Mode */
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#define SSP_SSCR1_TIE BIT_1 /* Transmit FIFO Interrupt Enable */
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#define SSP_SSCR1_RIE BIT_0 /* Receive FIFO Interrupt Enable */
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/* SSP_SSSR 0x0008 SSP Status Register */
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#define SSP_SSSR_OSS BIT_31 /* Odd Sample Status */
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/* TX FIFO Odd Sample Status */
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#define SSP_SSSR_TX_OSS BIT_30
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/* Bit(s) SSP_SSSR_RSRV_29_24 reserved */
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#define SSP_SSSR_BCE BIT_23 /* Bit Count Error */
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/* Clock Synchronization Status */
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#define SSP_SSSR_CSS BIT_22
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#define SSP_SSSR_TUR BIT_21 /* Transmit FIFO Underrun */
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#define SSP_SSSR_EOC BIT_20 /* End Of Chain */
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/* Receiver Time-out Interrupt */
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#define SSP_SSSR_TINT BIT_19
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/* Peripheral Trailing Byte Interrupt */
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#define SSP_SSSR_PINT BIT_18
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/* Bit(s) SSP_SSSR_RSRV_17_16 reserved */
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#define SSP_SSSR_RFL_MSK SHIFT12(0xf) /* Receive FIFO Level */
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#define SSP_SSSR_RFL_BASE 12
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#define SSP_SSSR_TFL_MSK SHIFT8(0xf) /* Transmit FIFO Level */
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#define SSP_SSSR_TFL_BASE 8
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#define SSP_SSSR_ROR BIT_7 /* Receive FIFO Overrun */
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/* Receive FIFO Service Request */
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#define SSP_SSSR_RFS BIT_6
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/* Transmit FIFO Service Request */
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#define SSP_SSSR_TFS BIT_5
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#define SSP_SSSR_BSY BIT_4 /* SSP Busy */
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#define SSP_SSSR_RNE BIT_3 /* Receive FIFO Not Empty */
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#define SSP_SSSR_TNF BIT_2 /* Transmit FIFO Not Full */
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/* Bit(s) SSP_SSSR_RSRV_1_0 reserved */
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/* SSP_SSITR 0x000C SSP Interrupt Test Register */
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/* Bit(s) SSP_SSITR_RSRV_31_8 reserved */
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#define SSP_SSITR_TROR BIT_7 /* Test RXFIFO Overrun */
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/* Test RXFIFO Service Request */
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#define SSP_SSITR_TRFS BIT_6
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/* Test TXFIFO Service Request */
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#define SSP_SSITR_TTFS BIT_5
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/* Bit(s) SSP_SSITR_RSRV_4_0 reserved */
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/* SSP_SSDR 0x0010 SSP Data Register */
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#define SSP_SSDR_DATA_MSK SHIFT0(0xffffffff) /* DATA */
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#define SSP_SSDR_DATA_BASE 0
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/* */
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/* Bit(s) SSP_SSTO_RSRV_31_24 reserved */
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#define SSP_SSTO_TIMEOUT_MSK SHIFT0(0xffffff) /* Timeout Value */
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#define SSP_SSTO_TIMEOUT_BASE 0
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/* SSP_SSPSP 0x002C SSP Programmable Serial Protocol Register */
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/* Bit(s) SSP_SSPSP_RSRV_31 reserved */
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#define SSP_SSPSP_EDMYSTOP_MSK SHIFT28(0x7) /* Extended Dummy Stop */
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#define SSP_SSPSP_EDMYSTOP_BASE 28
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#define SSP_SSPSP_EDMYSTRT_MSK SHIFT26(0x3) /* Extended Dummy Start */
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#define SSP_SSPSP_EDMYSTRT_BASE 26
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/* Frame Sync Relative Timing Bit */
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#define SSP_SSPSP_FSRT BIT_25
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#define SSP_SSPSP_DMYSTOP_MSK SHIFT23(0x3) /* Dummy Stop */
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#define SSP_SSPSP_DMYSTOP_BASE 23
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/* Bit(s) SSP_SSPSP_RSRV_22 reserved */
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#define SSP_SSPSP_SFRMWDTH_MSK SHIFT16(0x3f) /* Serial Frame Width */
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#define SSP_SSPSP_SFRMWDTH_BASE 16
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#define SSP_SSPSP_SFRMDLY_MSK SHIFT9(0x7f) /* Serial Frame Delay */
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#define SSP_SSPSP_SFRMDLY_BASE 9
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#define SSP_SSPSP_DMYSTRT_MSK SHIFT7(0x3) /* Dummy Start */
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#define SSP_SSPSP_DMYSTRT_BASE 7
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#define SSP_SSPSP_STRTDLY_MSK SHIFT4(0x7) /* Start Delay */
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#define SSP_SSPSP_STRTDLY_BASE 4
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#define SSP_SSPSP_ETDS BIT_3 /* End Of Transfer Data State */
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#define SSP_SSPSP_SFRMP BIT_2 /* Serial Frame Polarity */
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#define SSP_SSPSP_SCMODE_MSK SHIFT0(0x3) /* Serial Bit-rate Clock Mode */
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#define SSP_SSPSP_SCMODE_BASE 0
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/* SSP_SSTSA 0x0030 SSP TX Time Slot Active Register */
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/* Bit(s) SSP_SSTSA_RSRV_31_8 reserved */
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#define SSP_SSTSA_TTSA_MSK SHIFT0(0xff) /* TX Time Slot Active */
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#define SSP_SSTSA_TTSA_BASE 0
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/* SSP_SSRSA 0x0034 SSP RX Time Slot Active Register */
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/* Bit(s) SSP_SSRSA_RSRV_31_8 reserved */
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#define SSP_SSRSA_RTSA_MSK SHIFT0(0xff) /* RX Time Slot Active */
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#define SSP_SSRSA_RTSA_BASE 0
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/* SSP_SSTSS 0x0038 SSP Time Slot Status Register */
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#define SSP_SSTSS_NMBSY BIT_31 /* Network Mode Busy */
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/* Bit(s) SSP_SSTSS_RSRV_30_3 reserved */
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#define SSP_SSTSS_TSS_MSK SHIFT0(0x7) /* Time Slot Status */
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#define SSP_SSTSS_TSS_BASE 0
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/* SSP_SSACD 0x003C SSP Audio Clock Divider Register */
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/* Bit(s) SSP_SSACD_RSRV_31_8 reserved */
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#define SSP_SSACD_SCDX8 BIT_7 /* SYSCLK Divided By 8 */
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/* Audio Clock PLL Select */
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#define SSP_SSACD_ACPS_MSK SHIFT4(0x7)
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#define SSP_SSACD_ACPS_BASE 4
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/* SYSCLK Divider Bypass */
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#define SSP_SSACD_SCDB BIT_3
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/* Audio Clock Divider Select */
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#define SSP_SSACD_ACDS_MSK SHIFT0(0x7)
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#define SSP_SSACD_ACDS_BASE 0
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/* SSP_SSACDD 0x0040 SSP Audio Clock Dither Divider Register */
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/* Bit(s) SSP_SSACDD_RSRV_31 reserved */
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#define SSP_SSACDD_NUM_MSK SHIFT16(0x7fff) /* Numerator */
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#define SSP_SSACDD_NUM_BASE 16
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/* Bit(s) SSP_SSACDD_RSRV_15_12 reserved */
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#define SSP_SSACDD_DEN_MSK SHIFT0(0xfff) /* Denominator */
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#define SSP_SSACDD_DEN_BASE 0
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/* DUMMY_REGISTER 0x0000 This is a Dummy Register */
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#define DUMMY_REGISTER_DUMMY_MSK SHIFT0(0xffffffff) /* Ignore this register */
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#define DUMMY_REGISTER_DUMMY_BASE 0
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/*
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*
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* THE REGISTER DEFINES
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*
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*/
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#define SSP_TOP_CTRL (0x0000)
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#define SSP_FIFO_CTRL (0x0004)
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#define SSP_INT_EN (0x0008)
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#define SSP_TIMEOUT (0x000C)
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#define SSP_DATAR (0x0010) /* 32 bit SSP Data Register */
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#define SSP_STATUS (0x0014)
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/*
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*
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* SSP Top Control Register
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*
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*/
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/* TXD Three-state Enable On Last Phase */
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#define SSP_TCR_TTELP BIT_18
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/* TXD Three-State Enable */
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#define SSP_TCR_TTE BIT_17
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/* Slave Clock Free Running */
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#define SSP_TCR_SCFR BIT_16
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/* Invert Frame Signal */
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#define SSP_TCR_IFS BIT_15
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/* Hold Frame Low Control */
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#define SSP_TCR_HFL BIT_14
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/* Trailing Byte */
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#define SSP_TCR_TRIAL BIT_13
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/* Loopback Mode */
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#define SSP_TCR_LBM BIT_12
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/* Motorola SPI SSPSCLK phase setting */
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#define SSP_TCR_SPH BIT_11
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/* Motorola SPI SSPSCLK Polarity Setting */
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#define SSP_TCR_SPO BIT_10
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/* Data Size Select */
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#define SSP_TCR_DSS_MASK SHIFT5(0x1f)
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#define SSP_TCR_DSS32 SHIFT5(0x1f)
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#define SSP_TCR_DSS24 SHIFT5(0x17)
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#define SSP_TCR_DSS16 SHIFT5(0xf)
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#define SSP_TCR_DSS8 SHIFT5(0x7)
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/* SSP Frame (SSPSFRMx) Direction */
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#define SSP_TCR_SFRMDIR BIT_4
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/* SSP Serial Bit Rate Clock (SSPSCLKx) Direction */
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#define SSP_TCR_SCLKDIR BIT_3
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#define SSP_TCR_FRF_MASK SHIFT1(0x3)
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/* Synchronous Serial Port Enable */
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#define SSP_TCR_SSE BIT_0
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/*
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*
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* SSP FIFO Control Register
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*
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*/
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/* Rx FIFO Auto Full Control */
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#define SSP_FCR_RAFC BIT_17
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/* apb_pwdata Write to Tx FIFO Endian */
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#define SSP_FCR_TWE_MASK SHIFT14(0x3)
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#define SSP_FCR_TWE(x) (x << 14)
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/* apb_prdata Read from Rx FIFO Endian */
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#define SSP_FCR_RRE_MASK SHIFT12(0x3)
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#define SSP_FCR_RRE(x) (x << 12)
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/* Receive Service Request Enable */
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#define SSP_FCR_RSRE BIT_11
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/* Transmit Service Request Enable */
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#define SSP_FCR_TSRE BIT_10
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/* RXFIFO Trigger Threshold */
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/* MaxBurstSize(DMA)/Data Size Select(SSP) - 1 */
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#define SSP_FCR_RFT_MASK SHIFT5(0x1f)
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#define SSP_FCR_RFT(x) (x << 5)
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/* TXFIFO Trigger Threshold */
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/* MaxBurstSize(DMA)/Data Size Select(SSP) - 1 */
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#define SSP_FCR_TFT_MASK SHIFT0(0x1f)
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#define SSP_FCR_TFT(x) (x << 0)
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/*
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*
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* SSP Interrupt Enable Register
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*
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*/
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/* Transmit FIFO Underrun Interrupt Mask */
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#define SSP_IER_TIM BIT_5
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/* Receive FIFO Overrun Interrupt Mask */
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#define SSP_IER_RIM BIT_4
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/* Transmit FIFO Interrupt Enable */
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#define SSP_IER_TIE BIT_3
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/* Receive FIFO Interrupt Enable */
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#define SSP_IER_RIE BIT_2
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/* Receiver Time-out Interrupt Enable */
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#define SSP_IER_RTOIE BIT_1
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/* -------------------- */
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#endif /* __INC_SSP_H */
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