200 lines
5.9 KiB
C
200 lines
5.9 KiB
C
#ifndef _SSP_HOST_H_
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#define _SSP_HOST_H_
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#include "NSSP.h"
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#include "APBCLK.h"
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//#include "timer_dec.h"
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//#include "cache_ops.h"
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//#include "gpio_dec.h"
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//#include "mfp-emei.h"
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#define SHIFT0(Val) (Val)
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#define SHIFT1(Val) ((Val) << 1)
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#define SHIFT2(Val) ((Val) << 2)
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#define SHIFT3(Val) ((Val) << 3)
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#define SHIFT4(Val) ((Val) << 4)
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#define SHIFT5(Val) ((Val) << 5)
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#define SHIFT6(Val) ((Val) << 6)
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#define SHIFT7(Val) ((Val) << 7)
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#define SHIFT8(Val) ((Val) << 8)
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#define SHIFT9(Val) ((Val) << 9)
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#define SHIFT10(Val) ((Val) << 10)
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#define SHIFT11(Val) ((Val) << 11)
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#define SHIFT12(Val) ((Val) << 12)
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#define SHIFT13(Val) ((Val) << 13)
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#define SHIFT14(Val) ((Val) << 14)
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#define SHIFT15(Val) ((Val) << 15)
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#define SHIFT16(Val) ((Val) << 16)
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#define SHIFT17(Val) ((Val) << 17)
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#define SHIFT18(Val) ((Val) << 18)
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#define SHIFT19(Val) ((Val) << 19)
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#define SHIFT20(Val) ((Val) << 20)
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#define SHIFT21(Val) ((Val) << 21)
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#define SHIFT22(Val) ((Val) << 22)
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#define SHIFT23(Val) ((Val) << 23)
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#define SHIFT24(Val) ((Val) << 24)
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#define SHIFT25(Val) ((Val) << 25)
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#define SHIFT26(Val) ((Val) << 26)
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#define SHIFT27(Val) ((Val) << 27)
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#define SHIFT28(Val) ((Val) << 28)
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#define SHIFT29(Val) ((Val) << 29)
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#define SHIFT30(Val) ((Val) << 30)
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#define SHIFT31(Val) ((Val) << 31)
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#define SSP_TIMEOUT_MAX (0x2000)
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#define SSP_RX_TIMEOUT (0x2000)
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#define SSP_CS (GPIO25)
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#define SSP_CR1_IE (SSP_SSCR1_TINTE|SSP_SSCR1_TIE|SSP_SSCR1_RIE)
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#define SSP_SR_CLR (SSP_SSSR_ROR|SSP_SSSR_TINT)
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#define SSP_XFER_BEGIN 0x01
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#define SSP_XFER_END 0x02
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#define SSP_XFER_BE 0x03
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#define SSP_DMA_TX_CHANNEL 6
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#ifdef SPI_MUX
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#define SSP_DMA_RX_CHANNEL 7
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#else
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#define SSP_DMA_RX_CHANNEL 20
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#endif
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#define SSP_CS_GPIO 13
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#define SSP_CS_GPIO_SLAVE 34
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#define SPI_DSS8 0x7
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#define SPI_DSS16 0xf
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#define SPI_DSS32 0x1f
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/* TXD Three-state Enable On Last Phase */
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#define SSP_TCR_TTELP BIT_18
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/* TXD Three-State Enable */
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#define SSP_TCR_TTE BIT_17
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/* Data Size Select */
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#define SSP_TCR_DSS_MASK SHIFT5(0x1f)
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#define SSP_TCR_DSS32 SHIFT5(0x1f)
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#define SSP_TCR_DSS24 SHIFT5(0x17)
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#define SSP_TCR_DSS16 SHIFT5(0xf)
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#define SSP_TCR_DDS8 SHIFT5(0x7)
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#define SSP_TCR_HFL SHIFT14(1);
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/* Transmit FIFO Underrun Interrupt Mask */
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#define SSP_IER_TIM BIT_5
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/* Receive FIFO Overrun Interrupt Mask */
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#define SSP_IER_RIM BIT_4
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#define SSP_TCR_INITIAL (SSP_TCR_TTELP | SSP_TCR_TTE | SSP_TCR_DDS8)
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#define SSP_FCR_INITIAL (SSP_FCR_TFT(0x1)|SSP_FCR_RFT(0x1))
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#define SSP_IER_INITIAL 0
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/* Rx FIFO Auto Full Control */
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#define SSP_FCR_RAFC BIT_17
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/* Receive Service Request Enable */
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#define SSP_FCR_RSRE BIT_11
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/* Transmit Service Request Enable */
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#define SSP_FCR_TSRE BIT_10
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#define SSP_FCR_RFT_MASK SHIFT5(0x1f)
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#define SSP_FCR_RFT(x) (x << 5)
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/* TXFIFO Trigger Threshold */
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/* MaxBurstSize(DMA)/Data Size Select(SSP) - 1 */
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#define SSP_FCR_TFT_MASK SHIFT0(0x1f)
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#define SSP_FCR_TFT(x) (x << 0)
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#define TOP_INIT_DATA8 0x000620E0
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#define TOP_INIT_DATA16 0x000621E0
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#define TOP_INIT_DATA32 0x000623E0
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#define FIFO_INIT 0x00000108
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#define FIFO_INIT_READ 0xCE7
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#define FIFO_INIT_WRITE 0x4E7
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#define INT_EN_INIT 0x30
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static SSP_TypeDef *ssp_ports[3] = {SSP0, SSP1, SSP2};
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#define ssp_port(x) ssp_ports[x]
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typedef enum{
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SSP_CLK_6_5M = 0,
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SSP_CLK_13M,
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SSP_CLK_26M,
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SSP_CLK_52M
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}SSP_CLOCK;
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typedef enum{
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SSP_DATA_LEN_8 = 0,
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SSP_DATA_LEN_16,
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SSP_DATA_LEN_18,
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SSP_DATA_LEN_32
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}SSP_DATA_LEN;
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typedef struct {
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unsigned int mode;
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unsigned int data_length;
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unsigned int speed;
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unsigned int tx_watermark;
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unsigned int rx_watermark;
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unsigned int fmt;
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unsigned int i2s_width;
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int irq;
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}ssp_init_param;
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#define SPI_CPHA 0x01 /* clock phase */
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#define SPI_CPOL 0x02 /* clock polarity */
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#define SPI_MODE_0 (0|0) /* (original MicroWire) */
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#define SPI_MODE_1 (0|SPI_CPHA)
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#define SPI_MODE_2 (SPI_CPOL|0)
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#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
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/*psp params*/
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#define SSP_SPI_MODE (0x0 << 1)
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#define SSP_SSP_MODE (0x1 << 1)
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#define SSP_PSP_MODE (0x3 << 1)
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#define SSP_ONCHIP_CLOCK (0x0 << 6)
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#define SSP_EXTER_CLOCK (0x1 << 6)
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#define SSP_DATA_16BIT 16
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#define SSP_DATA_8BIT 8
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#define SSP_DATA_32BIT 32
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#define SSP_DATA_18BIT 18
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extern unsigned int Endian_Convert (unsigned int in);
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extern int spi_wait_complete(int port);
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extern void spi_assert_cs(int port);
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extern void spi_deassert_cs(int port);
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#ifdef SPISD_SUPPORT
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int sd_spi_assert_clear(int port);
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void spi_rw_init_froSD(int port);
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void changeToWord(int port);
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void changeToWordDma(int port);
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void changeToByte(int port);
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void ssp_reg_printf(int port);
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void spi_xmit_config(int port, int tx_mode);
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void ssp_clk_cfg(int port, int clk);
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void ssp_pinmux_cfg(int port, uint32_t gpio_flag);
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void spi_cs_control(int i);
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void spi_disable_ssp(int port);
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void spi_xmit_start_forSD(int port);
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void spi_xmit_stop_forSD(int port);
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void spi_xmit_start(int port);
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unsigned char ssp_write_byte(int port, unsigned char data);
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void ssp_config_master(int port, int is_master);
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int ssp_write_word(int port, int data);
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int ssp_read_word(int port);
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int spi_wait_complete(int port);
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int spi_wait_complete_byte(int port);
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unsigned char ssp_read_byte(int port);
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void ssp_init_master(int port, int ssp_clk,int master);
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unsigned char ssp_write_read_bytes(int port,unsigned char *inbuf, unsigned char *outbuf, unsigned int len);
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#endif
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void spi_xmit_data(int port, uint32_t data);
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void spi_xmit_stop(int port);
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uint32_t spi_recv_data(int port);
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#endif
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