328 lines
12 KiB
C
328 lines
12 KiB
C
/*================================================================
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Copyright (c) 2021, Quectel Wireless Solutions Co., Ltd. All rights reserved.
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Quectel Wireless Solutions Proprietary and Confidential.
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=================================================================*/
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/**
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******************************************************************************
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* @file example_gpio.c
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* @author Juson.zhang
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* @version V1.0.0
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* @date 2019/01/02
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* @brief This file tests GPIO's APIs
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******************************************************************************
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*/
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#include <stdio.h>
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#include "ql_gpio.h"
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#include "ql_rtos.h"
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#include "ql_uart.h"
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#include "ql_application.h"
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#include "ql_type.h"
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//#include "global_types.h"
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#include "ql_func.h"
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//#define GPIO_UART_TEST
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#ifdef GPIO_UART_TEST//august add gpio test to uart
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#define QL_GPIO_TEST_PORT QL_USB_CDC_PORT
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static int i = 0;
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static int g_gpio = 0;
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static int g_eint = 0;
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static int c_flag = 1;
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static unsigned char uart_data[20] = {0};
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void gpio_irq_handler_test01(void)
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{
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int l=0;
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unsigned char buf[64] = {0};
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snprintf(buf, sizeof(buf)," eint test: %d \n",i++);
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ql_uart_write(QL_GPIO_TEST_PORT, buf, sizeof(buf));
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ql_eint_enable(g_gpio , g_eint);
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}
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int chnum(char p)
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{
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int num = 0;
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if(p>='0' && p<='9')
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num = p - '0';
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return num;
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}
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int read_direction(char p)
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{
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if(p == 'O' || p == 'o') return PIN_DIRECTION_OUT;
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else if(p == 'I' || p == 'i') return PIN_DIRECTION_IN;
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else return -1;
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}
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int read_pull(char p)
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{
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if(p == 'U' || p == 'u') return PIN_PULL_PU;
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else if(p == 'D' || p == 'd') return PIN_PULL_PD;
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else if(p == 'N' || p == 'n') return PIN_PULL_DISABLE;
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else return -1;
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}
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int read_level(char p)
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{
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if(p == 'H' || p == 'h') return PIN_LEVEL_HIGH;
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else if(p == 'L' || p == 'l') return PIN_LEVEL_LOW;
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else return -1;
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}
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int read_eint(char p)
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{
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if(p == 'N' || p == 'n') return PIN_NO_EDGE;
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else if(p == 'R' || p == 'r') return PIN_RISING_EDGE;
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else if(p == 'F' || p == 'f') return PIN_FALLING_EDGE;
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else if(p == 'B' || p == 'b') return PIN_BOTH_EDGE;
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else return -1;
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}
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void incorrect_command(void)
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{
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unsigned char buff[64] = {0};
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snprintf(buff, sizeof(buff)," Undefined command, please re-enter \r\n");
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ql_uart_write(QL_GPIO_TEST_PORT, buff, sizeof(buff));
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}
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void quec_gpio_uart_callback(QL_UART_PORT_NUMBER_E port, void *para)
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{
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c_flag = 2;
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memset(uart_data,0,sizeof(uart_data));
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ql_uart_read(port,uart_data, sizeof(uart_data));
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}
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static void quec_gpio_test(void * argv)
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{
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int ret = -1;
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int i = 0,j = 1;
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int gpio_num = 0;
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unsigned char level = 0;
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unsigned char buf[64] = {0};
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unsigned char data[] = "hello, please select gpio 0~127!!!\n";
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ret = ql_uart_open(QL_GPIO_TEST_PORT, QL_UART_BAUD_115200, QL_FC_NONE);
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if (ret) {
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printf("open uart[%d] failed! \n", QL_GPIO_TEST_PORT);
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return;
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}
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ql_uart_register_cb(QL_GPIO_TEST_PORT, quec_gpio_uart_callback); //use callback to read uart data
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ql_uart_write(QL_GPIO_TEST_PORT, data, sizeof(data));
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while(c_flag)
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{
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if(c_flag == 2)
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{
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for(i = 0;i < 15;i++)
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{
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if(uart_data[i] == '#')
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{
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gpio_num = chnum(uart_data[i+2])*100+chnum(uart_data[i+3])*10+chnum(uart_data[i+4]);
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j = 0;
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if(gpio_num > GPIO_PIN_NO_MAX){
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incorrect_command();
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break;
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}
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switch(uart_data[i+1])
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{
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//The format is set as:INIT GPIO OUT/IN PU/PD/N H/L
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case 'i':
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case 'I':
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ret = ql_gpio_init(gpio_num, read_direction(uart_data[i+5]), read_pull(uart_data[i+6]),read_level(uart_data[i+7]));
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if(ret < 0){
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memset(buf, 0, sizeof(buf));
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snprintf(buf, sizeof(buf), "gpio %d init filed \r\n",gpio_num);
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ql_uart_write(QL_GPIO_TEST_PORT,buf, sizeof(buf));
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break;
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}
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if((read_direction(uart_data[i+5])== -1) || (read_pull(uart_data[i+6])== -1) || (read_level(uart_data[i+7])== -1)){
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incorrect_command();
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break;
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}
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memset(buf, 0, sizeof(buf));
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snprintf(buf, sizeof(buf), "init gpio %d direction: %d pull: %d level: %d \r\n",gpio_num,
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read_direction(uart_data[i+5]),read_pull(uart_data[i+6]),read_level(uart_data[i+7]));
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ql_uart_write(QL_GPIO_TEST_PORT,buf, sizeof(buf));
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break;
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//The format is set as:GET GPIO LEVEL
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case 'g':
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case 'G':
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ql_gpio_get_level(gpio_num, &level);
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memset(buf, 0, sizeof(buf));
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snprintf(buf, sizeof(buf), " ==== get gpio %d level is %d ==== \n",gpio_num,level);
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ql_uart_write(QL_GPIO_TEST_PORT,buf, sizeof(buf));
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break;
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//The format is set as:SET GPIO H/L
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case 's':
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case 'S':
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ret = ql_gpio_set_level(gpio_num,read_level(uart_data[i+5]));
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if(ret == -1){
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memset(buf, 0, sizeof(buf));
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snprintf(buf, sizeof(buf)," gpio %d uninitialized \n",gpio_num);
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ql_uart_write(QL_GPIO_TEST_PORT, buf, sizeof(buf));
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break;
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}
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if(read_level(uart_data[i+5]) == -1){
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incorrect_command();
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break;
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}
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memset(buf, 0, sizeof(buf));
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snprintf(buf, sizeof(buf)," **** set gpio %d level is %d **** \n",gpio_num, read_level(uart_data[i+5]));
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ql_uart_write(QL_GPIO_TEST_PORT, buf, sizeof(buf));
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break;
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//The format is set as:EINT GPIO N/R/F/B
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case 'e':
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case 'E':
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if(read_eint(uart_data[i+5]) == -1){
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incorrect_command();
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break;
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}
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if(ql_eint_register((g_gpio = gpio_num),(g_eint = read_eint(uart_data[i+5])),PIN_PULL_PD, gpio_irq_handler_test01,NULL)) {
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memset(buf, 0, sizeof(buf));
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snprintf(buf, sizeof(buf),"eint register failed \n");
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ql_uart_write(QL_GPIO_TEST_PORT, buf, sizeof(buf));
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break;
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}
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ql_eint_enable(gpio_num, read_eint(uart_data[i+5]));
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memset(buf, 0, sizeof(buf));
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snprintf(buf, sizeof(buf)," eint gpio %d way is %d \r\n",gpio_num, read_eint(uart_data[i+5]));
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ql_uart_write(QL_GPIO_TEST_PORT, buf, sizeof(buf));
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break;
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default: incorrect_command();break;
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}
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}
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}
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if(j) incorrect_command();
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else j = 1;
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c_flag = 1;
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}
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ql_rtos_task_sleep_ms(500);
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}
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}
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#else
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#define test_log(fmt, args...) printf(fmt, ##args)
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#ifndef QUEC_ARR_SIZE
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#define QUEC_ARR_SIZE(a) ( sizeof(a) / sizeof(a[0]) )
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#endif
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static quec_gpio_cfg_t __quec_gpio_cfg[] =
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{
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{GPIO_PIN_NO_31, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_32, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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#if 0
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{GPIO_PIN_NO_0, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_1, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_10, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_11, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_33, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_34, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_35, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_36, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_16, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_17, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_18, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_19, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_49, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_50, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_85, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_121, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_122, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_124, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_8, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_9, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_20, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_21, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_22, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_24, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_25, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_26, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_71, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_74, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_78, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_77, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_76, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_75, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_72, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_73, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_81, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_82, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_37, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_38, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_39, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_40, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_41, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_42, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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{GPIO_PIN_NO_43, PIN_DIRECTION_OUT, PIN_NO_EDGE, PIN_PULL_DISABLE, PIN_LEVEL_LOW},
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#endif
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};
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static QlOSStatus __quec_gpio_cust_config(void)
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{
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int i=0;
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for(i=0; i<QUEC_ARR_SIZE(__quec_gpio_cfg) ; i++)
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{
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ql_gpio_init(__quec_gpio_cfg[i].gpio_pin_num, __quec_gpio_cfg[i].pin_dir, __quec_gpio_cfg[i].pin_pull, __quec_gpio_cfg[i].pin_level);
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}
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return 0;
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}
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static void quec_gpio_test(void * argv)
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{
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int i = 0, j = 0;
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unsigned char level = 0;
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__quec_gpio_cust_config();
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ql_rtos_task_sleep_s(1);
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while(1) {
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j++;
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test_log("quec_gpio_test_task, id:%d \n", j);
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for(i=0; i<QUEC_ARR_SIZE(__quec_gpio_cfg) ; i++) {
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ql_gpio_set_level(__quec_gpio_cfg[i].gpio_pin_num, PIN_LEVEL_LOW);
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test_log("===Set gpio[%d] level is %d=== \n", __quec_gpio_cfg[i].gpio_pin_num, PIN_LEVEL_LOW);
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}
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ql_rtos_task_sleep_s(3);
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for(i=0; i<QUEC_ARR_SIZE(__quec_gpio_cfg) ; i++) {
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ql_gpio_get_level(__quec_gpio_cfg[i].gpio_pin_num, &level);
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test_log("***Get gpio[%d] level is %d*** \n", __quec_gpio_cfg[i].gpio_pin_num, level);
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}
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ql_rtos_task_sleep_s(3);
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for(i=0; i<QUEC_ARR_SIZE(__quec_gpio_cfg) ; i++) {
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ql_gpio_set_level(__quec_gpio_cfg[i].gpio_pin_num, PIN_LEVEL_HIGH);
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test_log("===Set gpio[%d] level is %d=== \n", __quec_gpio_cfg[i].gpio_pin_num, PIN_LEVEL_HIGH);
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}
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ql_rtos_task_sleep_s(3);
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for(i=0; i<QUEC_ARR_SIZE(__quec_gpio_cfg) ; i++) {
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ql_gpio_get_level(__quec_gpio_cfg[i].gpio_pin_num, &level);
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test_log("***Get gpio[%d] level is %d*** \n", __quec_gpio_cfg[i].gpio_pin_num, level);
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}
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ql_rtos_task_sleep_s(3);
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break;
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}
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}
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#endif
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//application_init(quec_gpio_test, "quec_gpio_test", 2, 0);
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