590 lines
21 KiB
C
590 lines
21 KiB
C
/*--------------------------------------------------------------------------------------------------------------------
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(C) Copyright 2006, 2007 Marvell DSPC Ltd. All Rights Reserved.
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-------------------------------------------------------------------------------------------------------------------*/
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/*********************************************************************
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* M O D U L E B O D Y *
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**********************************************************************
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* Title: Direct Memory Access - DMA *
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* *
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* Filename: dma.h *
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* *
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* Target, platform: Tavor project, Arbel platform *
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* *
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* Author: Olga Fomenko *
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* *
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* Description: This is the header file of DMA SW packet, includes *
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* all API and user definitions *
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* Notes: *
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**********************************************************************/
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#ifndef _DMA_HW_
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#define _DMA_HW_
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#include "dma_hw.h"
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#include "dma_hw_connectivity.h"
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// to compile this module for release version - comment this define
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//#define DMA_DEBUG
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#define DMA_CHANNEL_ICAT_RX DMA_CHANNEL_14
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#define DMA_CHANNEL_ICAT_TX DMA_CHANNEL_21
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#define DMA_CHANNEL_HSDPA DMA_CHANNEL_8
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typedef enum
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{
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DMA_BYTE_TSZ = 1,
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DMA_WORD_TSZ = 2,
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DMA_DWORD_TSZ = 4,
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DMA_QWORD_TSZ = 8
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}DMA_TransferSizeE;
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typedef enum
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{
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DMA_INC_BY_TSZ = 0,
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DMA_DEC_BY_TSZ = 1,
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DMA_NO_CHANGE = 2
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}DMA_AddrPostModifierE;
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typedef enum
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{
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DMA_A2B = 0,
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DMA_B2A
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}DMA_PortDirectionConnectionE;
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typedef struct
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{
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UINT32 packetLength;
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DMA_TransferSizeE transferSize;
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UINT8 interruptsEnableBits;
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DMA_AddrPostModifierE srcPostMod;
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DMA_AddrPostModifierE dstPostMod;
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DMA_PortDirectionConnectionE portConnection;
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}DMA_SingleDescriptorS;
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typedef struct
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{
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UINT32 packetLength;
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DMA_TransferSizeE transferSize;
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//UINT8 interruptsEnableBits;
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DMA_AddrPostModifierE srcPostMod;
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DMA_AddrPostModifierE dstPostMod;
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DMA_PortDirectionConnectionE portConnection;
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void* srcAddr;
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void* dstAddr;
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UINT32 numberOfPackets;
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}DMA_ChainElementDescriptorS;
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typedef enum
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{
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DMA_CHAIN_CYCLIC_MEM2MEM = 0,
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DMA_CHAIN_CYCLIC_MEM2PER,
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DMA_FINITE_CHAIN_MEM2MEM,
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DMA_FINITE_CHAIN_MEM2PER
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}DMA_ChainTypeE;
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#define DMA_IS_MEMORY_ONLY_TRANSACTION(type) ((type==DMA_CHAIN_CYCLIC_MEM2MEM)|| \
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(type==DMA_FINITE_CHAIN_MEM2MEM))
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typedef struct
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{
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DMA_ChainElementDescriptorS* pChainDescArray;
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UINT32 numDescs;
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UINT32 currentDesc;
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DMA_ChainTypeE chainType;
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}DMA_ChainDescriptorS;
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typedef enum
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{
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DMA_GSSP1_Rx = 0,
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DMA_GSSP1_Tx,
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DMA_GSSP2_Rx,
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DMA_GSSP2_Tx,
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DMA_DSSP3_Rx,
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DMA_DSSP3_Tx
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}DMA_PeripheralsE;
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//--------- Notification Functions
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typedef void (*DMATransferErrorNotifyFn)(UINT32 channel, UINT32 callbackCookie);
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typedef void (*DMATransferEndedNotifyFn)(UINT32 channel, UINT32 callbackCookie);
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typedef void (*DMATransferStoppedNotifyFn)(UINT32 channel, UINT32 callbackCookie);
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typedef enum
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{
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DMA_RC_CHANNEL_IS_BUSY=-5,
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DMA_RC_OK = 1,
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DMA_RC_CHANNAL_INVALID ,
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DMA_RC_CHANNEL_NOT_CLOSED,
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DMA_RC_CHANNEL_NOT_OPEN,
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DMA_RC_ADDRESS_NOT_ALIGNED,
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DMA_RC_ILLEGAL_ADDRESS,
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DMA_RC_SIZE_ERROR,
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DMA_RC_CHANNEL_NOT_AVAILABLE ,
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DMA_RC_CHANNEL_NOT_STOPPED,
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DMA_RC_INTC_BIND_ERROR,
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DMA_RC_INTC_INTERRUPT_ERROR,
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DMA_RC_MUX_CONNECTION_ILLEGAL,
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DMA_RC_CHANNEL_MATRIXED_VALUE_ERROR,
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DMA_RC_CHANNEL_DATA_ERROR,
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DMA_RC_CHANNEL_OVERFLOW_ERROR,
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DMA_RC_MAPPING_INVALID,
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DMA_RC_ILLEGAL_PARAMETERS,
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DMA_RC_BUFFER_ERROR,
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DMA_RC_RM_ERROR
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}DMA_ReturnCode;
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///////////////////////////////////////////////////////////////////////////////////
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// API - DMA SW package 1 function declaration
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///////////////////////////////////////////////////////////////////////////////////
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//--------- System Control Services -----------------------------------------------
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void DMAPhase1Init (void);
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DMA_ReturnCode DMAPhase2Init (void);
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//--------- Channel Control Services ----------------------------------------------
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DMA_ReturnCode DMAChannelOpen (DMA_ChannelE channel);
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DMA_ReturnCode DMAChannelRegister (DMA_ChannelE channel,
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DMATransferEndedNotifyFn endNotifyFn,
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DMATransferStoppedNotifyFn stopNotifyFn,
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DMATransferErrorNotifyFn errorNotifyFn,
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UINT32 callbackCookie);
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DMA_ReturnCode DMAChannelConfigure (DMA_ChannelE channel,
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DMA_DREQConnectionE dreqConnection,
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DMA_MUXConnectionE muxConnection);
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//#define DMAChannelStart(channel) {DmaHwRegisters.controller[DMA_GET_CONTROLLER_NUMBER(channel)].DCR |= ( DMA_CHANNEL_START_BIT >> DMA_GET_CHANNEL_PHYSICAL_NUMBER(channel) );}
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void DMAChannelStart (DMA_ChannelE channel);
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//#define DMAChannelTerminate(channel){DmaHwRegisters.controller[DMA_GET_CONTROLLER_NUMBER(channel)].DCR |= ( DMA_CHANNEL_TERMINATE_BIT >> DMA_GET_CHANNEL_PHYSICAL_NUMBER(channel) );}
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void DMAChannelTerminate (DMA_ChannelE channel);
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DMA_ReturnCode DMAChannelClose (DMA_ChannelE channel);
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void DMAChannelStop (DMA_ChannelE channel, BOOL waitForStop);
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#define DMAIsChannelRunning(channel)(DmaHwRegisters.controller[DMA_GET_CONTROLLER_NUMBER(channel)].DCR & (DMA_CHANNEL_START_BIT>>DMA_GET_CHANNEL_PHYSICAL_NUMBER(channel)) ) // TBD - check out :idle -?
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//--------- Single Transfer Setup Services
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DMA_ReturnCode DMAMemory2MemorySetup (DMA_ChannelE channel,
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void *srcAddr,
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void *dstAddr,
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UINT32 length,
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DMA_SingleDescriptorS *pSingleDescriptor);
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DMA_ReturnCode DMAPeripheral2MemorySetup (DMA_ChannelE channel,
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void *srcAddr,
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void *dstAddr,
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UINT32 length,
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DMA_SingleDescriptorS *pSingleDescriptor);
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DMA_ReturnCode DMAPeripheral2AlignedMemorySetup (DMA_ChannelE channel,
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void *srcAddr,
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void *dstAddr,
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UINT32 length,
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const DMA_SingleDescriptorS *pSingleDescriptor);
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DMA_ReturnCode DMAMemory2PeripheralSetup (DMA_ChannelE channel,
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void *srcAddr,
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void *dstAddr,
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UINT32 length,
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DMA_SingleDescriptorS *pSingleDescriptor,
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void* pChainManagerPool,
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UINT32 sizeOfChainManagerPool);
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DMA_ReturnCode DMAAlignedMemory2PeripheralSetup (DMA_ChannelE channel,
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void *srcAddr,
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void *dstAddr,
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UINT32 length,
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const DMA_SingleDescriptorS *pSingleDescriptor,
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void* pChainManagerPool,
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UINT32 sizeOfChainManagerPool);
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DMA_ReturnCode DMASingleDescriptorSetup (DMA_ChannelE channel,
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DMA_SingleDescriptorS *pSingleDesc,
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UINT8 descNumber,
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UINT32 numberOfPackets,
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void *srcAddr,
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void *dstAddr);
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// secondaryAPI
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UINT8 DMAGetInterruptVector (BOOL error_,
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BOOL ended,
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BOOL stop);
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UINT32 DMAGetRequiredSizeOfBuffer(UINT32 numberOfDescInChain);
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UINT32 DMAGetRemainder(DMA_ChannelE channel);
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///////////////////////////////////////////////////////////////////////////////////
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// API supports chaining mode
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///////////////////////////////////////////////////////////////////////////////////
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// Fill up the descriptors list - "automatic"
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DMA_ReturnCode DMADescriptorsChainSetup(DMA_ChannelE channel,
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void *srcBaseAddr,
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void *dstBaseAddr,
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UINT32 entireLength,
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DMA_SingleDescriptorS *pSingleDesc);
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DMA_ReturnCode DMAOneDescInChainSetup(DMA_ChannelE channel,
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DMA_SingleDescriptorS* pSingleDesc,
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UINT32 descIndex,
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void* srcAddr,
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void* dstAddr,
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UINT32 singleTransactionLength);
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// Prepare a "link-list" (chaining) of descriptors
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DMA_ReturnCode DMADescriptorsChainPrepare(DMA_ChannelE channel,
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UINT32 numDescriptors,
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void *descBuffer,
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UINT32 descBufferSize,
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DMA_ChainTypeE chainType);
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///////////////////////////////////////////////////////////////////////////////////
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// this definition is temporary - only for first stage integration with SSP
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///////////////////////////////////////////////////////////////////////////////////
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#if 1
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typedef enum
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{
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DMA_CSSP0_TX , DMA_CSSP0_RX ,
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DMA_CSSP1_TX , DMA_CSSP1_RX
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}DMA_Peripherals;
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typedef enum
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{
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DMA_ADDRESS_INCREMENT_NONE = 0,
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DMA_ADDRESS_INCREMENT_SOURCE,
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DMA_ADDRESS_INCREMENT_TARGET,
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DMA_ADDRESS_INCREMENT_BOTH
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}DMA_AddressIncrement;
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typedef struct
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{
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UINT16 packetSize;
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DMA_AddressIncrement bufferIncrement;
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UINT32 totalLength;
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BOOL stopInterruptEnable;
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}DMA_ChainConfig;
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typedef enum
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{
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DMA_FLOW_CONTROL_NONE = 0,
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DMA_FLOW_CONTROL_SOURCE,
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DMA_FLOW_CONTROL_TARGET
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}DMA_FlowControl;
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typedef enum
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{
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DMA_LITTLE_ENDIAN = 0, /* the usually used */
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DMA_BIG_ENDIAN
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}DMA_ByteOrdering;
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typedef enum
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{
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DMA_BURST_INVALID = 0,
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DMA_BURST_8_BYTES,
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DMA_BURST_16_BYTES,
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DMA_BURST_32_BYTES
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}DMA_BurstSize;
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typedef enum
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{
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DMA_MEMORY_WIDTH = 0,
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DMA_DATA_WIDTH_ONE_BYTE,
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DMA_DATA_WIDTH_TWO_BYTES,
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DMA_DATA_WIDTH_FOUR_BYTES
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}DMA_DataWidth;
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typedef struct
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{
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UINT32 interruptsEnableBits;
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DMA_AddressIncrement addressIncrement;
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DMA_FlowControl flowControl;
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DMA_ByteOrdering byteOrdering;
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DMA_BurstSize burstSize;
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DMA_DataWidth dataWidth;
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}DMA_DescriptorsHWConfig;
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typedef struct
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{
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UINT32 interruptsEnableBits;
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BOOL peripheralAddrIncrement; // Increment address of peripheral
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BOOL peripheralFlow; // Peripheral Flow Control TRUE/FALSE
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DMA_ByteOrdering byteOrdering;
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DMA_BurstSize burstSize;
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DMA_DataWidth dataWidth;
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}DMA_SingleHWConfig;
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#define DMA_INTERRUPT_NONE 0x00L
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#define DMA_INTERRUPT_TRANSFER_STARTED 0x01L
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#define DMA_INTERRUPT_TRANSFER_ENDED 0x02L
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#define DMA_INTERRUPT_TRANSFER_STOPPED 0x04L
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#endif /*if 1*/
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/*
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*
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* THE BASE ADDRESSES
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*
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*/
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#ifdef NEZHA3_1826
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#define DMA_BASE 0xD0200000 //CP DMA Base
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#else
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#define DMA_BASE 0xD4000000 //AP DMA Base
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#endif
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/*
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*
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* THE REGISTER DEFINES
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*
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*/
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#define DMA_CSR031 (DMA_BASE+0x0000) /* DMA Channel Control/Status
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* Registers 0-31 Start
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*/
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#define DMA_ALGN (DMA_BASE+0x00A0) /* 32 bit DMA Alignment Register */
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#define DMA_PCSR (DMA_BASE+0x00A4) /* 32 bit DMA Programmed I/O
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* Control Status
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* Register
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*/
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#define DMA_RQSR0 (DMA_BASE+0x00E0) /* 32 bit DREQ Status Register 0 */
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#define DMA_INT (DMA_BASE+0x00F0) /* 32 bit DMA Interrupt Register */
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#define DMA_RCMRX (DMA_BASE+0x0100) /* DMA Request to Channel Map
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* Registers 0-63 and
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* 64-99 Start
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*/
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#define DMA_DADRX (DMA_BASE+0x0200) /* DMA Descriptor Address Registers Start */
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#define DMA_SADRX (DMA_BASE+0x0204) /* DMA Source Address Registers 0-31
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* Start
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*/
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#define DMA_TADRX (DMA_BASE+0x0208) /* DMA Target Address Registers 0-31
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* Start
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*/
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#define DMA_CMDX (DMA_BASE+0x020C) /* DMA Command Registers 0-31 Start */
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//#define DUMMY_REGISTER (DMA_BASE+0x0000) /* 32 bit This is a Dummy Register */
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/*
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*
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* THE BIT DEFINES
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*
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*/
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/* DMA_CSR031 0x0000 DMA Channel Control/Status Registers 0-31 */
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#define DMA_CSR031_RUN BIT_31 /* Run */
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#define DMA_CSR031_NODESCFETCH BIT_30 /* No-Descriptor Fetch */
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#define DMA_CSR031_STOPIRQEN BIT_29 /* Stop interrupt enabled */
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/* Setting the End-of-Receive interrupt enable */
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#define DMA_CSR031_EORIRQEN BIT_28
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/* Jump to the next descriptor on EOR */
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#define DMA_CSR031_EORJMPEN BIT_27
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#define DMA_CSR031_EORSTOPEN BIT_26 /* Stop channel on EOR */
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/* Set descriptor compare status */
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#define DMA_CSR031_SETCMPST BIT_25
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/* Clear descriptor compare status */
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#define DMA_CSR031_CLRCMPST BIT_24
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/* Request after channel stopped interrupt enable */
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#define DMA_CSR031_RASIRQEN BIT_23
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#define DMA_CSR031_MASKRUN BIT_22 /* MASKRUN */
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/* Bit(s) DMA_CSR031_RSRV_21_11 reserved */
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/* Descriptor compare status */
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#define DMA_CSR031_CMPST BIT_10
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#define DMA_CSR031_EORINT BIT_9 /* End of Receive Interrupt */
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#define DMA_CSR031_REQPEND BIT_8 /* Request pending */
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/* Bit(s) DMA_CSR031_RSRV_7_5 reserved */
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/* Request after channel stopped */
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#define DMA_CSR031_RASINTR BIT_4
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#define DMA_CSR031_STOPINTR BIT_3 /* Stop interrupt */
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#define DMA_CSR031_ENDINTR BIT_2 /* End interrupt */
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#define DMA_CSR031_STARTINTR BIT_1 /* Start interrupt */
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#define DMA_CSR031_BUSERRINTR BIT_0 /* Bus error interrupt */
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/* DMA_ALGN 0x00A0 DMA Alignment Register */
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/* Alignment control for channel x */
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#define DMA_ALGN_DALGNX_MSK SHIFT0(0xffffffff)
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#define DMA_ALGN_DALGNX_BASE 0
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/* DMA_PCSR 0x00A4 DMA Programmed I/O Control Status Register */
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/* Activate posted writes and split reads */
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#define DMA_PCSR_BRGSPLIT BIT_31
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/* Bit(s) DMA_PCSR_RSRV_30_1 reserved */
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#define DMA_PCSR_BRGBUSY BIT_0 /* Bridge busy status */
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/* DMA_RQSR0 0x00E0 DREQ Status Register 0 */
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/* Bit(s) DMA_RQSR0_RSRV_31_9 reserved */
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/* Clearing pending request */
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#define DMA_RQSR0_CLR BIT_8
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/* Bit(s) DMA_RQSR0_RSRV_7_5 reserved */
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#define DMA_RQSR0_REQPEND_MSK SHIFT0(0x1f) /* Request pending */
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#define DMA_RQSR0_REQPEND_BASE 0
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/* DMA_INT 0x00F0 DMA Interrupt Register */
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#define DMA_INT_CHLINTRX_MSK SHIFT0(0xffffffff) /* Channel interrupt */
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#define DMA_INT_CHLINTRX_BASE 0
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/* DMA_RCMRx 0x0100 DMA Request to Channel Map Registers 0-63 and 64-99 */
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/* Bit(s) DMA_RCMRX_RSRV_31_8 reserved */
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#define DMA_RCMRX_MAPVLD BIT_7 /* Map valid channel */
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/* Bit(s) DMA_RCMRX_RSRV_6_5 reserved */
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#define DMA_RCMRX_CHLNUM_MSK SHIFT0(0x1f) /* Channel number */
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#define DMA_RCMRX_CHLNUM_BASE 0
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/* DMA_DADRx 0x0200 DMA Descriptor Address Registers */
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/* Descriptor address */
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#define DMA_DADRX_DESCRIPTOR_ADDRESS_MSK SHIFT4(0xfffffff)
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#define DMA_DADRX_DESCRIPTOR_ADDRESS_BASE 4
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/* Bit(s) DMA_DADRX_RSRV_3_2 reserved */
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/* Enable Descriptor Branch */
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#define DMA_DADRX_BREN BIT_1
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#define DMA_DADRX_STOP BIT_0 /* Stop */
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/* DMA_SADRx 0x0204 DMA Source Address Registers 0-31 */
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#define DMA_SADRX_SRCADDR_MSK SHIFT3(0x1fffffff) /* Source address */
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#define DMA_SADRX_SRCADDR_BASE 3
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#define DMA_SADRX_SRCADDR2 BIT_2 /* SRCADDR2 */
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#define DMA_SADRX_SRCADDR0_MSK SHIFT0(0x3) /* SRCADDR0 */
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#define DMA_SADRX_SRCADDR0_BASE 0
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/* DMA_TADRx 0x0208 DMA Target Address Registers 0-31 */
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#define DMA_TADRX_TRGADDR_MSK SHIFT3(0x1fffffff) /* Target address */
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#define DMA_TADRX_TRGADDR_BASE 3
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#define DMA_TADRX_TRGADDR2 BIT_2 /* TRGADDR2 */
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#define DMA_TADRX_TRGADDR0_MSK SHIFT0(0x3) /* TRGADDR0 */
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#define DMA_TADRX_TRGADDR0_BASE 0
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/* DMA_CMDx 0x020C DMA Command Registers 0-31 */
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#define DMA_CMDX_INCSRCADDR BIT_31 /* Source address increment */
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#define DMA_CMDX_INCTRGADDR BIT_30 /* Target address increment */
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#define DMA_CMDX_FLOWSRC BIT_29 /* Source flow control */
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#define DMA_CMDX_FLOWTRG BIT_28 /* Target flow control */
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/* Bit(s) DMA_CMDX_RSRV_27_26 reserved */
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/* Descriptor compare enable */
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#define DMA_CMDX_CMPEN BIT_25
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/* Bit(s) DMA_CMDX_RSRV_24 reserved */
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#define DMA_CMDX_ADDRMODE BIT_23 /* ADDRMODE */
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#define DMA_CMDX_STARTIRQEN BIT_22 /* STARTIRQEN */
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#define DMA_CMDX_ENDIRQEN BIT_21 /* End interrupt enable */
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/* Bit(s) DMA_CMDX_RSRV_20_18 reserved */
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#define DMA_CMDX_SIZE_MSK SHIFT16(0x3) /* Maximum burst size */
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#define DMA_CMDX_SIZE_BASE 16
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#define DMA_CMDX_WIDTH_MSK SHIFT14(0x3) /* WIDTH */
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#define DMA_CMDX_WIDTH_BASE 14
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/* Bit(s) DMA_CMDX_RSRV_13 reserved */
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/* Length of the transfer in bytes */
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#define DMA_CMDX_LEN_MSK SHIFT0(0x1fff)
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#define DMA_CMDX_LEN_BASE 0
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/* DUMMY_REGISTER 0x0000 This is a Dummy Register */
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#define DUMMY_REGISTER_DUMMY_MSK SHIFT0(0xffffffff) /* Ignore this register */
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#define DUMMY_REGISTER_DUMMY_BASE 0
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typedef enum{
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DMA_REQ_CLK = 1,
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DMA_REQ_GSSP_RX = 3,
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DMA_REQ_UART2_RX = 4,
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DMA_REQ_UART2_TX = 5,
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DMA_REQ_USIM1_RX = 8,
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DMA_REQ_USIM1_TX = 9,
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DMA_REQ_USIM2_RX = 10,
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DMA_REQ_USIM2_TX = 11,
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DMA_REQ_APB_E_Cipher = 12,
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DMA_REQ_UART1_RX = 21,
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DMA_REQ_UART1_TX = 22,
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DMA_REQ_UART3_RX = 23,
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DMA_REQ_UART3_TX = 24,
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DMA_REQ_I2C0_TX = 25,
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DMA_REQ_I2C0_RX = 26,
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DMA_REQ_I2C1_TX = 27,
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DMA_REQ_I2C1_RX = 28,
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DMA_REQ_PWR_I2C_TX = 30,
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DMA_REQ_PWR_I2C_RX = 31,
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DMA_REQ_I2C2_TX = 32,
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DMA_REQ_I2C2_RX = 33,
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DMA_REQ_UART4_RX = 36,
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DMA_REQ_UART4_TX = 37,
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DMA_REQ_SSP0_RX = 52,
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DMA_REQ_SSP0_TX = 53,
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DMA_REQ_SSP1_RX = 54,
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DMA_REQ_SSP1_TX = 55,
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DMA_REQ_SSP2_RX = 60,
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DMA_REQ_SSP2_TX = 61,
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DMA_REQ_AEU_READ_CHANNEL = 68,
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DMA_REQ_AUE_WRITE_CHANNEL = 69,
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DMA_REQ_QSPI_RX = 97,
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DMA_REQ_QSPI_TX = 99,
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DMA_REQ_MEM2MEM_MOVE = 255 // RESERVED for Memory to Memory moves
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}DMA_MAP_DEVICE;
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typedef enum
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{
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DMAC_GSSP_RX = DMA_REQ_GSSP_RX,//3,
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// DMAC_GSSP_TX = DMA_REQ_UART2_RX,//4,
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DMAC_UART2_RX = DMA_REQ_UART2_RX,//4,
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DMAC_UART2_TX = DMA_REQ_UART2_TX,//5,
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DMAC_USIM1_RX = DMA_REQ_USIM1_RX,//8,
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DMAC_USIM1_TX = DMA_REQ_USIM1_TX,//9,
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DMAC_USIM2_RX = DMA_REQ_USIM2_RX,//10,
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DMAC_USIM2_TX = DMA_REQ_USIM2_TX,//11,
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DMAC_APB_E_Cipher = DMA_REQ_APB_E_Cipher,//12,
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DMAC_UART1_RX = DMA_REQ_UART1_RX,//21,
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DMAC_UART1_TX = DMA_REQ_UART1_TX,//22,
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DMAC_UART3_RX = DMA_REQ_UART3_RX,//23,
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DMAC_UART3_TX = DMA_REQ_UART3_TX,//24,
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DMAC_UART4_RX = DMA_REQ_UART4_RX,//36,
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DMAC_UART4_TX = DMA_REQ_UART4_TX,//37,
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DMAC_SSP_0_RX = DMA_REQ_SSP0_RX,//52,
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DMAC_SSP_0_TX = DMA_REQ_SSP0_TX,//53,
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DMAC_SSP_1_RX = DMA_REQ_SSP1_RX,//54,
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DMAC_SSP_1_TX = DMA_REQ_SSP1_TX,//55,
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DMAC_SSP_2_RX = DMA_REQ_SSP2_RX,//60,
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DMAC_SSP_2_TX = DMA_REQ_SSP2_TX,//61,
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DMAC_NAND_DATA = DMA_REQ_QSPI_RX,//97,
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DMAC_NAND_CMD = DMA_REQ_QSPI_TX,//99,
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DMAC_MEM2MEM_MOVE = DMA_REQ_MEM2MEM_MOVE //255 // RESERVED for Memory to Memory moves
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}DMAC_DRCMR_T, DMAC_DEVICE_T;
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/* -------------------- */
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#endif //_DMA_HW_
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