64 lines
2.8 KiB
C
64 lines
2.8 KiB
C
/*------------------------------------------------------------
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(C) Copyright [2006-2008] Marvell International Ltd.
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All Rights Reserved
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------------------------------------------------------------*/
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/*--------------------------------------------------------------------------------------------------------------------
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INTEL CONFIDENTIAL
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Copyright 2006 Intel Corporation All Rights Reserved.
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The source code contained or described herein and all documents related to the source code ("Material") are owned
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by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or
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its suppliers and licensors. The Material contains trade secrets and proprietary and confidential information of
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Intel or its suppliers and licensors. The Material is protected by worldwide copyright and trade secret laws and
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treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted,
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transmitted, distributed, or disclosed in any way without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual property right is granted to or
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conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement,
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estoppel or otherwise. Any license under such intellectual property rights must be express and approved by
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Intel in writing.
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-------------------------------------------------------------------------------------------------------------------*/
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#ifndef _DSP_BOOT_H_
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#define _DSP_BOOT_H_
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#include "bsp_config.h"
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/* DSP boot defines/macros*/
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#if defined(MSA_INIT)
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#if defined(TTC_DSP_INIT)
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/* DSP start address for TTC is configurable through COEL_APB_MSA_BOOT */
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#define DSP_BOOT_ADDRESS_REG 0xD4070000
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#define DSP_L2_SRAM_ADDRESS 0xd1e00000
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//#define msaCode
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/* DSP DDR address reference */
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#define DSP_DDR_ADDRESS 0xd0000000
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/* reserved start DDR address for DSP scatter file*/
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extern void Image$$DDR_DSP_RO$$Base;/* Exec Address of DSP RO region */
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extern void Image$$DDR_DSP_RO$$ZI$$Limit;/* Exec Address of DSP RO region */
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#if defined (DSP_BOOT_FROM_DDR)
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#define DSP_START_ADDRESS ((UINT32)&Image$$DDR_DSP_RO$$Base) | DSP_DDR_ADDRESS
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#else
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#define DSP_DDR_IMAGE_DSP_INIT_SIZE 0x50000 /* 320K */
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#define DSP_DDR_IMAGE_START_ADDR (UINT32)&Image$$DDR_DSP_RO$$Base
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#define DSP_DDR_IMAGE_END_ADDR (DSP_DDR_IMAGE_START_ADDR + DSP_DDR_IMAGE_DSP_INIT_SIZE)
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#define DSP_START_ADDRESS 0xd1e4c400 // was 0xd1e44c00
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#endif
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#else /*Hermon*/
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#define DSP_START_ADDRESS (bspMsaRunFromExternal()? XSCALE_SRAM : MSA_FLASH_BASE)
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#define DSP_BOOT_ADDRESS_REG 0x42900078
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#endif /* TTC_DSP_INIT */
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#else /* APPS / Arbel */
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#undef DSP_BOOT_ADDRESS_REG
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#endif /*MSA_INIT*/
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/*DSP boot API function*/
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void MSAPhase1Init(void);
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#endif /*_DSP_BOOT_H_*/
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