425 lines
17 KiB
C
425 lines
17 KiB
C
/*------------------------------------------------------------
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(C) Copyright [2006-2008] Marvell International Ltd.
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All Rights Reserved
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------------------------------------------------------------*/
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/************************************************************************/
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/* COPYRIGHT (C) 2002 Intel Corporation. */
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/* */
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/* This file and the software in it is furnished under */
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/* license and may only be used or copied in accordance with the terms */
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/* of the license. The information in this file is furnished for */
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/* informational use only, is subject to change without notice, and */
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/* should not be construed as a commitment by Intel Corporation. */
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/* Intel Corporation assumes no responsibility or liability for any */
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/* errors or inaccuracies that may appear in this document or any */
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/* software that may be provided in association with this document. */
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/* Except as permitted by such license, no part of this document may */
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/* be reproduced, stored in a retrieval system, or transmitted in any */
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/* form or by any means without the express written consent of Intel */
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/* Corporation. */
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/* */
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/* Title: Comm. Power Manager Header File */
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/* */
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/* Filename: commpm.h */
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/* */
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/* Author: Raviv Levi */
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/* */
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/* Project, Target, subsystem: Tavor, Arbel, HOP */
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/* */
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/* Remarks: - */
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/* */
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/* Created: 19/9/2005 */
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/* */
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/* Modified: */
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/************************************************************************/
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#ifndef _COMMPM_H_
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#define _COMMPM_H_
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#include "global_types.h"
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#include "powerManagement.h"
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/*----------- Global defines -------------------------------------------------*/
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//#if ((defined PM_DEBUG_MODE_ENABLED))/* && (!defined COMMPM_DEBUG_MODE_ENABLED))*/
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// #define COMMPM_DEBUG_MODE_ENABLED
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//#endif
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/*----------- Global macro definitions ---------------------------------------*/
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#define COMMPM_MAX_TIME_TABLE 30
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/*----------- Global type definitions ----------------------------------------*/
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// This enumerator describes the various values that may be returned.
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typedef enum
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{
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COMMPM_RC_ERR = -100,
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COMMPM_RC_OK = 0
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} CommPM_ReturnValueE;
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// This enumerator describes the various core frequencies available through
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// the CommPM package. Note that the frequencies relate to the GB core as the
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// Arbel core frequencies are determines by the 2:1 / 3:2 ratio (according to the fuse settings).
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// This enumerator is basically a wrapper to the CommCCU_SystemPLLFreqE enumerator.
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typedef enum
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{
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COMMPM_GB_CORE_FREQ_52MHZ = 0,
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COMMPM_GB_CORE_FREQ_104MHZ,
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COMMPM_GB_CORE_FREQ_156MHZ,
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COMMPM_GB_CORE_FREQ_208MHZ,
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COMMPM_GB_CORE_FREQ_312MHZ,
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COMMPM_GB_CORE_NUM_OF_FREQS
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}CommPM_GBCoreFreqsE;
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// this ENUM is added for the CommPMDDRRequestManage called by RM to handle the request of the DDR
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typedef enum
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{
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COMMPM_RELQ_HIGH_FREQ_DDR = 0,
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COMMPM_REQUEST_HIGH_FREQ_DDR
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}CommPM_DDRRequestE;
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// This enumerator describes the various wakeup sources currently supported by our HW.
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typedef enum
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{
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COMMPM_WAKEUP_SOURCE_SSP = 0, // Only GSSP2 is used. (even though GSSP1 is connected too)
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COMMPM_WAKEUP_SOURCE_I2C, // Not used.
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COMMPM_WAKEUP_SOURCE_MSL,
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COMMPM_WAKEUP_SOURCE_USIM, // Not used.
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COMMPM_WAKEUP_SOURCE_TIMER,
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COMMPM_WAKEUP_SOURCE_SCK,
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COMMPM_WAKEUP_SOURCE_WDT,
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COMMPM_WAKEUP_SOURCE_WB_SLEEP_MODULE,
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COMMPM_WAKEUP_SOURCE_TCU, // Not used.
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COMMPM_WAKEUP_SOURCE_PMIC, // Not used.
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COMMPM_WAKEUP_SOURCE_UART,
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COMMPM_WAKEUP_SOURCE_AC_IPC, // Apps Comm IPC wakeup
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COMMPM_WAKEUP_SOURCE_CGPIO,
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COMMPM_NUM_OF_WAKEUP_SOURCES
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}CommPM_WakeupSourcesE;
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// This enumerator describes the wakeup states of a CommPM wakeup source.
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typedef enum
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{
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COMMPM_WAKEUP_SOURCE_ENABLED = 0,
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COMMPM_WAKEUP_SOURCE_DISABLED
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}CommPM_SourceWakeupStateE;
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//this enum represents the available DDR acknoledges
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typedef enum
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{
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COMMPM_DDR_READY_ACK = 0,
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COMMPM_DDR_HF_READY_ACK,
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COMMPM_DDR_HF_RELQ_ACK
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}CommPM_DDRAckE;
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//this enum represents the available clients for DDR and PP notify
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//Currently, the only COMM application known is CPA (L1 representing also PS)
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// future may add more applications.
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typedef enum
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{
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COMMPM_CLIENT_0_NOTUSED = 0,
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COMMPM_CLIENT_CPA_1,COMMPM_CLIENT_CPA_GSM_UMTS_1=COMMPM_CLIENT_CPA_1,
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COMMPM_CLIENT_CPA_GSM_TD_1 = COMMPM_CLIENT_CPA_1,
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COMMPM_CLIENT_AUDIO_2,
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COMMPM_CLIENT_3, COMMPM_CLIENT_CPA_LTE_3=COMMPM_CLIENT_3,
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COMMPM_CLIENT_CPA_SIMB_POWERON,
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COMMPM_CLIENT_PLATFORM_INTERNAL,
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COMMPM_CLIENT_MMI,
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COMMPM_NUMBER_OF_CLIENTS
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}CommPM_ClientsE;
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//this enum represents the available PP (product points)
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//ICAT EXPORTED ENUM
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typedef enum {
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COMMPM_PP_NOTSET,
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COMMPM_PP_1,
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COMMPM_PP_2,
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COMMPM_PP_3,
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COMMPM_PP_4,
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COMMPM_NUMBER_OF_PP = 4
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} CommPM_PPE;
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#define COMMPM_MAX_PP COMMPM_PP_4
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#define COMMPM_D2 COMMPM_PP_NOTSET // for duty cycle
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// This type definition describes the DDR notify callback functions type.
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typedef void (*COMMPM_DDRAckNotificationT)(CommPM_DDRAckE ackType);
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// This type definition describes the PP change notify callback functions type.
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typedef void (*COMMPM_DDRDVFMNotificationT)(CommPM_PPE PPType);
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// Services and applications that control entry to D1 (D1 is entered when both COMM and MSA are in C1)
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// Due to Silicon bug in A0 - the D1 state causes problems for several services:
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// UART, TCU, HSDPA (?)
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//ICAT EXPORTED ENUM
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typedef enum
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{
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Service_UART = 0x01,
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Enable_TCU_clock= 0x02,
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Service_HSPDA = 0x04,
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Service_ICAT = 0x08,
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Service_client5 = 0x10,
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Service_client6 = 0x20,
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Service_client7 = 0x40,
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Service_client8 = 0x80
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} CommPM_servicesD1E;
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//ICAT EXPORTED ENUM
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typedef enum {
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COMMPM_MODEM_ENABLE = 0,
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COMMPM_MODEM_DISABLE,
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COMMPM_INVALID_STATE
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}PM_Modem_StateE;
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typedef enum
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{
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COMMPM_BIT_DISABLE= 0,
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COMMPM_BIT_ENABLE,
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}CommPM_Bit_StatusE;
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typedef enum
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{
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COMMPM_NMOS_ENGAGE= 0,
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COMMPM_NMOS_DISENGAGE,
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}CommPM_Nmos_StatusE;
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//rafiagiv 27.02.07
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// added control in A0 - PM bits spread in various placed in HRBL, thus controled via commPM
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typedef enum
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{
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//CPMU drivers controls
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COMMPM_WB_GSM_TCU_CE_SEL = 0, //TCU_CE_SEL
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COMMPM_WB_GSM_SLP_TIMER_SEL, //SGW
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COMMPM_GSM_STKY_RST, //GWE_STKY_RST
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COMMPM_WB_SLEEP_MODULE_POLARITY_FIX, //(not documented yet)
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COMMPM_WB_NUM_OF_CONROL_BITS_IN_CPMU,
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//MCCU drivers controls
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COMMPM_WB_SLP_EQ_EN, //GWbWakeSel
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COMMPM_WB_WAKE_SEL, //GWbslpEqEn
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COMMPM_WB_NUM_OF_CONROL_BITS
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}CommPM_WB_GSM_Control_BitsE;
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/* Work Directive - what to activate in power */
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/* By default (May 06) all is disabled, When mature, the default will
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be all enabled (set in CommPMInit()) */
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//ICAT EXPORTED STRUCT
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typedef struct
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{
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UINT32 D2mode; // 0 - no D2, 1 - D2 alike, 2 - full D2
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UINT32 D2Variation; // 0 Stay in D0, 1, go to C1, 2 Full D2
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UINT32 LPTsleepTicks; // how many ticks the LPT should sleep
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// temp solution for L1 Standalone.
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UINT32 LPTdebugBusyWait; // to enable time to enter commands when
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// waking up (since currently (Sep 06) at C1/D2
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// we can not submit commands)
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UINT32 DDRFunctionalityIsOn; // 0-regular work without DDR / 1-DDR functionality is open for debug / 2-DDR full functionality
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UINT32 endlessLoopAfterD2nExit;
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UINT32 endlessLoopAfterDDRgrantnTimes;
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UINT32 kickWDTonD2Exit;
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UINT16 ServiceD1control; // word that indicates service controlling D1, if bit is set, D1 should be prevented
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// (the bit position is set by the enum CommPM_servicesD1E)
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UINT8 AppsCommSyncActivated;
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BOOL allowC1; // when set real C1 from HW (if D2 set, also C1 ?)
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BOOL notifyMSA; // if set - we work with L1, and should notify them
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// otherwise we are in 'D2 standalone' - only us
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BOOL LPTidle; // LPT does nothing
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BOOL LPTdecisionOnly; // do only decision no setting to HW, no prepare
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// (means no real D2, no C1) (not relevant in LPTidle)
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// if not set - we have full LPT functionality
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BOOL L1isRegister; // to synchronize D2 decisions on L1 registration
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BOOL PmDebugTaskEnalbe; //to enable/disable comm pm debug task
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} CommPM_workModeS;
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// Timing for DDR request (reg, HF) - (to put under PMDEBUG?)
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//ICAT EXPORTED STRUCT
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typedef struct
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{
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UINT32 DdrHfRequestTS; // current client request TS (maybe DDR in HF already)
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UINT32 DdrHfRequestFirstClientTS; // signifies the first client request (the one we wait for its ack)
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UINT32 DdrRegRequestTS;
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UINT32 DdrRegMaxResponseTime;
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UINT32 DdrHfClientTabResponseTime[COMMPM_MAX_TIME_TABLE];
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UINT32 DdrRegClientTabResponseTime[COMMPM_MAX_TIME_TABLE];
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UINT32 DdrHfMaxResponseTime;
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} CommPM_DDRtimingS;
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/*----------- Extern definition ----------------------------------------------*/
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extern CommPM_workModeS _CPMworkMode;
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//#define PMUM_POCR_VCXOST 71 // PMUM_POCR[23:16] VCXOST 0~-0xE5
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//#define PMUM_POCR_VCXOST 99 // PMUM_POCR[23:16] VCXOST 0~-0xE5
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//#define PMUM_POCR_VCXOST 94 // PMUM_POCR[23:16] VCXOST 0~-0xE5
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#ifdef L1_DCXO_ENABLED
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extern UINT16 RfDcxoIsUsingFlg;
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extern UINT8 check_if_DCS_mode(void);
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#define PMUM_POCR_VCXOST (((RfDcxoIsUsingFlg == TRUE) && (check_if_DCS_mode() == TRUE)) ? 141 : 94)
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#else
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#define PMUM_POCR_VCXOST 94 // PMUM_POCR[23:16] VCXOST 0~-0xE5
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#endif
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//Please note - the following define VCTCXO_STAB_TIME is for calculation only. It is not the actual VCTCXO stabilization (OSCC register)
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//#define COMMPM_DEFAULT_VCTCXO_STAB_TIME_IN_SCK_TVR_P (PMUM_POCR_VCXOST - 15 + 65 + 80) //0.5 (stabilization time in OSCC) + 1.55 (DC) = 2.05ms
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#define COMMPM_DEFAULT_VCTCXO_STAB_TIME_IN_SCK_TVR_P (PMUM_POCR_VCXOST - 15 + 40) //0.5 (stabilization time in OSCC) + 1.55 (DC) = 2.05ms
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// #define COMMPM_DEFAULT_VCTCXO_STAB_TIME_IN_SCK_TVR_P 68 //0.5 (stabilization time in OSCC) + 1.55 (DC) = 2.05ms
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#define COMMPM_DEFAULT_VCTCXO_STAB_TIME_IN_SCK_TVR_PV 19 //0.550(stabilization time in OSCC)
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#define COMMPM_DEFAULT_MAIN_PLL_STAB_TIME_IN_SCK 0
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#define COMMPM_DEFAULT_HARBELL_IPC_REC_TIME_IN_SCK_NO_SYNC 113 //38 +75 (additonal ~2 msec of apps ack time for ddr req)
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#define COMMPM_DEFAULT_HARBELL_IPC_REC_TIME_IN_SCK_WITH_SYNC 58 //38 +75 (additonal ~2 msec of apps ack time for ddr req) -55 (1.7)
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#define COMMPM_DEFAULT_PLATFORM_RECOVERY_TIME_IN_SCK_GSM 9
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#define COMMPM_DEFAULT_PLATFORM_RECOVERY_TIME_IN_SCK_WB 6
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#define COMMPM_DEFAULT_APPS_D2_ROUND_TRIP_TIME_IN_SCK 86 //~2.6mSec for APPS D2 round trip(goes to D2 and wake)
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#define COMMPM_DEFAULT_PLATFORM_D2_ENTRY_TIME_IN_SCK 32 //~1mSec for COMM D2 entry sequence (from interrupts disable till sleep)
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typedef struct
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{
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UINT32 DefaultVctcxoStabTimeInSck;
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UINT32 DefaultMainPllStabTimeInSck;
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UINT32 DefaultHarbelIPCrecTimeInSck;
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UINT32 DefaultPlatformRecoveryTimeInSck;
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} CommPM_WBWakeupParamsS;
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/* CPU state - active or idle for duty cycle tool */
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//ICAT EXPORTED ENUM
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typedef enum {
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CommPM_Active,
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CommPM_Idle,
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COMMPM_NUMBER_OF_CPU_STATES,
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} CommPM_CPUStateE;
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/* Comm state PP or LPM for duty cycle */
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typedef enum {
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CommPM_D2,
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CommPM_PP,
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} CommPM_CoreStateE;
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/* Send PP update to DSP */
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typedef enum {
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CommPmSendDSP,
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CommPmDontSendDSP,
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} CommPM_SendDSPE;
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#ifdef DutyCycleDspEnable
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/*IPC Commands for MSA Duty Cycles*/
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#define COMMPM_MSA_POWER_MANAGER_CTRL_LENGTH 1
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#define COMMPM_MSA_POWER_MANAGER_CTRL_CMD 0
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#define COMMPM_MSA_POWER_MANAGER_CTRL_OPCODE 0x00F6
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#define COMMPM_MSA_POWER_MANAGER_CTRL_IPC_RET_OPCODE 0x000D
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#define COMMPM_MSA_POWER_MANAGER_CTRL_START_CMD 0x000D
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#define COMMPM_MSA_POWER_MANAGER_CTRL_STOP_CMD 0x000E
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#define COMMPM_MSA_POWER_MANAGER_CTRL_RESET_CMD 0x0010
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#define COMMPM_MSA_POWER_MANAGER_CTRL_DISPLAY_CMD 0x000F
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#define COMMPM_MSA_POWER_MANAGER_CTRL_CHANGE_PP1_CMD 0x0011
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#define COMMPM_MSA_POWER_MANAGER_CTRL_CHANGE_PP2_CMD 0x0012
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#define COMMPM_MSA_POWER_MANAGER_CTRL_CHANGE_PP3_CMD 0x0013
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#define COMMPM_MSA_POWER_MANAGER_CTRL_CHANGE_PP4_CMD 0x0014
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#define COMMPM_MSA_POWER_MANAGER_WRONG_OPCODE 0
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#define COMMPM_MSA_POWER_MANAGER_CANNOT_REGISTER_TO_IPC 0
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#endif
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typedef enum {
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DutyCycleOff,
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DutyCycleOn,
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} CommPM_DutyCycleSateE;
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typedef enum {
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DutyCycleCore,
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DutyCycleDSP,
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} DutyCycleWhichCore;
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typedef struct {
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UINT32 Time[COMMPM_NUMBER_OF_PP+1][COMMPM_NUMBER_OF_CPU_STATES];
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} DutyCycleDataS;
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/* Duty Cycle Tool - debug time spent in each pp and cpu state */
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typedef struct {
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DutyCycleDataS DutyCycleData;
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UINT32 LastTime;
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CommPM_DutyCycleSateE state;
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} CommPM_DutyCycleS;
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/*duty cycle event*/
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typedef enum
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{
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CP_FREQ_416M = 0,
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CP_FREQ_624 = 1,
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CP_D2 = 2,
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} DutyCycleEvent ;
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////duty cycle end///////////
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extern CommPM_DutyCycleS GCommPM_DutyCycle;
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typedef struct
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{
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UINT32 CommPmD2WakeupTime;
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UINT32 EarlyWakeupTime;
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} CommPM_GSMWakeupParamsS;
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/*----------- Global variable declarations -----------------------------------*/
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/*----------- Global constant definitions ------------------------------------*/
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/*----------- Global function prototypes -------------------------------------*/
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// Init functions.
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void CommPMInit (void);
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// Package specific APIs.
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void CommPMWaitForHWSignal (BOOL waitForHWSignal);
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void CommPMWakeupSourceStateSet (CommPM_WakeupSourcesE wakeupSource,
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CommPM_SourceWakeupStateE sourceWakeupState);
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void CommPMDDRRequestManage(CommPM_DDRRequestE request);
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void AC_IPCInterruptHandler(UINT32 status);
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// API to control entering D1, if TRUE - allow D1, if FALSE - prevent D1
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void CommPMControlEnterD1state(CommPM_servicesD1E service, BOOL b_enable);
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void CommpmWbGsmBitSet (CommPM_WB_GSM_Control_BitsE controlBit ,CommPM_Bit_StatusE enableDisable);
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CommPM_Bit_StatusE CommpmWbGsmBitGet (CommPM_WB_GSM_Control_BitsE controlBit);
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void CommpmUsimNmosEngageSet (CommPM_Nmos_StatusE enableDisable);
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CommPM_Nmos_StatusE CommpmUsimNmosEngageGet(void);
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void CommpmDDRAckNotificationCBBind(CommPM_ClientsE client , COMMPM_DDRAckNotificationT cbkForDDRAck);
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void CommpmDDRAckNotify(CommPM_DDRAckE DDRAck);
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void PMsetApplication(void);
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// Debug functions.
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#if defined(COMMPM_DEBUG_MODE_ENABLED)
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void CommPMDebugTaskCreate(void);
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#endif // COMMPM_DEBUG_MODE_ENABLED
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/*----------- Module internal function prototypes -------------------------------------*/
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PM_PowerStatesE CommPMD2EntryExit_TillDDRAck(PM_PowerStatesE state);
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void CommPMCP15D2Recover(void);
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BOOL CommPMD2EnterAsm(UINT32 r0PlaceHolder,UINT32 r1PlaceHolder);
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BOOL CommPMD2ExitHandlerAsmPhase1(void);
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void CommpmUartEnableForDebug(void); //D2DEBUG
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void SendSignalToUART(char signal); //D2DEBUG
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void CommPMGetGSMWakeupTime(CommPM_GSMWakeupParamsS *CommPM_GSMWakeupParams);
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void CommPMGetWBWakeupTime (CommPM_WBWakeupParamsS *CommPM_WBWakeupParams);
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void CommPmDutyCycleUpdate(UINT32 timestamp_32khz, DutyCycleEvent ppEvent, CommPM_CPUStateE cpuState, CommPM_SendDSPE sendDsp);
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DutyCycleEvent ChangeCoreFreqToDutyCycleEvent(void);
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typedef int (*MMIC1PrepareFunc)(void);
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typedef int (*MMIC1RecoverFunc)(void);
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typedef int (*MMID2PrepareFunc)(void);
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typedef int (*MMID2RecoverFunc)(BOOL ExitFromD2);
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typedef int (*MMIStatusFunc)(void);
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void mmiD2CallbackRegister(UINT32 prepare_func, UINT32 recover_func);
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void mmiC1CallbackRegister(UINT32 prepare_func, UINT32 recover_func);
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int MMID2Prepare(void);
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int MMID2Recover(BOOL ExitFromD2);
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int MMIC1Prepare(void);
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int MMIC1Recover(void);
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int MMIStatus(void);
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UINT32 DCXOLPMRegister(unsigned char *name);
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void DCXOLPMOn(UINT32 client);
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void DCXOLPMOff(UINT32 client);
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#endif //_COMMPM_H_
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