155 lines
7.0 KiB
C
155 lines
7.0 KiB
C
/*------------------------------------------------------------
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(C) Copyright [2006-2008] Marvell International Ltd.
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All Rights Reserved
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------------------------------------------------------------*/
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/*--------------------------------------------------------------------------------------------------------------------
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INTEL CONFIDENTIAL
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Copyright 2006 Intel Corporation All Rights Reserved.
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The source code contained or described herein and all documents related to the source code ("Material") are owned
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by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or
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its suppliers and licensors. The Material contains trade secrets and proprietary and confidential information of
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Intel or its suppliers and licensors. The Material is protected by worldwide copyright and trade secret laws and
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treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted,
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transmitted, distributed, or disclosed in any way without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual property right is granted to or
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conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement,
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estoppel or otherwise. Any license under such intellectual property rights must be express and approved by
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Intel in writing.
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-------------------------------------------------------------------------------------------------------------------*/
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#if !defined (CPU_MIPS_TEST_H)
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# define CPU_MIPS_TEST_H
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/*********************************************************************
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* There may be next debug tools (and their combinations):
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* - MIPS logger into RAM MIPS_TEST_RAM
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* - XDA external logger MIPS_TEST
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* - ISPT external logger DATA_COLLECTOR_IMPL
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* Some combination may be chosen by compile switches only, some by run-time.
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*
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* Let's "describe" next macro for every one or no-loggers case:
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* CPU_MIPS_TEST
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* CPU_MIPS_TEST_S
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* MIPS_MIN_LISR_ID
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* MIPS_MIN_TASK_ID
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*********************************************************************/
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#if !defined (MIPS_TEST) && !defined (MIPS_TEST_RAM) && !defined (DATA_COLLECTOR_IMPL)
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// No Logger required
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#define CPU_MIPS_TEST_SYNC32K(dATA_OUT)
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#define CPU_MIPS_TEST(dATA_OUT)
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#define CPU_MIPS_TEST_S(dATA_OUT)
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#endif
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#if defined (MIPS_TEST_RAM)
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// Dynamic switching of the "MIPS" monitoring modes: MIPS_RAM, XDA, EXT, etc.
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typedef enum
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{
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mipsRamModeNormal,
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mipsRamModeXDA,
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mipsRamModeExt,
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mipsRamModeMax
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}MipsRamMode;
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//include list of user defined event IDs
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#include "cpu_mips_evntList.h"
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extern MipsRamMode mipsRamModeSet(MipsRamMode mode);
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extern void mipsRamSwitchSubTaskID(UINT32 modifier);
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extern void mipsRamHook(UINT32 value);
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extern UINT32 mipsRamSync32kEvent(UINT32 value); //Unprotected! Returns the T32K free running timer as APDC=13MHZ
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// Profiling of specific tasks:
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// Trace a sub-task ID (16-bit) and set the current sub-task ID (0 indicates no sub-task, i.e. main task is active)
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#define MIPSRAM_SUB_TASK_ID_MOD_MASK 0xFFFF0000
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#define CPU_MIPS_TEST_S(dATA_OUT) mipsRamSwitchSubTaskID((dATA_OUT)<<16)
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#if !defined SEND_PM_TRACE_TO_LOGGER_SYNC32K
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#define SEND_PM_TRACE_TO_LOGGER_SYNC32K(mSG_TYPE) mipsRamSync32kEvent(mSG_TYPE) /*CPU_MIPS_TEST_SYNC32K(mSG_TYPE)*/
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#endif
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#if !defined SEND_PM_TRACE_TO_LOGGER
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#define SEND_PM_TRACE_TO_LOGGER(mSG_TYPE) CPU_MIPS_TEST(mSG_TYPE);
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#endif
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#if !defined SEND_PM_TRACE_DATA_TO_LOGGER
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#define SEND_PM_TRACE_DATA_TO_LOGGER(mSG_TYPE, dATA) CPU_MIPS_TEST(mSG_TYPE | dATA);
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#endif
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#if defined (DATA_COLLECTOR_IMPL) //Amit&Alex - in Tavor ISPT,XDA and MIPS_RAM all use the same hook
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extern void _DC_INTC_Hook(UINT32 value);
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#if defined (EDEN_1928) || defined (NEZHA3_1826)
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#define CPU_MIPS_TEST(dATA_OUT)
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#else
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#define CPU_MIPS_TEST(dATA_OUT) _DC_INTC_Hook(dATA_OUT);
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#endif
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#else //Amit&Alex - else, in Hermon use original MIPS_RAM hook
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//#define CPU_MIPS_TEST_SYNC32K(dATA_OUT) mipsRamSync32kEvent(dATA_OUT)
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#if defined (EDEN_1928) || defined (NEZHA3_1826)
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#define CPU_MIPS_TEST(dATA_OUT)
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#else
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#define CPU_MIPS_TEST(dATA_OUT) mipsRamHook((UINT32)(dATA_OUT))
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#endif
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#endif
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#endif //(MIPS_TEST_RAM)
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//-------------------------------------------------------------------------------------------------------------------
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#if defined (DATA_COLLECTOR_IMPL) && !defined (MIPS_TEST_RAM)
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#define CPU_MIPS_TEST(dATA_OUT) _DC_INTC_Hook(dATA_OUT);
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#define CPU_MIPS_TEST_S(dATA_OUT)
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#define SEND_PM_TRACE_TO_LOGGER_SYNC32K(mSG_TYPE) mipsRamSync32kEvent(mSG_TYPE)
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#else
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#if defined (MIPS_TEST)&& !defined (SILICON_PV2) && !defined (MIPS_TEST_RAM) //_TAVOR_HARBELL_
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#define CPU_MIPS_TEST(dATA_OUT) *((volatile UINT16 *) 0x0c600000) = dATA_OUT
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#define CPU_MIPS_TEST_S(dATA_OUT)
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#endif//#if defined (MIPS_TEST)&& !defined (_TAVOR_HARBELL_) && !defined (MIPS_TEST_RAM)
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#endif//#if defined (DATA_COLLECTOR_IMPL) && !defined (MIPS_TEST_RAM)
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//-------------------------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------------------------
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#if !defined(MIPS_MIN_TASK_ID)
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#if defined(MIPS_TEST_RAM)
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#define MIPS_MIN_TASK_ID 0x100
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#else
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#define MIPS_MIN_TASK_ID 0
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#endif
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#endif
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#if defined (MIPS_TEST)
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#define START_MIPS_TEST_FUNC_1 *((volatile UINT16 *) 0x0c600000) = 224
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#define STOP_MIPS_TEST_FUNC_1 *((volatile UINT16 *) 0x0c600000) = 225
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#define START_MIPS_TEST_FUNC_2 *((volatile UINT16 *) 0x0c600000) = 226
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#define STOP_MIPS_TEST_FUNC_2 *((volatile UINT16 *) 0x0c600000) = 227
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#define START_MIPS_TEST_FUNC_3 *((volatile UINT16 *) 0x0c600000) = 228
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#define STOP_MIPS_TEST_FUNC_3 *((volatile UINT16 *) 0x0c600000) = 229
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#define START_MIPS_TEST_FUNC_4 *((volatile UINT16 *) 0x0c600000) = 230
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#define STOP_MIPS_TEST_FUNC_4 *((volatile UINT16 *) 0x0c600000) = 231
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#define START_MIPS_TEST_FUNC_5 *((volatile UINT16 *) 0x0c600000) = 232
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#define STOP_MIPS_TEST_FUNC_5 *((volatile UINT16 *) 0x0c600000) = 233
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#define START_MIPS_TEST_FUNC_6 *((volatile UINT16 *) 0x0c600000) = 234
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#define STOP_MIPS_TEST_FUNC_6 *((volatile UINT16 *) 0x0c600000) = 235
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#define START_MIPS_TEST_FUNC_7 *((volatile UINT16 *) 0x0c600000) = 236
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#define STOP_MIPS_TEST_FUNC_7 *((volatile UINT16 *) 0x0c600000) = 237
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#define START_MIPS_TEST_FUNC_8 *((volatile UINT16 *) 0x0c600000) = 238
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#define STOP_MIPS_TEST_FUNC_8 *((volatile UINT16 *) 0x0c600000) = 239
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#endif // End of Mips test
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/************************************************************************
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* Non-Automatic (non-NUCLEUS) events used by CPU_MIPS_TEST()
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*/
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#define CPU_MIPS_EVENT_BASE_CUSTOMER 0
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#define CPU_MIPS_EVENT_BASE_SYSRESERVE 0x80
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#define CPU_MIPS_EVENT_BASE_PM 0xE0 /*depends also from ISPT */
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#endif //CPU_MIPS_TEST_H - EOF
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