293 lines
10 KiB
C
293 lines
10 KiB
C
/******************************************************************************
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*
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* (C)Copyright 2005 - 2012 Marvell. All Rights Reserved.
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*
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* THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MARVELL.
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* The copyright notice above does not evidence any actual or intended
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* publication of such source code.
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* This Module contains Proprietary Information of Marvell and should be
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* treated as Confidential.
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* The information in this file is provided for the exclusive use of the
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* licensees of Marvell.
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* Such users have the right to use, modify, and incorporate this code into
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* products for purposes authorized by the license agreement provided they
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* include this notice and the associated copyright notice with any such
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* product.
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* The information in this file is provided "AS IS" without warranty.
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*
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******************************************************************************/
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#ifndef __SPI_H__
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#define __SPI_H__
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#include "ssp_reg.h"
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// Flash Types
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typedef enum
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{
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CS0_XIP_FLASH = 1,
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CS2_XIP_FLASH = 2,
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NAND_FLASH = 3,
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ONENAND_FLASH = 4,
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MSYS_DOC_FLASH = 5,
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SDMMC_FLASH = 6,
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SPI_NOR_FLASH = 7,
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SPI_NAND_FLASH = 8
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} FlashType_T;
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// Flash Fuses
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typedef enum
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{
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NO_FLASH_P = 0,
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MSYS_DOC_FLASH_P = 1,
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ONENAND_FLASH_P = 2,
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CS0_XIP_FLASH_P = 3,
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NAND_FLASH_X16_P = 4,
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CS2_XIP_SIBLEY_P = 5,
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NAND_FLASH_X8_P = 6,
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CS2_XIP_TYAX_P = 7,
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SDMMC_FLASH_OPT1_P = 8,
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SDMMC_FLASH_OPT2_P = 9,
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SPI_FLASH_P = 10,
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SDMMC_FLASH_OPT3_P = 11
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} FlashProbeList_T;
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// Flash Structure Types
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typedef enum
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{
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BOOT_FLASH = 0,
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SAVE_STATE_FLASH = 1
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} FlashBootType_T;
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// ssp flash
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typedef enum
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{
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SSP_PORT_0 = 0,
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SSP_PORT_1 = 1,
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SSP_PORT_2 = 2,
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} SSP_PORT;
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typedef struct
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{
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unsigned int Reserved : 13;
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unsigned int SASize : 11; //size of spare area, in bytes, PER PAGE!!
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unsigned int UseSpareArea : 1; //tells driver whether to write spare area or not (1 = yes, 0 = no)
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unsigned int UseHwEcc : 1; //tells driver whether to use HW ECC during read and writes (1 = yes, 0 = no)
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unsigned int UseBBM : 1; //driver sets to determine if the flash should use BBM (1 = yes, 0 = no)
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unsigned int FlashNum : 4; //see above enum
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unsigned int FlashInitialized : 1; //1 = Flash initialized, 0 = Flash NOT initialized
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} FlashAttributes_T;
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typedef unsigned int (*InitFlash_F) (unsigned char FlashNum, FlashBootType_T FlashBootType, unsigned char *P_DefaultPartitionNum);
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typedef unsigned int (*FinalizeFlash_F) (FlashBootType_T FlashBootType);
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typedef unsigned int (*ReadFlash_F) (unsigned int FlashOffset, unsigned int LocalBuffer, unsigned int Size, FlashBootType_T FlashBootType);
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typedef unsigned int (*WriteFlash_F) (unsigned int FlashOffset, unsigned int LocalBuffer, unsigned int Size, FlashBootType_T FlashBootType);
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typedef unsigned int (*EraseFlash_F) (unsigned int FlashOffset, unsigned int Size, FlashBootType_T FlashBootType);
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typedef unsigned int (*ResetFlash_F) (FlashBootType_T FlashBootType);
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typedef unsigned int (*WipeFlash_F) (FlashBootType_T FlashBootType);
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typedef void (*ChangePartition_F) (unsigned int PartitionNum, FlashBootType_T FlashBootType);
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typedef unsigned int (*WriteOTP_F) (unsigned int FlashOffset, unsigned int LocalBuffer, unsigned int Size);
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typedef unsigned int (*ReadOTP_F) (unsigned int FlashOffset, unsigned int LocalBuffer, unsigned int Size);
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typedef unsigned int (*LockOTP_F) (void);
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typedef unsigned int (*ConvertToLogicalAddr_F) (unsigned int FlashLocation, FlashBootType_T FlashBootType);
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typedef struct
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{
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unsigned int BlockSize;
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unsigned int PageSize;
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unsigned int SectorSize;
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unsigned int NumBlocks;
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unsigned int TimFlashAddress;
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FlashType_T FlashType;
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unsigned int *ReservedPkgIDs;
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FlashAttributes_T FlashSettings;
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// Function pointers
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FinalizeFlash_F FinalizeFlash;
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ReadFlash_F ReadFromFlash;
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WriteFlash_F WriteToFlash;
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EraseFlash_F EraseFlash;
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ResetFlash_F ResetFlash;
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WipeFlash_F WipeFlash;
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ChangePartition_F ChangePartition;
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WriteOTP_F WriteOTP;
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ReadOTP_F ReadOTP;
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LockOTP_F LockOTP;
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ConvertToLogicalAddr_F pConvertToLogicalAddr;
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}
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FlashProperties_T, *P_FlashProperties_T;
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/* Supported SPI Devices */
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typedef struct{
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unsigned int SPI_ID;
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unsigned int SPI_CAPACITY;
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unsigned int SPI_SECTOR_SIZE;
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unsigned int SPI_PAGE_SIZE;
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} SPI_DEVICE_INFO_T, *P_SPI_DEVICE_INFO_T;
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typedef enum
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{
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SSP_CLOCK_13M = 0x0,
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SSP_CLOCK_26M = 0x1,
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SSP_CLOCK_52M = 0x2,
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} SSP_Clock;
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#define TRUE 1
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#define FALSE 0
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/*
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* SPI Command Set
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*/
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#define SPI_CMD_JEDEC_ID 0x009F
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#define SPI_CMD_READ_STATUS 0x05
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#define SPI_CMD_WRITE_ENABLE 0x06
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#define SPI_CMD_WRITE_STATUS_REG 0x01
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#define SPI_CMD_PROGRAM 0x02
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#define SPI_CMD_READ 0x03
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#define SPI_CMD_SECTOR_ERASE 0x20
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#define SPI_CMD_CHIP_ERASE 0xc7
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#define SPI_CMD_BLOCK_ERASE 0xd8
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#define SPI_CMD_POWER_DOWN 0xB9
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#define SPI_CMD_RELEASE_POWER_DOWN 0xAB
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#define SPI_CMD_RESET_ENABLE 0x66
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#define SPI_CMD_RESET 0x99
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#define DEFAULT_TIMEOUT 500
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#define TIME_OUT_ERROR 0x01
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#define SPINOR_WRITE_PAGE_SIZE (0x100 / 4)
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#define SPINOR_READ_PAGE_SIZE (0x100)
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#define WRITE_SIZE (256)
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#define READ_SIZE (0x10000)
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#ifdef SPINAND_SUPPORT
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#define SSP_BASE_FOR_SPI_NAND get_ssp_base()
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#else
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#define SSP_BASE_FOR_SPI_NOR GetSSPBase()
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#endif
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#define SSP_DMA_READ_SIZE 4096 //bytes per descriptor
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#define SPI_READ_STATUS_RDY_BIT BIT0
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#define MAX_TEST_SIZE (1024*4)
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typedef struct {
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unsigned int SPI_READ_CMD;
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unsigned int SPI_READ_STAUS_CMD;
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unsigned int SPI_WRITE_STATUS_CMD;
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unsigned int SPI_WRITE_ENABLE_CMD;
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unsigned int SPI_WRITE_STAGE1_CMD;
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unsigned int SPI_WRITE_STAGE2_CMD;
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unsigned int SPI_ERASE_CMD;
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} SPI_COMMANDS_T, *P_SPI_COMMANDS_T;
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/*
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* Nezha: SSP Register locations.
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*
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* Note: SSP_BASE_FOR_SPI_NOR set in platform_config.h
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*/
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/* SSP Control Register 0: (Offset: 0x00) */
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#define SSP_CR0 ((volatile unsigned int *) (SSP_BASE_FOR_SPI_NOR+SSP_SSCR0))
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/* SSP Control Register 1: (Offset: 0x04) */
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#define SSP_CR1 ((volatile unsigned int *) (SSP_BASE_FOR_SPI_NOR+SSP_SSCR1))
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/* SSP Status Register: (Offset: 0x08) */
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#define SSP_SR ((volatile unsigned int *) (SSP_BASE_FOR_SPI_NOR+SSP_SSSR))
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/* SSP Data Write/Read Register: (Offset: 0x10) */
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#define SSP_DR ((volatile unsigned int *) (SSP_BASE_FOR_SPI_NOR+SSP_SSDR))
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/* SSP SSP Programmable Serial Protocol Register: (Offset: 0x2C) */
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#define SSP_SP ((volatile unsigned int *) (SSP_BASE_FOR_SPI_NOR+SSP_SSPSP))
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/* SSP Time Out Register: (Offset: 0x28) */
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#define SSP_TO ((volatile unsigned int *) (SSP_BASE_FOR_SPI_NOR+SSP_SSTO))
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//Control Register special values
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#define SSP_CR0_INITIAL (SSP_SSCR0_TIM | SSP_SSCR0_RIM | 0x7)
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#define SSP_CR0_SSE SSP_SSCR0_SSE
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#define SSP_CR0_FPCKE SSP_SSCR0_FPCKE
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#define SSP_CR0_DSS_32 SSP_SSCR0_EDSS | 0xF
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#define SSP_CR0_DSS_24 SSP_SSCR0_EDSS | 0x7
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#define SSP_CR0_DSS_16 0x0000000F
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#define SSP_CR0_DSS_8 0x00000007
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#define SSP_CR1_INITIAL SSP_SSCR1_TTELP | SSP_SSCR1_TTE
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#define SSP_CR1_RWOT SSP_SSCR1_RWOT
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#define SSP_SSSR_TFL 0xF00 // BIT 11:8 --Transmit FIFO Level, when it's 0x0, TXFIFO is emptry or full.
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/*
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* NezhaC: SSP Register locations.
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*
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* Note: SSP_BASE_FOR_SPI_NOR set in platform_config.h
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*/
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/* SSP Top Control Register: (Offset: 0x00)*/
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#define SSP_TCR ((volatile int *) (SSP_BASE_FOR_SPI_NOR+SSP_TOP_CTRL))
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/* SSP FIFO Control Register: (Offset: 0x04)*/
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#define SSP_FCR ((volatile int *) (SSP_BASE_FOR_SPI_NOR+SSP_FIFO_CTRL))
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/* SSP Interrupt Enable Register: (Offset: 0x08)*/
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#define SSP_IER ((volatile int *) (SSP_BASE_FOR_SPI_NOR+SSP_INT_EN))
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/* SSP Time Out Register: (Offset: 0x0C)*/
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#define SSP_TOR ((volatile int *) (SSP_BASE_FOR_SPI_NOR+SSP_TIMEOUT))
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/* SSP Data Register: (Offset: 0x10)*/
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//#define SSP_DR ((volatile int *) (SSP_BASE_FOR_SPI_NOR+SSP_DATAR))
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/* SSP Status Register: (Offset: 0x14)*/
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#define SSP_STS ((volatile int *) (SSP_BASE_FOR_SPI_NOR+SSP_STATUS))
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//Control Register special values
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#define SSP_TCR_INITIAL (SSP_TCR_TTELP | SSP_TCR_TTE | SSP_TCR_DSS8)
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#define SSP_IER_INITIAL (SSP_IER_TIM | SSP_IER_RIM)
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#define SSP_FCR_INITIAL 0
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#define SSP_FCR_DMA_PAGE_PROGRAM (SSP_FCR_RFT(4) | SSP_FCR_TFT(3) | SSP_FCR_RSRE | SSP_FCR_TSRE)
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#define SSP_FCR_DMA_READ (SSP_FCR_RFT(4) | SSP_FCR_TFT(3) | SSP_FCR_RSRE | SSP_FCR_TSRE)
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#define SSP_FCR_DMA_WRITE (SSP_FCR_TFT(2) | SSP_FCR_RSRE | SSP_FCR_TSRE)
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#define SSP_FCR_DMA_ERASE (SSP_FCR_TFT(2) | SSP_FCR_RSRE | SSP_FCR_TSRE)
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#define SSP_FCR_NAND_DMA_READ (SSP_FCR_RFT(3) | SSP_FCR_TFT(3) | SSP_FCR_RSRE | SSP_FCR_TSRE)
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#define SSP_TOR_TIMEOUT 0x1FFF
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/* Transmit FIFO Level: BIT 11:7, when it's 0x0, TXFIFO is emptry or full. */
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#define SSP_STS_TFL 0xF80
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/* Transmit FIFO Not Full: 0 = TXFIFO is ful, 1 = TXFIFO is not full */
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#define SSP_STS_TF_NF BIT_6
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/* SSP Busy: 0 = SSPx port is idle or disabled, 1 = SSPx port is currently transmitting or receiving framed data */
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#define SSP_STS_BSY BIT_0
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#define BU_REG_READ8(x) (*(volatile unsigned char *)(x) & 0xff)
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#define BU_REG_WRITE8(x,y) ((*(volatile unsigned char *)(x)) = y & 0xff )
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#define spi_reg_read(reg) *(volatile unsigned int *)(reg)
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#define spi_reg_write(reg, val) *(volatile unsigned int *)(reg) = val; *(volatile unsigned int *)(reg);
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#ifndef spi_reg_bit_set
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#define spi_reg_bit_set(reg, val) *(volatile unsigned int *)(reg) |= val; *(volatile unsigned int *)(reg);
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#endif
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#ifndef spi_reg_bit_clr
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#define spi_reg_bit_clr(reg, val) *(volatile unsigned int *)(reg) &= ~val; *(volatile unsigned int *)(reg);
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#endif
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unsigned int SPINOR_Wipe(int sspport);
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unsigned int SPINOR_EraseByBlock(int sspport, unsigned int Address, unsigned int Size);
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unsigned int SPINOR_EraseBySector(int sspport, unsigned int Address, unsigned int Size);
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unsigned int SPINOR_Read(int sspport, unsigned int FlashOffset, unsigned int Buffer, unsigned int Size);
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unsigned int SPINOR_Write(int sspport, unsigned int Address, unsigned int Buffer, unsigned int Size);
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int InitializeSPIDevice(int sspport, int sspclock);
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void SPINOR_SW_Reset(int sspport);
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int SPINOR_getSSPPort(void);
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void SetSSPPort(int port);
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#endif
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