207 lines
6.6 KiB
C
207 lines
6.6 KiB
C
#ifndef _SYSTEM_H_
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#define _SYSTEM_H_
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//#define isb() __asm__ volatile ("isb" : : : "memory")
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typedef enum {
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NO_ACCESS =0x0,
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FULL_ACCESS =0x3,
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READ_ONLY =0x6
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}access_permission;
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//region size
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typedef enum {
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REG_4KB =0x0B,
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REG_8KB =0x0C,
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REG_16KB =0x0D,
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REG_32KB =0x0E,
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REG_64KB =0x0F,
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REG_128KB =0x10,
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REG_256KB =0x11,
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REG_512KB =0x12,
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REG_1MB =0x13,
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REG_2MB =0x14,
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REG_4MB =0x15,
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REG_8MB =0x16,
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REG_16MB =0x17,
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REG_32MB =0x18,
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REG_64MB =0x19,
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REG_128MB =0x1A,
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REG_256MB =0x1B,
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REG_512MB =0x1C,
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REG_1GB =0x1D,
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REG_2GB =0x1E,
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REG_4GB =0x1F
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}region_size;
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#define SCTLR_M (1 << 0) /* Enable the MPU */
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#define SCTLR_A (1 << 1) /* Alignment check enable bit */
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#define SCTLR_C (1 << 2) /* Cache enable bit */
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#define SCTLR_SW (1 << 10) /* SWP/SWPB enable bit */
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#define SCTLR_Z (1 << 11) /* Branch prediction enable bit */
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#define SCTLR_I (1 << 12) /* Instruction cache enable bit */
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#define SCTLR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
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#define SCTLR_RR (1 << 14) /* Not on Cortex-R7 processor. Round Robin bit for cache implementation policy */
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#define SCTLR_BR (1 << 17) /* Background region bit */
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#define SCTLR_DZ (1 << 19) /* Divide by zero fault bit */
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#define SCTLR_FI (1 << 21) /* Fast interrupts configuration enable */
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#define SCTLR_U (1 << 22) /* Not on Cortex-R7 processor. Indicates use of the alignment model */
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#define SCTLR_EE (1 << 25) /* Exception endianness */
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#define SCTLR_NMFI (1 << 27) /* Non-maskable FIQ(NMFI) support */
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#define SCTLR_TE (1 << 30) /* Thumb exception enable */
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#define SCTLR_IE (1 << 31) /* Instruction Endianness */
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#if 1
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extern unsigned int sctlr_get(void);
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extern void sctlr_set(unsigned int val);
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#else
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static /*inline*/ unsigned int sctlr_get(void)
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{
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unsigned int val;
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__asm__ __volatile__ ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val) : : "memory", "cc");
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return val;
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}
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static /*inline*/ void sctlr_set(unsigned int val)
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{
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__asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val) : "memory", "cc");
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isb();
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}
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#endif
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/* Region num 0 has the lowest priority */
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#define MAX_REGION_NUM 16
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#define MPU_REGION_ACCESS_CTRL_B (1 << 0) /* Bufferable */
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#define MPU_REGION_ACCESS_CTRL_C (1 << 1) /* Cacheable */
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#define MPU_REGION_ACCESS_CTRL_S (1 << 2) /* Shared */
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#define MPU_REGION_ACCESS_CTRL_TEX(x) (((x) & 0x7) << 3) /* Type Extensions */
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#define MPU_REGION_ACCESS_CTRL_AP(x) (((x) & 0x7) << 8) /* Access Permissions */
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#define MPU_REGION_ACCESS_CTRL_XN (1 << 12) /* Execute Never */
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#define MPU_REGION_SIZE_MASK (0x1f << 1) /* Region size mask */
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#define MPU_REGION_ENABLE (1 << 0) /* Region Enable */
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#if 1
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extern unsigned int mpu_get_region_num(void);
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extern void mpu_set_region_num(unsigned int val);
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extern unsigned int mpu_get_region_base_addr(void);
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extern void mpu_set_region_base_addr(unsigned int val);
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extern unsigned int mpu_get_region_size(void);
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extern void mpu_set_region_size(unsigned int size);
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extern unsigned int mpu_get_region_size_enable(void);
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extern unsigned int mpu_get_region_access_ctrl(void);
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extern void mpu_set_region_access_ctrl(unsigned int acc_ctrl);
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extern void mpu_enable_region(unsigned int num, unsigned int enable);
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extern void CPUCleanDCacheLine(unsigned int addr);
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extern void CPUInvalidateDCacheLine(unsigned int addr);
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extern void CacheInvalidateMemory(void *pMem, unsigned int size);
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extern void CacheCleanMemory(void *pMem, unsigned int size);
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extern void enable_psram_cache(void);
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extern void disable_psram_cache(void);
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#else
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static /*inline*/ unsigned int mpu_get_region_num(void)
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{
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unsigned int val;
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__asm__ __volatile__ ("mrc p15, 0, %0, c6, c2, 0" : "=r" (val) : : "memory", "cc");
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return val;
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}
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static /*inline*/ void mpu_set_region_num(unsigned int val)
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{
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__asm__ __volatile__ ("mcr p15, 0, %0, c6, c2, 0" : : "r" (val) : "memory", "cc");
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isb();
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}
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static /*inline*/ unsigned int mpu_get_region_base_addr(void)
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{
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unsigned int val;
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__asm__ __volatile__ ("mrc p15, 0, %0, c6, c1, 0" : "=r" (val) : : "memory", "cc");
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return val;
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}
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static /*inline*/ void mpu_set_region_base_addr(unsigned int val)
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{
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__asm__ __volatile__ ("mcr p15, 0, %0, c6, c1, 0" : : "r" (val) : "cc");
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isb();
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}
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static /*inline*/ unsigned int mpu_get_region_size(void)
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{
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unsigned int val;
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__asm__ __volatile__ ("mrc p15, 0, %0, c6, c1, 2" : "=r" (val) : : "memory", "cc");
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return (val & MPU_REGION_SIZE_MASK) >> 1;
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}
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static /*inline*/ void mpu_set_region_size(unsigned int size)
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{
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unsigned val;
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__asm__ __volatile__ ("mrc p15, 0, %0, c6, c1, 2" : "=r" (val) : : "memory", "cc");
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val = (val & ~MPU_REGION_SIZE_MASK) | (size << 1);
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__asm__ __volatile__ ("mcr p15, 0, %0, c6, c1, 2" : : "r" (val) : "cc");
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isb();
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}
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static /*inline*/ unsigned int mpu_get_region_size_enable(void)
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{
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unsigned int val;
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__asm__ __volatile__ ("mrc p15, 0, %0, c6, c1, 2" : "=r" (val) : : "memory", "cc");
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return val;
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}
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static /*inline*/ unsigned int mpu_get_region_access_ctrl(void)
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{
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unsigned int acc_ctrl;
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__asm__ __volatile__ ("mrc p15, 0, %0, c6, c1, 4" : "=r" (acc_ctrl) : : "memory", "cc");
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return acc_ctrl;
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}
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static /*inline*/ void mpu_set_region_access_ctrl(unsigned int acc_ctrl)
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{
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__asm__ __volatile__ ("mcr p15, 0, %0, c6, c1, 4" : : "r" (acc_ctrl) : "cc");
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isb();
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}
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static /*inline*/ void mpu_enable_region(unsigned int num, unsigned int enable)
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{
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unsigned val;
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mpu_set_region_num(num);
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__asm__ __volatile__ ("mrc p15, 0, %0, c6, c1, 2" : "=r" (val) : : "memory", "cc");
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if (enable) {
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val |= MPU_REGION_ENABLE;
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}
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else {
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val &= ~MPU_REGION_ENABLE;
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}
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__asm__ __volatile__ ("mcr p15, 0, %0, c6, c1, 2" : : "r" (val) : "cc");
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isb();
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}
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#endif
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extern int mpu_set_region(unsigned int num, unsigned int base, unsigned int size, unsigned int acc_ctrl);
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int set_mpu_reg_background(int access );
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int set_mpu_reg_itcm(void);
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int set_mpu_reg_dtcm(void);
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int set_mpu_reg_flash(size_t size);
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int set_mpu_reg_asic_reg(void);
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int set_mpu_reg_psram(unsigned int enable_cache);
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int set_mpu_reg_squ(void);
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int set_mpu_reg_arom(void);
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int reset_all_mpu_reg(void);
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int reset_mpu_reg(int num);
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#endif /* _SYSTEM_H_ */
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