230 lines
4.2 KiB
C
230 lines
4.2 KiB
C
/******************************************************************************
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** (C) Copyright 2007 Marvell International Ltd. ?
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**?All Rights Reserved
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**
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** FILENAME: PlatformConfig.h
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**
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** PURPOSE: Platform specific header to set parameters
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**
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**
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******************************************************************************/
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#ifndef __platform_config_h
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#define __platform_config_h
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#include "Typedef.h"
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#include "Errors.h"
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#include "smemc.h"
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//
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// Timers
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#define APB_CU_ENABLE (*APB_CU_CR = 0x33)
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#define TIMER_FREQ(A) (((A)*13) >> 2)
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// MMC
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#define NUMBER_OF_SUPPORTED_SDMMC_CONFIGURATIONS 1
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// SPI
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#define SSP_BASE_FOR_SPI SSP3_BASE
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#define spi_reg_bit_set(reg, val)
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#define spi_reg_bit_clr(reg, val)
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#define SSP_RX_DMA_DEVICE DMAC_SSP_2_RX
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#define SSP_TX_DMA_DEVICE DMAC_SSP_2_TX
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//
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// Clock in nanoseconds. Not likely to be changing all that often...
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//
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#define NAND_CONTROLLER_CLOCK 104 // MHz
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#define UARTCLK 14745600
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#define PlatformISRAMLimit 0x12000 //768KB - 76KB (0xC0000 - 0x13000)
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//
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// Clock in nanoseconds. Not likely to be changing all that often...
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//
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#define DFC_WORKAROUND 0
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// Bit 19 of control register must be written as 0
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//#define DFC_INITIAL_CONTROL 0xCC021FFF
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#define DFC_INITIAL_CONTROL 0x8C821FFF
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#define DFC_INITIAL_TIMING0 0x003F3F3F
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#define DFC_INITIAL_TIMING1 0x100080FF //tR set to 52.4 usec
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#define TIMOffset_CS0 0x00000000 // offset for TIM on CS0
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#define CHIPBOOTTYPE (volatile unsigned long *)GEU_FUSE_VAL_APCFG1
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#define ASCR (volatile unsigned long *)PMUM_CPSR //See PMUM.h
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#define ARSR (volatile unsigned long *)PMUM_CRSR
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#define AD3SR (volatile unsigned long *)PMUM_AWUCRS
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#define AD3R (volatile unsigned long *)PMUM_AWUCRM
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#define APBC_AIB_CLK_RST (volatile unsigned long *)0xD401503C
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#define APPS_PAD_BASE 0xd401e000
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#define SMEMC_BASE SMC_BASE
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// OneNand boots from CS0 only
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#define FLEX_BOOTRAM_MAIN_BASE CS0Base
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//
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// Multifunction Padring Structures
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//
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typedef struct
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{
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volatile int * registerAddr;
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unsigned int regValue;
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unsigned int defaultValue;
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}CS_REGISTER_PAIR_S, *P_CS_REGISTER_PAIR_S;
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//Prototypes
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UINT_T ChipSelect2(void);
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UINT_T ChipSelect0(void);
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void ChipSelectDFC(void);
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void RestoreDefaultConfig(void);
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void SaveDefaultConfig(void);
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void ChipSelectOneNAND( void );
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void ChipSelectMsys( void );
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UINT_T PlatformMdocRdyForXIPAccess( void );
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//void PlatformResumeSetup(pQuick_Resume_Function *, pTim_Resume_Function *);
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UINT_T getPlatformPortSelection(unsigned int *);
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UINT8_T* GetProbeOrder(void);
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UINT_T PlatformUARTConfig(void);
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UINT_T PlatformAltUARTConfig(void);
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#if 0
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//UDC 1.1 Functions
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UINT_T SetupSingleEndedPort2(void);
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UINT_T PlatformUsbTransmit(UINT_T, UINT8_T*);
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void PlatformUsbInit(UINT_T);
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void PlatformUsbShutdown(void);
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void PlatformUsbDmaHandler(void);
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void PlatformUsbInterruptHandler(void);
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//U2D Functions
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void PlatformU2DInit(void);
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UINT_T PlatformU2DTransmit(UINT_T, UINT8_T*, UINT_T);
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void PlatformU2DShutdown(void);
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void PlatformU2DInterruptHandler(void);
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//CI2 USB Functions
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void PlatformCI2Init(void);
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UINT_T PlatformCI2Transmit(UINT_T, UINT8_T*, UINT_T);
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void PlatformCI2Shutdown(void);
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void PlatformCI2InterruptHandler(void);
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#endif
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// DCB added these to get things compiling
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//------------------------------------------
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#define PLATFORM_CHIPBOOTTYPE_FUSE_REG 2
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UINT_T CheckSuperSetPortEnablement(UINT_T Port);
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//UINT_T GetPlatformFuses(UINT_T platformFuses, pFUSE_SET pTBR_Fuse);
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UINT_T ReturnServicesFuses(UINT_T ServiceNumber);
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UINT_T PlatformUARTConfig(void);
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UINT_T PlatformAltUARTConfig(void);
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//specify if the platform requires save state for trusted operation
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UINT_T PlatformSaveStateRequired(void);
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//external prototypes
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#if 0
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extern UINT_T GetOSCR0(void);
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extern UINT_T OSCR0IntervalInSec(UINT_T Before, UINT_T After);
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extern UINT_T OSCR0IntervalInMilli(UINT_T Before, UINT_T After);
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extern UINT_T OSCR0IntervalInMicro(UINT_T Before, UINT_T After);
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#endif
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#endif |