305 lines
8.1 KiB
C
305 lines
8.1 KiB
C
#include "utilities.h"
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#include "psram.h"
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#include "bsp.h"
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#include "quec_cust_feature.h"
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extern int psram_read_mr(unsigned mr_addr, unsigned cs);
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void wb32Mb_psram_fast_refresh(void)
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{
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unsigned read_data = 0;
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__asm {DSB};
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PSRAM_REG32(PSRAM_BASE + 0x8024) &= ~(0xf<<12);
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PSRAM_REG32(PSRAM_BASE + 0x9024) &= ~(0xf<<12);
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PSRAM_REG32(PSRAM_BASE + 0x8024) |= (0x4<<12);
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PSRAM_REG32(PSRAM_BASE + 0x9024) |= (0x5<<12);
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// write CR0 to take effect:
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PSRAM_REG32(PSRAM_BASE + 0x8034) = 0x1000;
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PSRAM_REG32(PSRAM_BASE + 0x8030) = 0x10a;
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read_data = PSRAM_REG32(PSRAM_BASE + 0x8030);
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while ((read_data & 0x100) != 0x0) {
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read_data = PSRAM_REG32(PSRAM_BASE + 0x8030);
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}
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return;
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}
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#pragma arm section code="PSRAM_WB32_HALFSLEEP"
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void wb32Mb_psram_halfsleep_config(void)
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{
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#define WBD_32Mb
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/*[REG_C: SEQ_TABLE]*/ // WBD LUT 'h7: WR MR6 hybird sleep entry!
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/*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x8100) = 0x93188460;
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/*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x8104) = 0x84ff8f10;
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/*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x8108) = 0x240284e2;
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#ifdef WBD_32Mb
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/*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x8104) = 0xc400cf10;
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/*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x8108) = 0x2402c460;
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#endif // WBD_32Mb
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/*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x810c) = 0x0;
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//LOG_INFO("!!! WB32Mb psram hybrid sleep entry right @@@@ !!! \n");
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/*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x810c) = 0x0;
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/*[REG_C: SEQ_TABLE]*/ // LUT 'h8: CEN low halfsleep exit!
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/*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x8110) = 0x22012880;
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/*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x8114) = 0x2c056210;
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/*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x8118) = 0x0;
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return;
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}
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#pragma arm section code
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#if !defined(LTEONLY_THIN_SINGLE_SIM_2MFLASH)
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#pragma arm section code="PSRAMWRTESTMODE"
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void psram_wr_testmode(void)
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{
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/*[REG_C: SEQ_TABLE]*/ // WBD LUT 'hb: WR TESTMODE!
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/*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x8140) = 0xc400c440;
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/*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x8144) = 0x4400cb20;
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/*[REG_C: SEQ_TABLE]*/ PSRAM_REG32(PSRAM_BASE + 0x8148) = 0x0;
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}
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#pragma arm section code
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int psram_write_testmode(unsigned seq_addr)
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{
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unsigned read_data = 0;
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PSRAM_REG32(PSRAM_BASE + 0x8034) = seq_addr;
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PSRAM_REG32(PSRAM_BASE + 0x8030) = 0x10b;
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read_data = PSRAM_REG32(PSRAM_BASE + 0x8030);
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while ((read_data & 0x100) != 0x0) {
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read_data = PSRAM_REG32(PSRAM_BASE + 0x8030);
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}
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return read_data;
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}
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int winbond_psram_fast_refresh_entry(void)
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{
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psram_write_testmode(0xA4A00008);//STEP1
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psram_write_testmode(0x04000008);//STEP2
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psram_write_testmode(0x04000008);//STEP3
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psram_write_testmode(0xA4A00008);//STEP4
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psram_write_testmode(0x14900008);//STEP5
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psram_write_testmode(0x04c00008);//STEP6
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return 0;
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}
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int winbond_psram_fast_refresh_entry_test(void)
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{
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unsigned reg = 0;
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__asm {DSB};
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reg = PSRAM_REG32(PSRAM_BASE + 0x4010);
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reg |= (1<<12);
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PSRAM_REG32(PSRAM_BASE + 0x4010) = reg;
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PSRAM_REG32(PSRAM_BASE + 0x0004) = 0x7E68F001;
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winbond_psram_fast_refresh_entry();
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PSRAM_REG32(PSRAM_BASE + 0x0004) = 0x7E684001;
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reg = PSRAM_REG32(PSRAM_BASE + 0x4010);
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reg &= ~(1<<12);
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PSRAM_REG32(PSRAM_BASE + 0x4010) = reg;
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return 0;
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}
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int winbond_psram_fast_refresh_exit(void)
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{
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psram_write_testmode(0xA4A00008);//STEP1
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psram_write_testmode(0x54600008);//STEP2
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psram_write_testmode(0x04000008);//STEP3
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return 0;
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}
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int winbond_psram_fast_refresh_exit_test(void)
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{
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unsigned reg = 0;
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__asm {DSB};
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reg = PSRAM_REG32(PSRAM_BASE + 0x4010);
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reg |= (1<<12);
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PSRAM_REG32(PSRAM_BASE + 0x4010) = reg;
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PSRAM_REG32(PSRAM_BASE + 0x0004) = 0x7E68F001;
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winbond_psram_fast_refresh_exit();
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PSRAM_REG32(PSRAM_BASE + 0x0004) = 0x7E684001;
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reg = PSRAM_REG32(PSRAM_BASE + 0x4010);
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reg &= ~(1<<12);
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PSRAM_REG32(PSRAM_BASE + 0x4010) = reg;
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return 0;
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}
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static int psram_read_mr(unsigned mr_addr, unsigned cs)
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{
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unsigned read_data = 0;
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// read MR register
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PSRAM_REG32(PSRAM_BASE + 0x8034) = mr_addr + (cs << 23);
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PSRAM_REG32(PSRAM_BASE + 0x8030) = 0x109;
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read_data = PSRAM_REG32(PSRAM_BASE + 0x8030);
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while ((read_data & 0x100) != 0x0) {
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read_data = PSRAM_REG32(PSRAM_BASE + 0x8030);
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}
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read_data = PSRAM_REG32(PSRAM_BASE + 0x8038); // this is the mr read data value
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RTI_LOG("RB: MR0x%x_CS%d: @[0x%08X]=[0x%08X]\r\n", mr_addr, cs, (PSRAM_BASE + 0x8034), PSRAM_REG32(PSRAM_BASE + 0x8034));
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RTI_LOG("RB: MR0x%x_CS%d: @[0x%08X]=[0x%08X]\r\n", mr_addr, cs, (PSRAM_BASE + 0x8038), read_data);
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return read_data;
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}
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int psram_fast_refresh_exit(void)
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{
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#if 0
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unsigned char psram_type = getPsramType();
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//RTI_LOG("psram_fast_refresh_exit,psram_type: %d\r\n",psram_type);
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switch (psram_type) {
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//case WB_8M8M:
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//case WB_250MHZ_8M8M:
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case WB_8M:
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case WB_250MHZ_8M:
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winbond_psram_fast_refresh_exit_test();
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//psram_read_mr(0x1002, 0);
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//psram_read_mr(0x1002, 1);
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break;
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#if 0
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case WB_4M:
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psram_read_mr(0x1000,0);
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break;
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#endif
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default:
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break;
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}
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#endif
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return 0;
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}
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int psram_fast_refresh_entry(void)
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{
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#if 0
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unsigned char psram_type = getPsramType();
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//RTI_LOG("psram_fast_refresh_entry,psram_type: %d\r\n",psram_type);
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switch (psram_type) {
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//case WB_8M8M:
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//case WB_250MHZ_8M8M:
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case WB_8M:
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case WB_250MHZ_8M:
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winbond_psram_fast_refresh_entry_test();
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//psram_read_mr(0x1002, 0);
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//psram_read_mr(0x1002, 1);
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break;
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#if 0
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case WB_4M:
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psram_read_mr(0x1000,0);
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break;
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#endif
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default:
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break;
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}
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#endif
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return 0;
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}
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#endif
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int crane_psram_init(void)
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{
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#if !defined(LTEONLY_THIN_SINGLE_SIM_2MFLASH)
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unsigned long read_data = 0;
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#endif
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unsigned char psram_type = getPsramType();
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switch (psram_type) {
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#if !defined(LTEONLY_THIN_SINGLE_SIM_2MFLASH)
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/************************************************/
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/************************************************/
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//bug:212193,move WB_8M8M psram config from cinit1 function, fix get wrong psram type
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case WB_8M8M:
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read_data = PSRAM_REG32(PSRAM_BASE + 0x8000);
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read_data &= 0xff00ffff;
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read_data |= (5<<16)|(5<<20);
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PSRAM_REG32(PSRAM_BASE + 0x8000) = read_data;
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break;
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/************************************************/
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/************************************************/
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/************************************************/
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case WB_8M:
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case WB_250MHZ_8M:
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//case WB_8M8M:
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//case WB_250MHZ_8M8M:
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//psram_wr_testmode();
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//winbond_psram_fast_refresh_exit_test();
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#ifdef QUECTEL_PROJECT_CUST //quectelĬÈÏʹÄÜ8M psram fast refresh
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psram_wr_testmode();
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winbond_psram_fast_refresh_entry_test();
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#endif //QUECTEL_PROJECT_CUST
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break;
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case AP_8M:
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case AP_250MHZ_8M:
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//case AP_8M8M:
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//case AP_250MHZ_8M8M:
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//case AP_16M:
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PSRAM_REG32(0xC0108024) &= 0xFF00FFFF;
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PSRAM_REG32(0xC0109024) &= 0xFF00FFFF;
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PSRAM_REG32(0xC0108024) |= 0x480000;
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PSRAM_REG32(0xC0109024) |= 0x280000;
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AP8M_psram_lpm_table();
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break;
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#endif
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case WB_4M:
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wb32Mb_psram_halfsleep_config();
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wb32Mb_psram_fast_refresh();
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WB4M_psram_lpm_table();
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break;
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case AP_4M:
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AP4M_psram_lpm_table();
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break;
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default:
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break;
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}
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if(CHIP_IS_CRANELR || CHIP_IS_CRANELS || CHIP_IS_CRANELG || CHIP_IS_CRANELRH)
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{
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unsigned int reg_val = 0;
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reg_val = PSRAM_REG32(0xD4090128);
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reg_val &=~(0x3<<28);
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reg_val |= (0x1<<28); // change psram pad to pull down
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PSRAM_REG32(0xD4090128) = reg_val;
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}
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return 0;
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}
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