592 lines
20 KiB
C
592 lines
20 KiB
C
#ifndef FREQCHANGE_H
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#define FREQCHANGE_H
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#include "common.h"
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//#include "gbl_types.h"
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//#include "acipc.h"
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typedef enum
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{
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DDR_FREQUENCY_156,
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DDR_FREQUENCY_312,
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DDR_FREQUENCY_400,
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DDR_FREQUENCY_416 = DDR_FREQUENCY_400,
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DDR_FREQUENCY_528,
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DDR_FREQUENCY_624,
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DDR_FREQUENCY_667_800,
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DDR_FREQUENCY_INVALID
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} DDR_FREQUENCY;
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#define BU_REG_READ(x) (*(volatile unsigned long *)(x))
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#define BU_REG_WRITE(x,y) ((*(volatile unsigned long *)(x)) = y )
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/***************freq_change*/
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#define PMUA_DM_CC_CP 0xd4282808
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#define PMUA_CP_IMR 0xd4282870
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#define PMUA_CC_CP 0xd4282800
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#define PMUA_CC_AP 0xd4282804
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#define PMUA_CP_ISR 0xd4282878
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#define PMU_FCCR_T 0xd4050008
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#define PMUA_CP_STATUS 0xd42828c4
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#define PMUA_AP_ISR 0xd42828a0
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#define PMU_PLL2CR 0xd4050034
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#define PP_MAX_NUM 8
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#define PP_MAX_NUM_NZ3 18
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#if defined(NEZHA3_1826)
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#define CPMU_DVC_CP (0xD0250000+0x0080)
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#define CPMU_DVC_DP (0xD0250000+0x0084)
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#define PMU_DVC_AP (0xd4050000+0x2020)
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#define PMU_DVC_APSUB (0xd4050000+0x202C)
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#define PMU_DVC_CHIP (0xd4050000+0x2030)
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#define CP_DVC_LV_MASK ((CHIP_IS_HELAN4_A0 || CHIP_IS_NEZHA3_A0) ? 0xf : 0x7)//Helan4 or not
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#define CP_DVC_ACTIVE_OFF ((CHIP_IS_HELAN4_A0 || CHIP_IS_NEZHA3_A0) ? 8 : 4) //Helan4 or not
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#define CP_DVC_CHG_REQ ((CHIP_IS_HELAN4_A0 || CHIP_IS_NEZHA3_A0) ? 15 : 7) //Helan4 or not
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#endif
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#define PMU_DVC_CTRL 0xd4052000
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#define PMU_DVC_STBL_0_1 0xd4052004
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#define PMU_DVC_STBL_1_2 0xd4052008
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#define PMU_DVC_STBL_2_3 0xd405200C
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#define PMU_DVC_CP 0xd4052024
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#define PMU_DVC_DSP 0xd4052028
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#define PMU_DVC_IMR 0xd4052050
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#define PMU_DVC_ISR 0xd4052054
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#define PMU_DVC_STATUS 0xd4052040
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#define PMU_DVC_EX_STR 0xd405205C
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#define PMU_CCGR_T (0xd4050000+0x0024)
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#define PMUA_DM_CC_AP (0xD4282800+0x000C)
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#define PMUA_DFC_AP (0xD4282800+0x0180)
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#define PMUA_DFC_CP (0xD4282800+0x0184)
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#define PMUA_DFC_STATUS (0xD4282800+0x0188)
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#define PMUA_DFC_LEVEL0 (0xD4282800+0x0190)
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#define PMUA_DFC_LEVEL1 (0xD4282800+0x0194)
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#define PMUA_DFC_LEVEL2 (0xD4282800+0x0198)
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#define PMUA_DFC_LEVEL3 (0xD4282800+0x019C)
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#define PMUA_DFC_LEVEL4 (0xD4282800+0x01A0)
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#define PMUA_DFC_LEVEL5 (0xD4282800+0x01A4)
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#define PMUA_DFC_LEVEL6 (0xD4282800+0x01A8)
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#define PMUA_DFC_LEVEL7 (0xD4282800+0x01AC)
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#define MAX_PPNUM 4 /* ULC */
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#define MAX_DFCLVL_NUM 5
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#define DFC_MAGIC_FLAG 0x4446434C
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#define MAX_CPDVC_NUM_V1 5
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#define DVC_MAGIC_V1 0x44564301
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#if defined(NEZHA3_1826)
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#define CPMU_DFC_CP (0xD0250000+0x0090)
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#define CPMU_DFC_DP (0xD0250000+0x0094)
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#define CPMU_DFC_STATUS (0xD0250000+0x0098)
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#endif
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#ifdef EDEN_1928
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#define CPMU_DDRDFC_CTRL 0xD025003C
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#define CPMU_DVC 0xD025009C
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#define DFC_INT (1u<<31)
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#define DFC_INT_MSK (1<<30)
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#define DFC_INT_CLR (1<<29)
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#define DFC_INT_PROGRESS (1<<28)
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#define DFC_HW_EN (1<<5)
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#endif
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#if defined(NEZHA3_1826)
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#define HWDFC_ENABLE 1
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#else
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#define HWDFC_ENABLE 0
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#endif
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//ICAT EXPORTED ENUM
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typedef enum {
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_HWDFC_TEST_DISABEL=0,
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_HWDFC_TEST_ACTIVE_LPM_CORE,
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_HWDFC_TEST_ACTIVE_LPM,
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_HWDFC_TEST_ACTIVE,
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_HWDFC_TEST_CORE,
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_HWDFC_TEST_NEW_API,
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} HWDFC_TEST_TYPE;
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typedef enum
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{
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cpu_PLL1_156MHZ = 0x0, //PPL1:624,DIV:4;
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cpu_PLL1_208MHZ = 0x1, //PPL1:624,DIV:3; PPL1:832,DIV:4;
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cpu_PLL1_312MHZ = 0x2, //PPL1:624,DIV:2;
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cpu_PLL1_416MHZ = 0x3, //PPL1:832,DIV:2;
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cpu_PLL1_624MHz = 0x4,
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cpu_PLL1_832MHz = 0x5,
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cpu_PLL1_1248MHz = 0x6,
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cpu_PLL2 = 0x7,
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cpu_PLL2P = 0x8,
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cpu_PLL_NO_SET = 0xFF,
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}CPU_PLL_T;
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//ICAT EXPORTED ENUM
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typedef enum {
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_HWDFC_DISABEL=0,
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_HWDFC_ENABLE,
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} HWDFC_TYPE;
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typedef enum
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{
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core_PLL1_416MHz = 0x0,
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core_PLL1_624MHz = 0x1,
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core_PLL2 = 0x2,
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core_PLL1_312MHz = 0x3,
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core_PLL_NO_SET = 0xFF,
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} CORE_PLL_FREQ_T;
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typedef enum
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{
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ACLK_PLL1_416MHz = 0x0,
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ACLK_PLL1_624MHz = 0x1,
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ACLK_PLL2 = 0x2,
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ACLK_PLL1_312MHz = 0x3,
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} ACLK_PLL_FREQ_T;
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typedef enum
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{
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core_PLL1_832MHz = 0x0,
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core_PLL1_1248MHz = 0x1,
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core_PLL2OUT = 0x2,
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core_PLL2P = 0x3,
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} CORE_PLL_FREQ_Nezha2_T;
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typedef enum
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{
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DCLK_PLL1_416MHz = 0x0,
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DCLK_PLL1_624MHz = 0x1,
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DCLK_PLL2 = 0x2,
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DCLK_PLL2_DIV_2_5 = 0x3,
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} DCLK_PLL_FREQ_T;
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//ICAT EXPORTED ENUM
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typedef enum {
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CFG_PP_0 = 0,
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CFG_PP_1,
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CFG_PP_2,
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CFG_PP_3,
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CFG_PP_4,
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CFG_PP_5,
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CFG_PP_6,
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CFG_PP_7,
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CFG_PP_AUTO = 0xFF, // CQ00023417
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} PP_TYPE;
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// ICAT EXPORTED ENUM - add by zhangwl for PP chang - CQ00023417
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typedef enum {
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CPIDLE_0_5 = 5,
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CPIDLE_1_0 = 10,
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CPIDLE_1_5 = 15,
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CPIDLE_2_0 = 20,
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CPIDLE_2_5 = 25,
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CPIDLE_3_0 = 30,
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CPIDLE_3_5 = 35,
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CPIDLE_4_0 = 40,
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CPIDLE_4_5 = 45,
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CPIDLE_5_0 = 50,
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CPIDLE_5_5 = 55,
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CPIDLE_6_0 = 60,
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CPIDLE_6_5 = 65,
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CPIDLE_7_0 = 70,
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CPIDLE_7_5 = 75,
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CPIDLE_8_0 = 80,
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CPIDLE_8_5 = 85,
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CPIDLE_9_0 = 90,
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CPIDLE_9_5 = 95,
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CPIDLE_DEFAULT = 0xFF,
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} PP_CPIDLE_T;
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//ICAT EXPORTED ENUM
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typedef enum {
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LTE_DMA_78M = 0x7F,
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LTE_DMA_156M = 0x5F,
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LTE_DMA_208M = 0x4B,
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LTE_DMA_312M = 0x4F,
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} LTE_DMA_CLOCK;
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//ICAT EXPORTED ENUM
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typedef enum
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{
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VOLTAGE_0_65 = 0x04,
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VOLTAGE_0_70 = 0x08,
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VOLTAGE_0_75 = 0x0C,
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VOLTAGE_0_775 = 0x0E,
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VOLTAGE_0_7875 = 0x0F,
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VOLTAGE_0_80 = 0x10,
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VOLTAGE_0_8125 = 0x11,
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VOLTAGE_0_825 = 0x12,
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VOLTAGE_0_8375 = 0x13,
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VOLTAGE_0_85 = 0x14,
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VOLTAGE_0_8625 = 0x15,
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VOLTAGE_0_875 = 0x16,
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VOLTAGE_0_8875 = 0x17,
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VOLTAGE_0_90 = 0x18,
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VOLTAGE_0_9125 = 0x19,
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VOLTAGE_0_925 = 0x1A,
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VOLTAGE_0_9375 = 0x1B,
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VOLTAGE_0_95 = 0x1C,
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VOLTAGE_0_9625 = 0x1D,
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VOLTAGE_0_975 = 0x1E,
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VOLTAGE_0_9875 = 0x1F,
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VOLTAGE_1_00 = 0x20,
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VOLTAGE_1_0125 = 0x21,
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VOLTAGE_1_025 = 0x22,
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VOLTAGE_1_0375 = 0x23,
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VOLTAGE_1_05 = 0x24,
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VOLTAGE_1_0625 = 0x25,
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VOLTAGE_1_075 = 0x26,
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VOLTAGE_1_0875 = 0x27,
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VOLTAGE_1_10 = 0x28,
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VOLTAGE_1_1125 = 0x29,
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VOLTAGE_1_125 = 0x2A,
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VOLTAGE_1_1375 = 0x2B,
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VOLTAGE_1_15 = 0x2C,
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VOLTAGE_1_1625 = 0x2D,
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VOLTAGE_1_175 = 0x2E,
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VOLTAGE_1_1875 = 0x2F,
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VOLTAGE_1_20 = 0x30,
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VOLTAGE_1_2125 = 0x31,
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VOLTAGE_1_225 = 0x32,
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VOLTAGE_1_2375 = 0x33,
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VOLTAGE_1_25 = 0x34,
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VOLTAGE_1_2625 = 0x35,
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VOLTAGE_1_275 = 0x36,
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VOLTAGE_1_2875 = 0x37,
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VOLTAGE_1_30 = 0x38,
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VOLTAGE_1_35 = 0x3C,
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VOLTAGE_DEFAULT = 0xFF,
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} PP_VOLTAGE_T;
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//ICAT EXPORTED ENUM
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typedef enum
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{
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MIPS_5 = 5,
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MIPS_1_0 = 10,
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MIPS_1_5 = 15,
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MIPS_2_0 = 20,
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MIPS_2_5 = 25,
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MIPS_3_0 = 30,
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MIPS_3_5 = 35,
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MIPS_4_0 = 40,
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MIPS_4_5 = 45,
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MIPS_5_0 = 50,
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MIPS_5_5 = 55,
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MIPS_6_0 = 60,
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MIPS_6_5 = 65,
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MIPS_7_0 = 70,
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MIPS_7_5 = 75,
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MIPS_8_0 = 80,
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MIPS_8_5 = 85,
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MIPS_9_0 = 90,
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MIPS_9_5 = 95,
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MIPS_MAX = 0xFF,
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} Mips_Threshold;
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//ICAT EXPORTED STRUCT
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typedef struct {
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PP_TYPE ProductPoint;
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Mips_Threshold HighWaterMark; //add by zhangwl for PP chang - CQ00023417
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Mips_Threshold LowWaterMark; //add by zhangwl for PP chang - CQ00023417
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LTE_DMA_CLOCK LTEDmaClock;
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PP_VOLTAGE_T ActiveVoltage;
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PP_VOLTAGE_T SleepVoltage;
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} LTE_CONFIG_S;
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typedef struct
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{
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CORE_PLL_FREQ_T core_PLL_use;
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ACLK_PLL_FREQ_T aclk_PLL_use;
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DCLK_PLL_FREQ_T dclk_PLL_use;
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UINT16 PLL2_value;
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UINT8 PCLK_div;
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UINT8 XPCLK_div;
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UINT8 PDCLK_div;
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UINT8 ACLK_div;
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UINT8 DCLK_div;
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UINT8 DCLK_SYNC;
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PP_VOLTAGE_T PP_Voltage;
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} ProductPoint_T;
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typedef struct
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{
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CORE_PLL_FREQ_Nezha2_T core_PLL_use;
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ACLK_PLL_FREQ_T aclk_PLL_use;
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DCLK_PLL_FREQ_T dclk_PLL_use;
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UINT16 PLL2_value;
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UINT8 PCLK_div;
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UINT8 XPCLK_div;
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UINT8 PDCLK_div;
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UINT8 ACLK_div;
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UINT8 DCLK_div;
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UINT8 DCLK_SYNC;
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PP_VOLTAGE_T PP_Voltage;
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} ProductPoint_Nezha2_T;
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#ifdef NEZHA3_1826
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typedef enum
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{
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CP_PLL1_416MHz = 0x0,
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CP_PLL1_624MHz = 0x1,
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CP_PLL1_832MHz = 0x2,
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CP_PLL2OUT = 0x3,
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} CORE_PLL_FREQ_Nezha3_T;
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typedef enum
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{
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CP_ACLK_312MHz = 0x0,
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CP_ACLK_416MHz = 0x1,
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} ACLK_PLL_FREQ_Nezha3_T;
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typedef struct
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{
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CORE_PLL_FREQ_Nezha3_T core_PLL_use;
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ACLK_PLL_FREQ_Nezha3_T cpss_aclk_PLL_use;
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ACLK_PLL_FREQ_Nezha3_T lte_aclk_PLL_use;
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DCLK_PLL_FREQ_T dclk_PLL_use;
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UINT16 PLL2_value;
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UINT8 PCLK_div;
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UINT8 bus_clk_div;
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UINT8 mem_clk_div;
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UINT8 CPSS_ACLK_div;
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UINT8 LTE_ACLK_div;
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UINT8 DCLK_div;
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PP_VOLTAGE_T PP_Voltage;
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} ProductPoint_Nezha3_T;
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typedef enum
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{
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LTE_ACLK_624MHz = 0x0,
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LTE_ACLK_416MHz = 0x1,
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} LTE_ACLK_PLL_FREQ_Nezha3_Z3_T;
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typedef enum
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{
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CPSS_ACLK_312MHz = 0x0,
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CPSS_ACLK_416MHz = 0x1,
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} CPSS_ACLK_PLL_FREQ_Nezha3_Z3_T;
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typedef struct
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{
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CORE_PLL_FREQ_Nezha3_T core_PLL_use;
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CPSS_ACLK_PLL_FREQ_Nezha3_Z3_T cpss_aclk_PLL_use;
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LTE_ACLK_PLL_FREQ_Nezha3_Z3_T lte_aclk_PLL_use;
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DCLK_PLL_FREQ_T dclk_PLL_use;
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UINT16 PLL2_value;
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UINT8 PCLK_div;
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UINT8 bus_clk_div;
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UINT8 mem_clk_div;
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UINT8 CPSS_ACLK_div;
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UINT8 LTE_ACLK_div;
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UINT8 DCLK_div;
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PP_VOLTAGE_T PP_Voltage;
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} ProductPoint_Nezha3_Z3_T;
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#endif
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typedef enum
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{
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FC_OK,
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FC_PP_NOT_EXIST,
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FC_ERROR,
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FC_NOT_SUPPORT,
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} FC_RTN_CODE_T;
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typedef enum
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{
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CP_DVC_LV0 = 0,
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CP_DVC_LV1 = 1,
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CP_DVC_LV2 = 2,
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CP_DVC_LV3 = 3,
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CP_DVC_LV4 = 4,
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CP_DVC_LV5 = 5,
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CP_DVC_LV6 = 6,
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CP_DVC_LV7 = 7,
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CP_DVC_LV8 = 8,
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CP_DVC_LV9 = 9,
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CP_DVC_LV10 = 10,
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CP_DVC_LV11 = 11,
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CP_DVC_LV12 = 12,
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CP_DVC_LV13 = 13,
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CP_DVC_LV14 = 14,
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CP_DVC_LV15 = 15,
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CP_DVC_NO_SET = 0xFF,
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} CP_DVC_LEVEL ;
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typedef enum
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{
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DSP_DVC_LV0 = 0,
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DSP_DVC_LV1 = 1,
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DSP_DVC_LV2 = 2,
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DSP_DVC_LV3 = 3,
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DSP_DVC_LV4 = 4,
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DSP_DVC_LV5 = 5,
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DSP_DVC_LV6 = 6,
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DSP_DVC_LV7 = 7,
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DSP_DVC_LV8 = 8,
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DSP_DVC_LV9 = 9,
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DSP_DVC_LV10 = 10,
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DSP_DVC_LV11 = 11,
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DSP_DVC_LV12 = 12,
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DSP_DVC_LV13 = 13,
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DSP_DVC_LV14 = 14,
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DSP_DVC_LV15 = 15,
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DSP_DVC_NO_SET = 0xFF,
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} DSP_DVC_LEVEL ;
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typedef enum
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{
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SVC_VL0 = 0,
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SVC_VL1,
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SVC_VL2,
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SVC_VL3,
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} CRN_SVC_e;
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#define REGS_GEU_BASE 0xD4201000
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#define EFUSE_DATA_BASE REGS_GEU_BASE /* efuse bank base address */
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#define REG_GEU_GEU_STATUS ASR_ADDR(REGS_GEU_BASE, 0X000)/*GEU Status Register*/
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#define REG_GEU_GEU_CONFIG ASR_ADDR(REGS_GEU_BASE, 0X004)/*GEU Configuration Register*/
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#define REG_GEU_GEU_INIT_KEY_VALUE ASR_ADDR(REGS_GEU_BASE,0X008)/*GEU Initial Key Value Register*/
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#define REG_GEU_GEU_INPUT_DATA_ENC_DEC ASR_ADDR(REGS_GEU_BASE, 0X028)/*Input Data for Encryption/Decryption Register*/
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#define REG_GEU_GEU_FUSE_PROG_VAL1 ASR_ADDR(REGS_GEU_BASE, 0X038)/*Fuse Programming Value[127:0] in Software Fuse Programming Mode Register*/
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#define REG_GEU_GEU_FUSE_PROG_VAL2 ASR_ADDR(REGS_GEU_BASE, 0X048)/*Fuse Programming Value[255:128] in Software Fuse Programming Mode Register*/
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#define REG_GEU_GEU_OUT_DATA_AFTER_ENC_DEC ASR_ADDR(REGS_GEU_BASE, 0X058)/*Output Data after Encryption/Decryption Register*/
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#define REG_GEU_GEU_SRAM_SPACE_ROUND_KEY_TABLE ASR_ADDR(REGS_GEU_BASE, 0X068)/*SRAM Space for Round Key Table Register*/
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#define REG_GEU_ROM_SPACE_SBOX_TABLE ASR_ADDR(REGS_GEU_BASE, 0X168)/*ROM Space for SBOX Table Register*/
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#define REG_GEU_GEU_ROM_SPACE_INV_SBOX_TABLE ASR_ADDR(REGS_GEU_BASE, 0X268)/*ROM Space for Inverse SBOX Table Register*/
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#define REG_GEU_GEU_OTP_DATA1 ASR_ADDR(REGS_GEU_BASE, 0X368)/*One Time Programmable Data Register 1*/
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#define REG_GEU_GEU_OTP_DATA2 ASR_ADDR(REGS_GEU_BASE, 0X36C)/*One Time Programmable Data Register 2*/
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#define REG_GEU_GEU_OTP_DATA3 ASR_ADDR(REGS_GEU_BASE, 0X370)/*One Time Programmable Data Register 3*/
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#define REG_GEU_GEU_OTP_DATA4 ASR_ADDR(REGS_GEU_BASE, 0X374)/*One Time Programmable Data Register 4*/
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#define REG_GEU_PRNG_CTRL_REG ASR_ADDR(REGS_GEU_BASE, 0X3a8)/*PRNG Control Register*/
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#define REG_GEU_GEU_FUSE_VAL_APCFG1 ASR_ADDR(REGS_GEU_BASE, 0X404)/*Fuse Value for Application Subsystem Config Register 1*/
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#define REG_GEU_GEU_FUSE_VAL_APCFG2 ASR_ADDR(REGS_GEU_BASE, 0X408)/*Fuse Value for Application Subsystem Config Register 2*/
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#define REG_GEU_GEU_FUSE_VAL_APCFG3 ASR_ADDR(REGS_GEU_BASE, 0X40C)/*Fuse Value for Application Subsystem Config Register 3*/
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#define REG_GEU_GEU_FUSE_BANK0_127_96 ASR_ADDR(REGS_GEU_BASE, 0X410)/*Fuse Bank0 127 96 Register*/
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#define REG_GEU_GEU_FUSE_BANK0_239_208 ASR_ADDR(REGS_GEU_BASE, 0X414)/*Fuse Bank0 239 208 Register*/
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#define REG_GEU_GEU_FUSE_BANK0_207_192 ASR_ADDR(REGS_GEU_BASE, 0X418)/*Fuse Bank0 207 192 Register*/
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#define REG_GEU_GEU_FUSE_BANK3_223_192 ASR_ADDR(REGS_GEU_BASE, 0X41c)/*Fuse Bank3 223 192 Register*/
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#define REG_GEU_GEU_FUSE_BANK3_255_224 ASR_ADDR(REGS_GEU_BASE, 0X420)/*Fuse Bank3 255 224 Register*/
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#define REG_GEU_GEU_FUSE_VAL_ROOT_KEY1 ASR_ADDR(REGS_GEU_BASE, 0X424)/*Fuse Value for Root Key Register 1*/
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#define REG_GEU_GEU_FUSE_VAL_ROOT_KEY2 ASR_ADDR(REGS_GEU_BASE, 0X428)/*Fuse Value for Root Key Register 2*/
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#define REG_GEU_GEU_FUSE_VAL_ROOT_KEY3 ASR_ADDR(REGS_GEU_BASE, 0X42C)/*Fuse Value for Root Key Register 3*/
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#define REG_GEU_GEU_FUSE_VAL_ROOT_KEY4 ASR_ADDR(REGS_GEU_BASE, 0X430)/*Fuse Value for Root Key Register 4*/
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#define REG_GEU_GEU_FUSE_VAL_ROOT_KEY5 ASR_ADDR(REGS_GEU_BASE, 0X434)/*Fuse Value for Root Key Register 5*/
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#define REG_GEU_GEU_FUSE_VAL_ROOT_KEY6 ASR_ADDR(REGS_GEU_BASE, 0X438)/*Fuse Value for Root Key Register 6*/
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#define REG_GEU_GEU_FUSE_VAL_ROOT_KEY7 ASR_ADDR(REGS_GEU_BASE, 0X43C)/*Fuse Value for Root Key Register 7*/
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#define REG_GEU_GEU_FUSE_VAL_ROOT_KEY8 ASR_ADDR(REGS_GEU_BASE, 0X440)/*Fuse Value for Root Key Register 8*/
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#define REG_GEU_GEU_FUSE_VAL_OEM_HASH_1_8 ASR_ADDR(REGS_GEU_BASE, 0X444)/*Fuse Value for OEM Hash Key Registers 1- 8*/
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#define REG_GEU_GEU_FUSE_STATUS ASR_ADDR(REGS_GEU_BASE, 0X484)/*Fuse Operation Status Register*/
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#define REG_GEU_GEU_HW_RANDOM_NUM_GEN ASR_ADDR(REGS_GEU_BASE, 0X488)/*Hardware Random Number Generator Register*/
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#define REG_GEU_GEU_FUSE_BANK0_191_160 ASR_ADDR(REGS_GEU_BASE, 0X48C)/*Fuse Bank0 191 160 Register*/
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#define REG_GEU_BLOCK3_RESERVED_0 ASR_ADDR(REGS_GEU_BASE, 0X490)/*Block 3 Reserved Fuse Bit Register 0*/
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#define REG_GEU_BLOCK3_RESERVED_1 ASR_ADDR(REGS_GEU_BASE, 0X494)/*Block 3 Reserved Fuse Bit Register 1*/
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#define REG_GEU_BLOCK3_RESERVED_2 ASR_ADDR(REGS_GEU_BASE, 0X498)/*Block 3 Reserved Fuse Bit Register 2*/
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#define REG_GEU_BLOCK3_RESERVED_3 ASR_ADDR(REGS_GEU_BASE, 0X49c)/*Block 3 Reserved Fuse Bit Register 3*/
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#define REG_GEU_BLOCK3_RESERVED_4 ASR_ADDR(REGS_GEU_BASE, 0X4A0)/*Block 3 Reserved Fuse Bit Register 4*/
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#define REG_GEU_BLOCK3_RESERVED_5 ASR_ADDR(REGS_GEU_BASE, 0X4A4)/*Block 3 Reserved Fuse Bit Register 5*/
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#define REG_GEU_GEU_FUSE_BANK0_159_128 ASR_ADDR(REGS_GEU_BASE, 0X4A8)/*Fuse Bank0 159 128 Register*/
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#define REG_GEU_GEU_FUSE_BANK0_255_240 ASR_ADDR(REGS_GEU_BASE, 0X4C8)/*Fuse Bank0 255 240 Register*/
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#define EFUSE_UUID_BASE REG_GEU_GEU_FUSE_VAL_APCFG1 /* bank 0,chip UUID */
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#define EFUSE_HUK_BASE REG_GEU_GEU_FUSE_VAL_ROOT_KEY1 /* bank 1,Hardware Unique Key */
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#define EFUSE_SSK_BASE REG_GEU_GEU_FUSE_VAL_OEM_HASH_1_8 /* bank 2,Secret Symmetric Key */
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#define EFUSE_BLOCK3_BASE REG_GEU_BLOCK3_RESERVED_0 /* bank3,Block 3 Reserved Fuse Bit Register 0*/
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#define GEU_CONFIG REG_GEU_GEU_CONFIG
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#define REG_PMU_PMU_AES_CLK_RES_CTRL 0xD4282868
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#define FUSE_BANK_SIZE (256/32)
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#define REG_MAIN_CCGR 0xD4050024
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#define SE_CLOCK_REG REG_PMU_PMU_AES_CLK_RES_CTRL //PMUap: PMU_AES_CLK_RES_CTRL
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/* bits definitions for register REG_GEU_GEU_CONFIG */
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#define BIT_STICKY_CONTROL_BIT ( BIT(30) )
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#define BIT_FUSE_POWER_BYPASS ( BIT(28) )
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#define BITS_FUSE_CLOCK_DIVIDER(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)) )
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#define BIT_FUSE_CLOCK_DISABLE ( BIT(23) )
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#define BIT_FUSE_SOFTWARE_RESET ( BIT(22) )
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#define BITS_FUSE_BLOCK_NUMBER(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)|BIT(21)) )
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#define BIT_HIGH_VOLT_ENABLE ( BIT(17) )
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#define BIT_BURN_FUSE_ENABLE ( BIT(16) )
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#define BIT_FUSE_LOCK ( BIT(15) )
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#define BIT_ENABLE_SOFT_FUSE_PROG ( BIT(14) )
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#define BIT_SEL_FUSE_B ( BIT(13) )
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#define BIT_GE_FUSE_READY205 ( BIT(1) )
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#define BIT_FUSE_BURN_DONE ( BIT(0) )
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#define STICKY_CONTROL_BIT BIT_STICKY_CONTROL_BIT
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#define FUSE_POWER_BYPASS BIT_FUSE_POWER_BYPASS
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#define FUSE_CLOCK_DIVIDER(_X_) BITS_FUSE_CLOCK_DIVIDER(_X_)
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#define FUSE_CLOCK_DISABLE BIT_FUSE_CLOCK_DISABLE
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#define FUSE_SOFTWARE_RESET BIT_FUSE_SOFTWARE_RESET
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#define FUSE_BLOCK_NUMBER(_X_) BITS_FUSE_BLOCK_NUMBER(_X_)
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#define HIGH_VOLT_ENABLE BIT_HIGH_VOLT_ENABLE
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#define BURN_FUSE_ENABLE BIT_BURN_FUSE_ENABLE
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#define FUSE_LOCK BIT_FUSE_LOCK
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#define ENABLE_SOFT_FUSE_PROG BIT_ENABLE_SOFT_FUSE_PROG
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#define SEL_FUSE_B BIT_SEL_FUSE_B
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/* bits definitions for register REG_GEU_FUSE_STATUS */
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#define FUSE_READY BIT_GE_FUSE_READY205
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#define FUSE_BURN_DONE BIT_FUSE_BURN_DONE
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#define ASR_ADDR(a,b) ((a)+(b))
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#define REGS_DRO_CONTROLIS_BASE 0xD4013200
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#define REGS_APBC_BASE 0xD4015000
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#define REG_APBC_APBC_DRO_CLK_RST ASR_ADDR(REGS_APBC_BASE, 0X58)/*Clock/Reset Control Register forDRO*/
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/* registers definitions for DRO_CONTROLIS */
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#define REG_DRO_CONTROLIS_DRO_CTRL ASR_ADDR(REGS_DRO_CONTROLIS_BASE, 0X00)/*DRO control register*/
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#define REG_DRO_CONTROLIS_DRO_CNT_TIME ASR_ADDR(REGS_DRO_CONTROLIS_BASE, 0X4)/*DRO runtime length register*/
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#define REG_DRO_CONTROLIS_DRO_LVT ASR_ADDR(REGS_DRO_CONTROLIS_BASE, 0X8)/*DRO LVT Value Register*/
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#define REG_DRO_CONTROLIS_DRO_HVT ASR_ADDR(REGS_DRO_CONTROLIS_BASE, 0XC)/*DRO HVT Value Register*/
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#define REG_DRO_CONTROLIS_DRO_SVT ASR_ADDR(REGS_DRO_CONTROLIS_BASE, 0X10)/*DRO SVT Value Register*/
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#define NUM_PROFILES_CRN 8
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#define NUM_SVC_LVL_CRN 4
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void set_cpu_dvc(CP_DVC_LEVEL cp_dvc_val);
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void set_cpu_freq(CORE_PLL_FREQ_T cp_freq_val);
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void cpu_freq_init(CORE_PLL_FREQ_T cp_freq_val);
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void set_dsp_dvc(DSP_DVC_LEVEL dsp_dvc_val);
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BOOL set_ddr_freq(DDR_FREQUENCY freq);
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void HWDFC_disable(void);
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void HWDFC_enable(void);
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extern int fatal_printf(const char * fmt,...);
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#ifdef EDNE_1928
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void set_ddr_hwdfc(UINT8 cp_hwdfc_idx);
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void _set_ddr_hwdfc(UINT8 cp_hwdfc_idx);
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void _set_cpu_freq(CPU_PLL_T cpu_freq_val);
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#endif
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#ifdef NEZHA3_1826
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void Nezha3_PP_change(UINT8 ProductPoint);
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void Helan4_PP_change(UINT8 ProductPoint); //Reuse Nezha3-Z3 PP, but not touch PLL2
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#endif
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void CpCoreFreqChangeTo416(void);
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void CpCoreFreqChangeTo104(void);
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void PsramPhyFreqChangeTo156(void);
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void PsramPhyFreqChangeTo416(void);
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#endif
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