199 lines
4.9 KiB
C
199 lines
4.9 KiB
C
#ifndef __DMA_EXT_H_
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#define __DMA_EXT_H_
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#include "types.h"
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typedef struct
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{
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unsigned int DDADR; //descriptor address reg
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unsigned int DSADR; //source address reg
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unsigned int DTADR; //target address reg
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unsigned int DCMD; //command address register
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}XLLP_DMAC_DESCRIPTOR_T, *P_XLLP_DMAC_DESCRIPTOR_T;
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typedef struct
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{
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unsigned int DCSR[32];
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unsigned int RESERVED0[0x8];
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unsigned int DALGN;
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unsigned int DPCSR;
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unsigned int RESERVED1[0xE];
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unsigned int DRQSR0;
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unsigned int DRQSR1;
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unsigned int DRQSR2;
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unsigned int RESERVED2[0x1];
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unsigned int DINT;
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unsigned int RESERVED3[0x3];
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unsigned int DRCMR1[64];
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XLLP_DMAC_DESCRIPTOR_T DMA_DESC[32];
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unsigned int RESERVED4[0x340];
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unsigned int DRCMR2[36];
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}XLLP_DMAC_T, *P_XLLP_DMAC_T;
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#define RCMR_MAPVLD BIT_7
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#define CSR_STOPINTR BIT_3
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#define CSR_RUN BIT_31
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#define CSR_STOPIRQEN BIT_29
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#define CSR_BUSERRINTR BIT_0
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#define CSR_STARTINTR BIT_1
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#define CSR_ENDINTR BIT_2
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#define CSR_EORIRQEN BIT_28
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#define CSR_NODESCFETCH BIT_30
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#define DMA_DDADR_RESERVED_MASK 0xFFFFFFF0
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#define DMA_STATUS_INTERRUPTS_MASK 0x01000217
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#define DMA_DEVICE_PART1_NUM 64
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#define DMA_SQU_2_SQU_CHANNEL 0
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#define DMA_SQU_2_DDR_CHANNEL 1
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#define DMA_DDR_2_SQU_CHANNEL 2
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#define DMA_DDR_2_DDR_CHANNEL 3
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#define DMA_XFER_CHANNEL 4
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#define DMA_GEU_W_CHANNEL 5
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#define DMA_GEU_R_CHANNEL 6
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#define DMA_SQU_ADDR_1 0xD1000000
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#define DMA_SQU_ADDR_2 0xD1004000
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#define DMA_MDMA_XFER_SIZE 0xF000
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#define DMA_MAX_BYTES_PER_DESC 0x1F00
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#define DMA_MDMA_NF_XFER_SIZE 0x1F00
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#define DMA_STRESS_XFER_SIZE 0x5000
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typedef struct
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{
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uint32_t DDADR; // descriptor address reg
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uint32_t DSADR; // source address register
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uint32_t DTADR; // target address register
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uint32_t DCMD; // command address register
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}DMA_DESCRIPTOR, *P_DMA_DESCRIPTOR;
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struct DMA_CMD_BITS
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{
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uint32_t Length :13; //Bits [12:0]: Length of transfer in Bytes
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uint32_t Reserved4 :1; //Bit 13: reserved
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uint32_t Width :2; //Bits [15:14]: Width of onchip peripheral - 0=reserved, 1=1B, 2=2B, 3=4B
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uint32_t MaxBurstSize :2; //Bits [17:16]: Max Burst Size - 0=reserved, 1=8B, 2=16B, 3=32B
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uint32_t Reserved3 :3; //Bits [20:18]: reserved
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uint32_t EndIRQEn :1; //Bit 21: end interrupt enable
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uint32_t StartIRQEn :1; //Bit 22: start interrupt enable
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uint32_t AddrMode :1; //Bit 23: Addressing mode for descriptor compare - 0=target has addr/1=target has data
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uint32_t Reserved2 :1; //Bit 24: reserved
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uint32_t CmpEn :1; //Bit 25: Compare Enable - descriptor branching compare enable
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uint32_t Reserved1 :2; //Bits [27:26]: reserved
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uint32_t FlowTrg :1; //Bit 28: Target flow control - 1=wait for request signal
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uint32_t FlowSrc :1; //Bit 29: Source flow control - 1=wait for request signal
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uint32_t IncTrgAddr :1; //Bit 30: Target increment - 0=no increment, 1=increment
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uint32_t IncSrcAddr :1; //Bit 31: Source increment - 0=no increment, 1=increment
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};
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typedef union
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{
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uint32_t value;
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struct DMA_CMD_BITS bits;
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} DMA_CMDx_T, *P_DMA_CMDx_T;
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typedef enum{
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DMA_DREQ0 = 0, // DREQ 0, Companion Chip request 0
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DMA_DREQ1 = 1, // DREQ 1, Companion Chip request 1
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DMA_DREQ2 = 2,
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DMA_UART_0_RX = 3,
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DMA_UART_0_TX = 4,
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DMA_UART_1_RX = 5,
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DMA_UART_1_TX = 6,
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DMA_I2C0_TX = 7,
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DMA_I2C0_RX = 8,
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DMA_SSP_0_RX = 9,
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DMA_SSP_0_TX = 10,
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DMA_SSP_2_RX = 11,
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DMA_SSP_2_TX = 12,
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DMA_LCD0 = 13,
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DMA_LCD1 = 14,
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DMA_I2C1_TX = 15,
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DMA_I2C1_RX = 16,
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DMA_NAND_DATA = 44,
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DMA_NAND_CMD = 45,
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DMA_AEU_TX = 46,
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DMA_AEU_RX = 47,
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DMA_REQ_SSP0_RX = 52,
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DMA_REQ_SSP0_TX = 53,
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DMA_REQ_SSP1_RX = 54,
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DMA_REQ_SSP1_TX = 55,
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DMA_REQ_SSP2_RX = 60,
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DMA_REQ_SSP2_TX = 61,
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DMA_MEM2MEM_MOVE = 255 // RESERVED for Memory to Memory moves
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}DMA_MAP_DEVICE;
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typedef enum{
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DMA_DEV_SULOG_CH = 0,
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DMA_DEV_UART1_RX_CH = 2,
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DMA_DEV_UART1_TX_CH = 3,
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DMA_DEV_SSP0_TX_CH = 10,
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DMA_DEV_SSP0_RX_CH = 11,
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DMA_DEV_SSP2_TX_CH = 29,
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DMA_DEV_SSP2_RX_CH = 30,
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} DMA_DEVICE_CHANNEL;
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typedef struct DMA_STRESS_ARG_TAG{
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uint32_t channel;
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uint32_t num;
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uint32_t size;
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uint32_t stop_flag;
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uint32_t mask;
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uint32_t mask_t;
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uint32_t src[32];
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uint32_t dst[32];
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uint32_t des[32];
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}DMA_STRESS_ARG, *P_DMA_STRESS_ARG;
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typedef enum{
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DMA_BURST_SIZE_RSVD = 0,
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DMA_BURST_SIZE_8B,
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DMA_BURST_SIZE_16B,
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DMA_BURST_SIZE_32B
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}DMA_BURST_SIZE;
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typedef enum{
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DMA_MODE_FETCH = 0,
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DMA_MODE_NONFETCH
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}DMA_MODE;
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typedef enum
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{
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DMA_STOP = 0,
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DMA_END
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}DMA_WAIT_DONE_FLAG;
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#endif
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