118 lines
5.6 KiB
C
118 lines
5.6 KiB
C
/*------------------------------------------------------------
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(C) Copyright [2006-2008] Marvell International Ltd.
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All Rights Reserved
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------------------------------------------------------------*/
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/*--------------------------------------------------------------------------------------------------------------------
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INTEL CONFIDENTIAL
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Copyright 2006 Intel Corporation All Rights Reserved.
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The source code contained or described herein and all documents related to the source code ("Material") are owned
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by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or
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its suppliers and licensors. The Material contains trade secrets and proprietary and confidential information of
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Intel or its suppliers and licensors. The Material is protected by worldwide copyright and trade secret laws and
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treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted,
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transmitted, distributed, or disclosed in any way without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual property right is granted to or
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conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement,
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estoppel or otherwise. Any license under such intellectual property rights must be express and approved by
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Intel in writing.
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-------------------------------------------------------------------------------------------------------------------*/
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/************************************************************************/
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/* */
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/* Title: GPIO (General Purpose Input Output) Configuration */
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/* Header File */
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/* */
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/* Filename: Gpio_Config.h */
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/* */
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/* Author: Yossi Gabay */
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/* */
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/* Target, subsystem: Common Platform, HAL */
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/* */
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/* Yaeli Karni Mar 2006, Enhance driver to support Boerne */
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/* */
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/************************************************************************/
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#ifndef _GPIO_CONFIG_H_
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#define _GPIO_CONFIG_H_
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#include "syscfg.h"
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#include "intc_config.h" // some configurations are shared as INTC and GPIO are coupled
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// Assumption is that our of hte 64 (hermon)/ 128 (Bulverde/Boerne) GPIOs the user will not
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// define more then 32 groups of GPIOs. If need arise, the number should be increased.
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// (user interface to GPIO is via the notion of PORT!)
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#define GPIO_MAX_PORT_HANDLES 32
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#define GPIO_DEFAULT_DEBOUNCE_CLOCK 1
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#if defined(_HERMON_B0_SILICON_) && !defined (INTEL_2CHIP_PLAT_BVD) && !defined(_TAVOR_BOERNE_)
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#if !defined(_EXTENDED_GPIO_)
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// EGPIO: Hermon specific feature
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#define _EXTENDED_GPIO_
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#endif
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#endif
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#if defined (_TAVOR_BOERNE_) || defined(SILICON_TTC)
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#define GPIO_128_ENTRIES
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#else
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#define GPIO_64_ENTRIES
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#endif
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// GPIO[127:64]: APP CPU's only
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// Defined in intc_config.h: see GPIO_128_ENTRIES
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#if defined(_HERMON_B0_SILICON_) && !defined(INTEL_2CHIP_PLAT_BVD)
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// Hermon has a special GPIO register layout for edge detectio, interrupt, and pulling control registers
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#else
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#define GPIO_APP_LAYOUT
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#endif
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#if !defined(GPIO_APP_LAYOUT)
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#define GPIO_DEBOUNCE_CONTROL /* Support debouncer control per GPIO pin */
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#define GPIO_PUPD_CONTROL /* Support pull-up/pull-down configuration from GPIO module */
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#define GPIO_LEVEL_DET_SUPPORTED /* Support level detection */
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#define GPIO_INT_MASK_REQ_REGS /* GIMR and GIRR allow masking of *enabled* edge detectors and reading interrupt status */
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#endif
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#if defined(_TAVOR_BOERNE_) || defined(SILICON_TTC)
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// Bit-wise set/clear type registers for direction and edge detection configuration
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#define GPIO_SETCLEAR_ACCESS
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#endif
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// The legacy register map has 3 (GPIO_LEGACY_REG_AMOUNT) registers of each type (sequential), which allows for up to 96 GPIOs;
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// For 128 GPIO's option the 4th is in offset 0x100 bytes from the first one (hence, 0x40 words from the first register).
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// This is applicable for registers {GPLRx,GPDRx,GPSRx,GPCRx,GRERx,GFERx,GEDRx}
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// For new Set/Clear registers {GSDR,GCDR,GSFER,GCFER,GSRER,GCRER} two options exist:
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// - GPIO_SC_REGS_EMBEDDED: the same approach, while these registers follow previous ones in the register map (TTC layout)
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// - otherwise: 4 registers sequentially located in a separate space after all legacy registers (Tavor layout)
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#if defined (SILICON_TTC)
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#define GPIO_SC_REGS_EMBEDDED
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#endif
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#if defined(SILICON_TTC)
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// GPIO edge detection interrupts only the core that unmasks it (per GPIO pin).
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// This feature allows controlling interrupt generation (from INTC package) without affecting the edge detector settings
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#define GPIO_CORE_INT_MASK
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#if defined(SILICON_TTC_CORE_MOHAWK)
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#define GPIO_CORE_INT_MASK_AP
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#else
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#define GPIO_CORE_INT_MASK_CP
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#endif
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#endif
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#if !defined (INTEL_2CHIP_PLAT_BVD)
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#define GPIO_SETUP_HW_ON_INIT
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#endif
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#if defined(SILICON_TTC)
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#define GPIO_HW_ADDRESS 0xD4019000L
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#else
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#define GPIO_HW_ADDRESS 0x40E00000L
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#endif
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#endif /* _GPIO_CONFIG_H_ */
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