391 lines
16 KiB
C
391 lines
16 KiB
C
/*------------------------------------------------------------
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(C) Copyright [2006-2008] Marvell International Ltd.
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All Rights Reserved
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------------------------------------------------------------*/
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/******************************************************************************
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* MODULE HEADER FILE
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*******************************************************************************
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* COPYRIGHT (C) 2005 Intel Corporation, All rights reserved..
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*
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* This file and the software in it is furnished under
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* license and may only be used or copied in accordance with the terms of the
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* license. The information in this file is furnished for informational use
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* only, is subject to change without notice, and should not be construed as
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* a commitment by Intel Corporation. Intel Corporation assumes no
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* responsibility or liability for any errors or inaccuracies that may appear
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* in this document or any software that may be provided in association with
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* this document.
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* Except as permitted by such license, no part of this document may be
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* reproduced, stored in a retrieval system, or transmitted in any form or by
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* any means without the express written consent of Intel Corporation.
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*
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* Title: USIM hardware header file
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*
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* Filename: usim_hw.h
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*
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* Author: Eilam Ben-Dror
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*
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* Description: This is the header file for the USIM hardware interface (UICC I/F).
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*
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* Last Updated: 14-Dec-2005
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*
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******************************************************************************/
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#ifndef _USIM_HW_H_
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#define _USIM_HW_H_
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#include "global_types.h"
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#include "usim_config.h"
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#include "usim_db.h"
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#ifdef USIM_TAVOR_DMA_ENABLE
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#include "dma.h"
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#endif
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#ifndef PHS_SW_DEMO_TTC
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#if defined(_HERMON_B0_SILICON_)
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// Hermon
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#define USIM_0_HW_ADDRESS 0x41600000L
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//#elif defined(_TAVOR_HARBELL_) || defined(SILICON_PV2)
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#elif defined(SILICON_PV2)
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// Tavor
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#define USIM_0_HW_ADDRESS 0xF0080000L
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#elif defined(SILICON_TTC)
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// TTC
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#define USIM_0_HW_ADDRESS 0xD4032000L /*USIM1*/
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//#define USIM_1_HW_ADDRESS 0xD4033000L /*USIM2*/
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#else
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#error Unsupported platform
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#endif
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#else
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#define USIM_0_HW_ADDRESS 0xD4032000L
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#define USIM_1_HW_ADDRESS 0xD4033000L
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#endif
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#define ALL_HW_BITS 0xFFFFFFFFL
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struct USIMController
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{
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UINT32 RBR ; // Receive Buffer Read only
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UINT32 THR ; // Transmit Holding Write only
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UINT32 IER ; // Interrupt Enable Read / Write
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UINT32 IIR ; // Interrupt Identification Read / Write *
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UINT32 FCR ; // FIFO Control Read / Write
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UINT32 FSR ; // FIFO Status Read only
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UINT32 ECR ; // Error Control Read / Write
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UINT32 LCR ; // Line Control Read / Write
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UINT32 CCR ; // Card Control Read / Write
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UINT32 LSR ; // Line Status Read only
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UINT32 EGTR; // Extra Guard Time Read / Write
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UINT32 BGTR; // Block Guard Time Read / Write
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UINT32 TOR ; // Time Out Read / Write
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UINT32 CLKR; // Clock Read / Write
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UINT32 DLR ; // Divisor Latch Read / Write
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UINT32 FLR ; // Factor Latch Read / Write
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UINT32 CWTR; // Character Waiting Time Read / Write
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UINT32 BWTR; // Block Waiting Time Read / Write
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} ;
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//#define USIMHWRegisters (* (volatile struct USIMController *) USIM_0_HW_ADDRESS)
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/*----------- Extern definition ----------------------------------------------*/
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#ifndef _USIM_HW_NO_EXTERN_
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#define EXTERN extern
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#else
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#define EXTERN
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#endif /* _USIM_HW_NO_EXTERN_ */
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EXTERN volatile struct USIMController * USIMHWRegisters [2];
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// Clock request types:
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typedef enum
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{
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USIM_HW_CLOCK_STOP_REQ = 0,
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USIM_HW_CLOCK_START_REQ
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}USIM_HW_ClockReqType;
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// RX Data Ready levels:
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typedef enum
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{
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USIM_HW_1B = 0, // 1 byte received would cause an interrupt
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USIM_HW_4B, // 4 bytes received would cause an interrupt
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USIM_HW_8B, // 8 bytes received would cause an interrupt
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USIM_HW_12B // 12 bytes received would cause an interrupt
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}USIM_HW_RDRLevel;
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#ifdef USIM_TAVOR_DMA_ENABLE
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#define DATA_LIMIT_FOR_DMA 5
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#define USIM_DMA_WRITE_CHAN DMA_CHANNEL_19 // DMA C3 -- channel 3
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#define USIM_DMA_READ_CHAN DMA_CHANNEL_18 // DMA C3 -- channel 2
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#endif
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/*----------- Global macro definitions ----------------------------------------*/
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#ifdef USIM_TAVOR_DMA_ENABLE
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/*---------------------- T a v o r ---------------------------------------------*/
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#define USIM_DISABLE_TX_DMA_MODE(c) (USIMHWRegisters[c]->IER &= 0xFFFF7FFF) // Disable the DMA transmit request
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#define USIM_ENABLE_TX_DMA_MODE(c) (USIMHWRegisters[c]->IER |= 0x00008000) // Enable DMA transmit request
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#define USIM_SET_TX_THRESHOLD_TO_8_BYTE(c) (USIMHWRegisters[card]->FCR != 0x100L) // Set DMA threshold to 8 byte for tx.
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#ifdef USIM_TAVOR_READ_WITH_DMA
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// Set DMA threshold to 8 byte rx fifo
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#define USIM_SET_RX_THRESHOLD_TO_8_BYTE(c) USIMHWRegisters[card]->FCR &= 0x0C0L \
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USIMHWRegisters[card]->FCR |= 0x080L
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#endif
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#endif
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/*------------------------------------------------------------------------------*/
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//#define DUMMY_DELAY \
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// { \
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// int cntr_delay_o01=0; \
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// for (;++cntr_delay_o01 < 0x3F;)\
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// ;\
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// }
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#define USIM_ENABLE(c,source) (USIMHWRegisters[c]->IER |= (0x1L << (source)))
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#define USIM_ENABLE_MASK(c, mask) (USIMHWRegisters[c]->IER = (mask))
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#define USIM_DISABLE(c,source) (USIMHWRegisters[c]->IER &= (~(0x1L<<(source))))
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#define USIM_DISABLE_ALL(c) USIMHWRegisters[c]->IER = 0
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#define USIM_GET_IER(c) (USIMHWRegisters[c]->IER)
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#define USIM_INTERRUPT_STATUS_GET(c,i) ((i) = (USIMHWRegisters[c]->IIR & 0x137FL))
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#define USIM_INTERRUPT_CLEAR(c,source) (USIMHWRegisters[c]->IIR = (0x1L << (source)))
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#define USIM_INTERRUPT_CLEAR_ALL(c) (USIMHWRegisters[c]->IIR = USIMHWRegisters[c]->IIR & USIM_CLEARABLE_INTERRUPT_SOURCES_MASK)
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#define USIM_PARITY_ERR_LEVEL_SET(c,level) \
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(USIMHWRegisters[c]->ECR = (level<<3) + (USIMHWRegisters[c]->ECR & 0x03L))
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#define USIM_T0_ERR_LEVEL_SET(c,level) \
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(USIMHWRegisters[c]->ECR = (level-1) + (USIMHWRegisters[c]->ECR & 0x18L))
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#define USIM_T0_ERR_CLEAR(c) (USIMHWRegisters[c]->ECR |= 0x40L)
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#define USIM_TX_BLOCK_SET(c) (USIMHWRegisters[c]->FCR |= 0x100L)
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#define USIM_TX_CLEAR(c) USIMHWRegisters[c]->FCR |= 0x02
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#define USIM_GET_FCR(c) (USIMHWRegisters[c]->FCR )
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#define USIM_PERR_NUM_GET(c,len) ((len) = (UINT8)((USIMHWRegisters[c]->ECR & 0xFF00) >> 8))
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#define USIM_TX_LENGTH_GET(c,len) ((len) = (UINT8)((USIMHWRegisters[c]->FSR & 0x1E00) >> 9))
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#define USIM_RX_LENGTH_GET(c,len) ((len) = (USIMHWRegisters[c]->FSR & 0xFF))
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#define USIM_RX_CLEAR(c) USIMHWRegisters[c]->FCR |= 0x01
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#define USIM_CLEAR_ALL(c) USIMHWRegisters[c]->FCR |= 0x03; \
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USIMHWRegisters[c]->IIR = USIM_CLEARABLE_INTERRUPT_SOURCES_MASK
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#define USIM_EXTRA_GUARD_TIME_SET(c,egtm) \
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USIMHWRegisters[c]->EGTR = (egtm); \
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USIMHWRegisters[c]->TOR = ((egtm)<4)? ((egtm+T0_ADJUST)*USIM_TIMEOUT_CHARS) : 255
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#define USIM_BLOCK_GUARD_TIME_SET(c,protocol) \
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if(protocol==USIM_T0) \
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(USIMHWRegisters[c]->BGTR = 4); \
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else \
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(USIMHWRegisters[c]->BGTR = 11)
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#define USIM_CHAR_WAIT_TIME_SET(c,protocol,cwt) \
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if(protocol==USIM_T0) \
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(USIMHWRegisters[c]->CWTR = (cwt-T0_ADJUST)); \
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else \
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(USIMHWRegisters[c]->CWTR = (cwt-T1_ADJUST))
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#define USIM_BLOCK_WAIT_TIME_SET(c,protocol,bwt) \
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if(protocol==USIM_T0) \
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(USIMHWRegisters[c]->BWTR = (bwt==USIM_MAX_WWT_REG_VALUE)?(bwt-T0_ADJUST):(bwt-T0_ADJUST)); \
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else \
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(USIMHWRegisters[c]->BWTR = (bwt==USIM_MAX_WWT_REG_VALUE)?(bwt-T1_ADJUST):(bwt-T1_ADJUST))
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#define USIM_CHAR_WAIT_TIME_GET(c,protocol,cwt) \
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if(protocol==USIM_T0) \
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(cwt=(USIMHWRegisters[c]->CWTR+T0_ADJUST)); \
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else \
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(cwt=(USIMHWRegisters[c]->CWTR+T1_ADJUST))
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#define USIM_BLOCK_WAIT_TIME_GET(c,protocol,bwt) \
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if(protocol==USIM_T0) \
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(bwt=(USIMHWRegisters[c]->BWTR==(USIM_MAX_WWT_REG_VALUE-T0_ADJUST))?(USIMHWRegisters[c]->BWTR+T0_ADJUST):(USIMHWRegisters[c]->BWTR+T0_ADJUST)); \
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else \
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(bwt=(USIMHWRegisters[c]->BWTR==(USIM_MAX_WWT_REG_VALUE-T1_ADJUST))?(USIMHWRegisters[c]->BWTR+T1_ADJUST):(USIMHWRegisters[c]->BWTR+T1_ADJUST))
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#define USIM_TIME_OUT_SET(c,time) (USIMHWRegisters[c]->TOR = (time))
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#define USIM_PROTOCOL_SET(c,protocol) if((protocol) == USIM_T0) \
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USIMHWRegisters[c]->LCR &= 0x07L; \
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else \
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USIMHWRegisters[c]->LCR |= 0x18L
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#define USIM_CONVENTION_SET(c,convention) \
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if((convention) == USIM_DIRECT) \
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{ \
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USIMHWRegisters[c]->LCR |= 0x04L; \
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USIMHWRegisters[c]->LCR &= 0x1CL; \
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} \
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else \
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{ \
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USIMHWRegisters[c]->LCR &= 0x1BL; \
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USIMHWRegisters[c]->LCR |= 0x03L; \
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}
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#define USIM_PARITY_TOGGLE(c) if((USIMHWRegisters[c]->LCR)&0x04L) \
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USIMHWRegisters[c]->LCR &= 0x1BL; \
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else \
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USIMHWRegisters[c]->LCR |= 0x04L
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#define USIM_CONVENTION_TOGGLE(c) \
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if((USIMHWRegisters[c]->LCR)&0x04L) \
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{ \
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USIMHWRegisters[c]->LCR &= 0x1BL; \
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USIMHWRegisters[c]->LCR |= 0x03L; \
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} \
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else \
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{ \
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USIMHWRegisters[c]->LCR |= 0x04L; \
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USIMHWRegisters[c]->LCR &= 0x1CL; \
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}
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#define USIM_DIVISOR_SET(c,divisor) (USIMHWRegisters[c]->DLR = (divisor))
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#define USIM_DIVISOR_GET(c) (USIMHWRegisters[c]->DLR & 0xFFFF)
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#define USIM_FACTOR_SET(c,factor) (USIMHWRegisters[c]->FLR = (factor) - 1)
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#define USIM_FACTOR_GET(c) ((USIMHWRegisters[c]->FLR & 0xFF) + 1)
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//#define USIM_WAIT_CLKR_CHANGED(c) {\
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// int cycl_cntr_o001 = 0xFF; \
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// for (; (cycl_cntr_o001>0) && (USIMHWRegisters[c]->CLKR & 0x1000); --cycl_cntr_o001)\
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// DUMMY_DELAY;\
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// _USIMClockRequestCounter[card]=(cycl_cntr_o001==0)?0:0xDEAD; \
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// }
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//#define USIM_CARD_CLOCK_SET(c,ratio) \
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// USIMHWRegisters[c]->CLKR = (USIMHWRegisters[c]->CLKR & 0x6000) + (ratio);\
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// USIM_WAIT_CLKR_CHANGED(c)
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/*see manual CLCK can be wrriten only to this bits*/
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#define USIM_CARD_CLOCK_WR_MASK 0xF0FFL
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#define USIM_CARD_CLOCK_GET(c) (USIMHWRegisters[c]->CLKR & USIM_CARD_CLOCK_WR_MASK)
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/* required to check RQST bit for == 0 after writting to this register */
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#define USIM_CARD_CLOCK_SET_RATIO(c,ratio) \
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(USIMHWRegisters[c]->CLKR = (USIM_CARD_CLOCK_GET(c) & 0xE000) | (ratio & 0xFF ) )
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#define USIM_CARD_CLOCK_GET_DIVISOR(c) (USIMHWRegisters[c]->CLKR & 0xFF)
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#define USIM_CARD_CLOCK_STOP_GET(c) (USIMHWRegisters[c]->CLKR & 0x2000)
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#define USIM_CARD_CLOCK_CHANGE_GET(c) (USIMHWRegisters[c]->CLKR & 0x1000)
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#define USIM_CARD_CLOCK_STOP_LEVEL_GET(c) (USIMHWRegisters[c]->CLKR & 0x4000)
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#define USIM_CARD_CLOCK_STOP_LEVEL_HIGH(c) USIMHWRegisters[c]->CLKR = 0x4000L | USIM_CARD_CLOCK_GET(c)
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#define USIM_CARD_CLOCK_STOP_LEVEL_LOW(c) USIMHWRegisters[c]->CLKR =(((~0x4000L) & USIM_CARD_CLOCK_GET(c)) & USIM_CARD_CLOCK_WR_MASK)
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#define USIM_CARD_CLOCK_START_REQ(c) USIMHWRegisters[c]->CLKR = ((( ~0x2000L) & USIM_CARD_CLOCK_GET(c)) & USIM_CARD_CLOCK_WR_MASK)
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#define USIM_CARD_CLOCK_STOP_REQ(c) USIMHWRegisters[c]->CLKR = 0x2000L | USIM_CARD_CLOCK_GET(c)
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#define USIM_CARD_CLOCK_STOP_CLCK_USIM(c) USIMHWRegisters[c]->CLKR = 0x8000L | USIM_CARD_CLOCK_GET(c)
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#define USIM_CARD_CLOCK_START_CLCK_USIM(c) USIMHWRegisters[c]->CLKR=((( ~0x8000L) & USIM_CARD_CLOCK_GET(c)) & USIM_CARD_CLOCK_WR_MASK)
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#define USIM_CARD_CLOCK_STOP_CLCK_USIM_GET(c) USIMHWRegisters[c]->CLKR = (USIMHWRegisters[c]->CLKR & 0x8000)
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// card control definitions:
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#define USIM_CARD_RESET(c) USIMHWRegisters[c]->CCR &= 0x016L
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#define USIM_CARD_UNRESET(c) USIMHWRegisters[c]->CCR |= 0x01L
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#define USIM_VOLTAGE_SET(c,v) /* USIMHWRegisters[c]->CCR = ((((v)%3) << 1) + 0x10L) */
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#define USIM_TXD_FORCE_SET(c) USIMHWRegisters[c]->CCR |= 0x10L
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#define USIM_TXD_FORCE_CLEAR(c) USIMHWRegisters[c]->CCR &= 0x07L
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#define USIM_IS_RX_ACTIVE(c) (USIMHWRegisters[c]->LSR & 0x04000L)
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#define USIM_IS_TX_ACTIVE(c) (USIMHWRegisters[c]->LSR & 0x02000L)
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#define USIM_IS_PARITY_ERROR(c) (USIMHWRegisters[c]->LSR & 0x02L)
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#define USIM_IS_RX_NOT_EMPTY(c) (USIMHWRegisters[c]->LSR & 0x01000)
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#define USIM_GET_LSR(c) (USIMHWRegisters[c]->LSR)
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#define USIM_DUMMY_READ(c) {volatile UINT8 dummy =(UINT8)USIMHWRegisters[c]->IIR;}
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#define T0_ADJUST 12
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#define T1_ADJUST 11
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#define USIM_ADJUST_CWT_GCF 3
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#define USIM_ADJUST_BWT_GCF 3
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/* Adjusting values for GCF - TC 7.2.1 c-3 (TS 102 230).
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* In test case(and spec) is written that required 960etu,
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* while Comprion IT3 test passes only after >1000etu */
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#define USIM_ADJUST_WWT_GCF 45
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#define USIM_HIGH_BAUD_RATE_EXTRA_GUARD_TIME_ADJUST (4)
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// Interrupt enable masks according to state:
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#define USIM_SEND_ENABLE_MASK 0x0204L
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#define USIM_W4RESPONSE_ENABLE_MASK 0x015FL
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#define USIM_RECEIVE_ENABLE_MASK 0x013BL
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#define USIM_DMA_SEND_ENABLE_MASK 0x8004L
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#define USIM_DMA_W4RESPONSE_ENABLE_MASK 0x405FL
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#define USIM_DMA_RECEIVE_ENABLE_MASK 0x403BL
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#define USIM_MAX_WWT_REG_VALUE 0xFFFFL
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#define USIM_CLEARABLE_INTERRUPT_SOURCES_MASK (0x106BL)
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/*----------- Global function prototypes -------------------------------------*/
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void USIM_HW_RXRead(USIM_Card card, UINT32 length, UINT8 * buffer);
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void USIM_HW_RXRead_Dummy(USIM_Card card, UINT32 length);
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void USIM_HW_TXWrite(USIM_Card card,UINT32 length, UINT8 * buffer);
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void USIM_HW_RXLevelSet(USIM_Card card, USIM_HW_RDRLevel level);
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void USIM_HW_deactivate(USIM_Card card, BOOL shutDown);
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void USIM_HW_cardReset(USIM_Card card, USIM_Class voltageClass);
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BOOL USIM_HW_Delay(USIM_Card card, UINT32 clockCycles, UINT32 mode);
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BOOL USIM_HW_checkClock(USIM_Card card);
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BOOL USIM_HW_cardClockRequest(USIM_Card card, USIM_HW_ClockReqType reqType);
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void usim_hw_clk_onoff(USIM_Card card, USIM_HW_ClockReqType reqType);
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void AIB_USIM1_IO_Set_3_3V(void);
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void AIB_USIM2_IO_Set_3_3V(void);
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void AIB_USIM2_IO_Set_1_8V(void);
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void usim_close_mfpr_set(USIM_Card card);
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#undef EXTERN
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#endif /* _USIM_HW_H_ */
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