271 lines
8.6 KiB
C
271 lines
8.6 KiB
C
#ifndef __APBCLK_H__
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#define __APBCLK_H__
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#define __IO volatile /*!< defines 'read / write' permissions */
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typedef unsigned char uint8_t;
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typedef unsigned short uint16_t;
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typedef unsigned int uint32_t;
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#define BIT_0 (1 << 0)
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#define BIT_1 (1 << 1)
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#define BIT_2 (1 << 2)
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#define BIT_3 (1 << 3)
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#define BIT_4 (1 << 4)
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#define BIT_5 (1 << 5)
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#define BIT_6 (1 << 6)
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#define BIT_7 (1 << 7)
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#define BIT_8 (1 << 8)
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#define BIT_9 (1 << 9)
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#define BIT_10 (1 << 10)
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#define BIT_11 (1 << 11)
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#define BIT_12 (1 << 12)
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#define BIT_13 (1 << 13)
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#define BIT_14 (1 << 14)
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#define BIT_15 (1 << 15)
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#define BIT_16 (1 << 16)
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#define BIT_17 (1 << 17)
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#define BIT_18 (1 << 18)
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#define BIT_19 (1 << 19)
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#define BIT_20 (1 << 20)
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#define BIT_21 (1 << 21)
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#define BIT_22 (1 << 22)
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#define BIT_23 (1 << 23)
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#define BIT_24 (1 << 24)
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#define BIT_25 (1 << 25)
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#define BIT_26 (1 << 26)
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#define BIT_27 (1 << 27)
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#define BIT_28 (1 << 28)
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#define BIT_29 (1 << 29)
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#define BIT_30 (1 << 30)
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#define BIT_31 ((unsigned)1 << 31)
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typedef struct
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{
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__IO uint32_t UART0_CLK_RST;
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__IO uint32_t UART1_CLK_RST; //0x0004
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__IO uint32_t GPIO_CLK_RST; //0x0008
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__IO uint32_t PWM0_CLK_RST; //0x000c
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__IO uint32_t PWM1_CLK_RST; //0x0010
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__IO uint32_t PWM2_CLK_RST; //0x0014
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__IO uint32_t PWM3_CLK_RST; //0x0018
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__IO uint32_t SSP0_CLK_RST; //0x001c
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__IO uint32_t SSP1_CLK_RST; //0x0020
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__IO uint32_t IPC_CLK_RST; //0x0024
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__IO uint32_t RTC_CLK_RST; //0x0028
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__IO uint32_t TWSI_CLK_RST; //0x002c
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__IO uint32_t KPC_CLK_RST; //0x0030
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__IO uint32_t TIMERS_CLK_RST; //0x0034
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__IO uint32_t TB_ROTARY_CLK_RST; //0x0038
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__IO uint32_t AIB_CLK_RST; //0x003C
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__IO uint32_t SW_JTAG_CLK_RST; //0x0040
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__IO uint32_t TIMERS1_CLK_RST; //0x0044
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__IO uint32_t ONEWIRE_CLK_RST; //0x0048
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__IO uint32_t SSP2_CLK_RST; //0x004C
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__IO uint32_t ASFAR; //0x0050
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__IO uint32_t ASSAR; //0x0054
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__IO uint32_t RESERVED1[2]; //0x0058-0x00060
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__IO uint32_t TWSI2_CLK_RST; //0x60
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__IO uint32_t COUNTER_CLK_SEL; //0x0064
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__IO uint32_t RESERVED2; //0x0068
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__IO uint32_t TSEN_CLK_RST; //0x006c
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__IO uint32_t USCER1; //0x0070
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__IO uint32_t USCER2; //0x0074
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__IO uint32_t ICER; //0x0078
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__IO uint32_t TWSI3_CLK_RST; //0x007c
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}APBClock_TypeDef;
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#define APBClock_BASE 0xD4015000
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#define APBClock (( APBClock_TypeDef *) APBClock_BASE )
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//0x0000 offset Clock/Reset Control Register for UART 0
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#define UART0_CLK_RST_APBCLK BIT_0
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#define UART0_CLK_RST_FNCLK BIT_1
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#define UART0_CLK_RST_RST BIT_2
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#define UART0_CLK_RST_FNCLKSEL_MSK SHIFT4(0x7)
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#define UART0_CLK_RST_FNCLKSEL_BASE 4
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//0x004 offset Clock/Reset Control Register for UART 1
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#define UART1_CLK_RST_APBCLK BIT_0
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#define UART1_CLK_RST_FNCLK BIT_1
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#define UART1_CLK_RST_RST BIT_2
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#define UART1_CLK_RST_FNCLKSEL_MSK SHIFT4(0x7)
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#define UART1_CLK_RST_FNCLKSEL_BASE 4
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//0x008 offset Clock/Reset Control Register for GPIO
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#define GPIO_CLK_RST_APBCLK BIT_0
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#define GPIO_CLK_RST_FNCLK BIT_1
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#define GPIO_CLK_RST_RST BIT_2
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#define GPIO_CLK_RST_FNCLKSEL_MSK SHIFT4(0x7)
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#define GPIO_CLK_RST_FNCLKSEL_BASE 4
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//0x00c offset Clock/Reset Control Register for PWM 0
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#define PWM0_CLK_RST_APBCLK BIT_0
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#define PWM0_CLK_RST_FNCLK BIT_1
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#define PWM0_CLK_RST_RST BIT_2
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#define PWM0_CLK_RST_FNCLKSEL_MSK SHIFT4(0x7)
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#define PWM0_CLK_RST_FNCLKSEL_BASE 4
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//0x0010 offset Clock/Reset Control Register for PWM 1
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#define PWM1_CLK_RST_APBCLK BIT_0
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#define PWM1_CLK_RST_FNCLK BIT_1
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#define PWM1_CLK_RST_RST BIT_2
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#define PWM1_CLK_RST_FNCLKSEL_MSK SHIFT4(0x7)
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#define PWM1_CLK_RST_FNCLKSEL_BASE 4
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//0x0014 offset Clock/Reset Control Register for PWM 2
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#define PWM2_CLK_RST_APBCLK BIT_0
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#define PWM2_CLK_RST_FNCLK BIT_1
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#define PWM2_CLK_RST_RST BIT_2
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#define PWM2_CLK_RST_FNCLKSEL_MSK SHIFT4(0x7)
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#define PWM2_CLK_RST_FNCLKSEL_BASE 4
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//0x0018 offset Clock/Reset Control Register for PWM 3
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#define PWM3_CLK_RST_APBCLK BIT_0
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#define PWM3_CLK_RST_FNCLK BIT_1
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#define PWM3_CLK_RST_RST BIT_2
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#define PWM3_CLK_RST_FNCLKSEL_MSK SHIFT4(0x7)
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#define PWM3_CLK_RST_FNCLKSEL_BASE 4
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//0x001c offset Clock/Reset Control Register for SSP 0
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#define SSP0_CLK_RST_APBCLK BIT_0
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#define SSP0_CLK_RST_FNCLK BIT_1
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#define SSP0_CLK_RST_RST BIT_2
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#define SSP0_CLK_RST_FNCLKSEL_MSK SHIFT4(0x7)
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#define SSP0_CLK_RST_FNCLKSEL_BASE 4
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#define SSP0_CLK_RST_SEL_SSP_FUNC_CLK BIT_7
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//0x0020 offset Clock/Reset Control Register for SSP 1
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#define SSP1_CLK_RST_APBCLK BIT_0
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#define SSP1_CLK_RST_FNCLK BIT_1
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#define SSP1_CLK_RST_RST BIT_2
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#define SSP1_CLK_RST_FNCLKSEL_MSK SHIFT4(0x7)
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#define SSP1_CLK_RST_FNCLKSEL_BASE 4
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#define SSP1_CLK_RST_SEL_SSP_FUNC_CLK BIT_7
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//0x0024 offset Clock/Reset Control Register for IPC
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#define IPC_CLK_RST_APBCLK BIT_0
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#define IPC_CLK_RST_FNCLK BIT_1
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#define IPC_CLK_RST_RST BIT_2
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#define IPC_CLK_RST_FNCLKSEL_MSK SHIFT4(0x7)
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#define IPC_CLK_RST_FNCLKSEL_BASE 4
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//0x0028 offset Clock/Reset Control Register for RTC
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#define RTC_CLK_RST_APBCLK BIT_0
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#define RTC_CLK_RST_FNCLK BIT_1
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#define RTC_CLK_RST_RST BIT_2
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#define RTC_CLK_RST_PM_POWER_SENSOR BIT_7
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#define RTC_CLK_RST_FNCLKSEL_MSK SHIFT4(0x7)
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#define RTC_CLK_RST_FNCLKSEL_BASE 4
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//0x002c offset Clock/Reset Control Register for TWSI1
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#define TWSI1_CLK_RST_APBCLK BIT_0
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#define TWSI1_CLK_RST_FNCLK BIT_1
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#define TWSI1_CLK_RST_RST BIT_2
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#define TWSI1_CLK_RST_FNCLKSEL_MSK SHIFT4(0x7)
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#define TWSI1_CLK_RST_FNCLKSEL_BASE 4
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//0x0030 offset Clock/Reset Control Register for Keypad Controller
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#define KPC_CLK_RST_APBCLK BIT_0
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#define KPC_CLK_RST_FNCLK BIT_1
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#define KPC_CLK_RST_RST BIT_2
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#define KPC_CLK_RST_FNCLKSEL_MSK SHIFT4(0x7)
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#define KPC_CLK_RST_FNCLKSEL_BASE 4
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//0x0034 offset Clock/Reset Control Register for Timer 0
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#define TIMERS0_CLK_RST_APBCLK BIT_0
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#define TIMERS0_CLK_RST_FNCLK BIT_1
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#define TIMERS0_CLK_RST_RST BIT_2
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#define TIMERS0_CLK_RST_FNCLKSEL_MSK SHIFT4(0x7)
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#define TIMERS0_CLK_RST_FNCLKSEL_BASE 4
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//0x0038 offset Clock/Reset Control Register for Trackball and Rotary
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#define TB_ROTARY_CLK_RST_APBCLK BIT_0
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#define TB_ROTARY_CLK_RST_FNCLK BIT_1
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#define TB_ROTARY_CLK_RST_RST BIT_2
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#define TB_ROTARY_CLK_RST_FNCLKSEL_MSK SHIFT4(0x7)
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#define TB_ROTARY_CLK_RST_FNCLKSEL_BASE 4
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//0x003c offset Clock/Reset Control Register for AIB
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#define AIB_CLK_RST_APBCLK BIT_0
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#define AIB_CLK_RST_FNCLK BIT_1
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#define AIB_CLK_RST_RST BIT_2
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#define AIB_CLK_RST_FNCLKSEL_MSK SHIFT4(0x7)
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#define AIB_CLK_RST_FNCLKSEL_BASE 4
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//0x0040 offset Clock/Reset Control Register for JTAG Software Emulation
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#define SW_JTAG_CLK_RST_APBCLK BIT_0
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#define SW_JTAG_CLK_RST_FNCLK BIT_1
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#define SW_JTAG_CLK_RST_RST BIT_2
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#define SW_JTAG_CLK_RST_FNCLKSEL_MSK SHIFT4(0x7)
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#define SW_JTAG_CLK_RST_FNCLKSEL_BASE 4
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//0x0044 offset Clock/Reset Control Register for Timer 1
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#define TIMERS1_CLK_RST_APBCLK BIT_0
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#define TIMERS1_CLK_RST_FNCLK BIT_1
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#define TIMERS1_CLK_RST_RST BIT_2
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#define TIMERS1_CLK_RST_FNCLKSEL_MSK SHIFT4(0x7)
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#define TIMERS1_CLK_RST_FNCLKSEL_BASE 4
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//0x0048 offset Clock/Reset Control Register for One-Wire
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#define ONEWIRE_CLK_RST_APBCLK BIT_0
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#define ONEWIRE_CLK_RST_FNCLK BIT_1
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#define ONEWIRE_CLK_RST_RST BIT_2
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#define ONEWIRE_CLK_RST_FNCLKSEL_MSK SHIFT4(0x7)
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#define ONEWIRE_CLK_RST_FNCLKSEL_BASE 4
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//0x004c offset Clock/Reset Control Register for SSP 2
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#define SSP2_CLK_RST_APBCLK BIT_0
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#define SSP2_CLK_RST_FNCLK BIT_1
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#define SSP2_CLK_RST_RST BIT_2
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#define SSP2_CLK_RST_FNCLKSEL_MSK SHIFT4(0x7)
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#define SSP2_CLK_RST_FNCLKSEL_BASE 4
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#define SSP2_CLK_RST_SEL_SSP_FUNC_CLK BIT_7
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//0x0050 AIB First Access Register
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#define APBC_ASFAR_MSK SHIFT0(0xffff)
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#define APBC_ASFAR_BASE 0
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//0x0054 AIB Secure Second Access Register
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#define APBC_ASSAR_MSK SHIFT0(0xffff)
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#define APBC_ASSAR_BASE 0
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//0x0058 DRO_TS control Register
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#define DRO_TS_dro_rst BIT_2
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#define DRO_TS_dro_func_clk_en BIT_1
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#define DRO_TS_dro_apb_clk_en BIT_0
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//0x005C I2C IO_control Access Register
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#define I2C_IO_CTRL_i2c_control_MSK SHIFT0(0xffff)
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#define I2C_IO_CTRL_i2c_control_BASE 0
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//0x0060 Clock/Reset Control Register for I2C1
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#define APBC_I2C1_CLK_RST_APBCLK BIT_0
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#define APBC_I2C1_CLK_RST_FNCLK BIT_1
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#define APBC_I2C1_CLK_RST_RST BIT_2
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#define APBC_I2C1_CLK_RST_FNCLKSEL_MSK SHIFT4(0x7)
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#define APBC_I2C1_CLK_RST_FNCLKSEL_BASE 4
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#endif
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