87 lines
3.4 KiB
C
87 lines
3.4 KiB
C
/*------------------------------------------------------------
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(C) Copyright [2006-2008] Marvell International Ltd.
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All Rights Reserved
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------------------------------------------------------------*/
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/******************************************************************************
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* MODULE IMPLEMENTATION FILE
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*******************************************************************************
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* COPYRIGHT (C) 2004 Intel Corporation.
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*
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* This file and the software in it is furnished under
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* license and may only be used or copied in accordance with the terms of the
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* license. The information in this file is furnished for informational use
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* only, is subject to change without notice, and should not be construed as
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* a commitment by Intel Corporation. Intel Corporation assumes no
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* responsibility or liability for any errors or inaccuracies that may appear
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* in this document or any software that may be provided in association with
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* this document.
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* Except as permitted by such license, no part of this document may be
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* reproduced, stored in a retrieval system, or transmitted in any form or by
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* any means without the express written consent of Intel Corporation.
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*
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* Title: APB Clock Control Unit HW Header file
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*
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* Filename: apbccu_hw.h
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*
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* Target, subsystem: Tavor Platform
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*
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* Authors: Abraham Coifman
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*
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* Description: APB Clock Control Unit HW Header file.
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*
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* Last Modified: <date>
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*
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* Notes:
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******************************************************************************/
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#ifndef _APBCCU_HW_H_
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#define _APBCCU_HW_H_
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#include "global_types.h"
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#define ARBEL_HW_BASE_ADDRESS 0xD4060000L
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#define APBC_HW_BASE_ADDRESS ( ARBEL_HW_BASE_ADDRESS + 0x104 )
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/* ACCU Registers Definitions: */
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typedef volatile struct {
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UINT32 APBC; // APB Control Read/Write
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} APBCCUController;
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#define APBCCURegisters ( *( APBCCUController * )APBC_HW_BASE_ADDRESS )
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/* APBC register Bits definitions */
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#define APBC_PDIV_MASK 0x00000003
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#define APBC_PGATE_MASK 0x00000004
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#define APBC_ARDY_MASK 0x00000008
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/* macro definitions: */
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// Set PGATE bit:
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#define APBC_CLOCK_GATE_SET ( TURN_BIT_ON(APBCCURegisters.APBC, APBC_PGATE_MASK) )
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// Reset PGATE bit:
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#define APBC_CLOCK_GATE_RESET ( TURN_BIT_OFF(APBCCURegisters.APBC, APBC_PGATE_MASK) )
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// Get PGATE bit (bit No. 3):
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#define APBC_CLOCK_GATE_GET(m) ( (m) = (APBCCU_StatusE)( (APBCCURegisters.APBC & APBC_PGATE_MASK) >> 2 ) )
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// Set ARDY bit:
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#define APBC_READY_CONTROL_SET ( TURN_BIT_ON(APBCCURegisters.APBC, APBC_ARDY_MASK) )
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// Reset ARDY bit:
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#define APBC_READY_CONTROL_RESET ( TURN_BIT_OFF(APBCCURegisters.APBC, APBC_ARDY_MASK) )
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// Get ARDY bit ( bit No. 4):
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#define APBC_READY_CONTROL_GET(m) ( (m) = (APBCCU_ReadyE)( (APBCCURegisters.APBC & APBC_ARDY_MASK) >> 3 ) )
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// Set Division value at PDIV field (val = 0-3)
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#define APBC_DIVISION_VALUE_SET(val) ( APBCCURegisters.APBC = (APBCCURegisters.APBC & ~APBC_PDIV_MASK) | \
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( val & 0x03 ) )
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// Get division value from PDIV field
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#define APBC_DIVISION_VALUE_GET(m) ( (m) = (APBCCU_ClkDivE)(APBCCURegisters.APBC & APBC_PDIV_MASK))
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#endif //_APBCCU_HW_H_
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