385 lines
13 KiB
C
385 lines
13 KiB
C
/*------------------------------------------------------------
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(C) Copyright [2006-2008] Marvell International Ltd.
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All Rights Reserved
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------------------------------------------------------------*/
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/************************************************************************/
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/* COPYRIGHT (C) 2002 Intel Corporation. */
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/* */
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/* This file and the software in it is furnished under */
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/* license and may only be used or copied in accordance with the terms */
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/* of the license. The information in this file is furnished for */
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/* informational use only, is subject to change without notice, and */
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/* should not be construed as a commitment by Intel Corporation. */
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/* Intel Corporation assumes no responsibility or liability for any */
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/* errors or inaccuracies that may appear in this document or any */
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/* software that may be provided in association with this document. */
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/* Except as permitted by such license, no part of this document may */
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/* be reproduced, stored in a retrieval system, or transmitted in any */
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/* form or by any means without the express written consent of Intel */
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/* Corporation. */
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/* */
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/* Title: Communication Subsystem Power Management Unit Header File */
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/* */
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/* Filename: cpmu.h */
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/* */
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/* Author: Olga Fomenko */
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/* */
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/* Project, Target, subsystem: Tavor, Arbel, HOP */
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/* */
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/* Remarks: - */
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/* */
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/* Created: 20/04/2005 */
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/* */
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/* Modified: */
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/************************************************************************/
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#ifndef _CPMU_H_
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#define _CPMU_H_
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#include "commccu.h" //including commccu because we must use CommCCU_SystemPLLFreqE enum to update CPCR
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typedef enum
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{// this type describes banks of L2 memory
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// to assemble a combination of any banks use
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// bitwise "or" operator for example:
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// CPMU_L2BANK_2|CPMU_L2BANK_10|CPMU_L2BANK_14
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// enum numeration matches to mask of status bits in appropriate register
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CPMU_L2BANK_0 = 1<<0,
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CPMU_L2BANK_1 = 1<<1,
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CPMU_L2BANK_2 = 1<<2,
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CPMU_L2BANK_3 = 1<<3,
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CPMU_L2BANK_4 = 1<<4,
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CPMU_L2BANK_5 = 1<<5,
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CPMU_L2BANK_6 = 1<<6,
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CPMU_L2BANK_7 = 1<<7,
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CPMU_L2BANK_8 = 1<<8,
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CPMU_L2BANK_9 = 1<<9,
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CPMU_L2BANK_10 = 1<<10,
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CPMU_L2BANK_11 = 1<<11,
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CPMU_L2BANK_12 = 1<<12,
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CPMU_L2BANK_13 = 1<<13,
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CPMU_L2BANK_14 = 1<<14,
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CPMU_L2BANK_15 = 1<<15,
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CPMU_L2ALLBANKS = 0xFFFF
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}CPMU_L2BankE;
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typedef enum
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{
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CPMU_L2BS_RETAIN_D0_D2 = 0,
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CPMU_L2BS_RETAIN_D0_NOT_D2,
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CPMU_L2BS_NOT_RETAIN_D0_D2
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}CPMU_L2BankStateE;
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typedef enum
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{
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// the bits control thi functionality are in 2 different registers, so
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// serial numeration is accidental
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// for a fact numeration matches shifting to control bits in appropriate
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// registers
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CPMU_RD2R_VCC_SRAM = 16, //CPCR
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CPMU_RD2R_VCC_COMM = 8, //CPCR
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CPMU_RD2R_VCTCXO = 4, // CPCR
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CPMU_RD2R_MEM_ARBEL = 2, // ITCM, DTCM/AHB DSRAM - CL1CR
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CPMU_RD2R_MEM_GB_L1= 1 // CL1CR
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}CPMU_RetainInD2ResourceE;
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typedef enum
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{// to assemble a combination of any peripherals use logical "or" operator
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// enum numeration matches to appropriate control bits mask
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CPMU_PERIPHERAL_USIM = 3<<0,
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//CPMU_PERIPHERAL_USB = 3<<2, // this oeripheral isn't available
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CPMU_PERIPHERAL_GSSP2 = 3<<4, // ASSP
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CPMU_PERIPHERAL_GSSP1 = 3<<6, // SSP
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CPMU_PERIPHERAL_MSL = 3<<8,
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CPMU_PERIPHERAL_I2C = 3<<10,
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CPMU_ALL_2_RESET_ASSERTION_PER = 0xFF3,
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CPMU_PERIPHERAL_SELECT_0= 1<<12, // 6
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CPMU_PERIPHERAL_SELECT_1= 1<<13,
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CPMU_PERIPHERAL_SELECT_2= 1<<14,
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CPMU_PERIPHERAL_SELECT_3= 1<<15,
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CPMU_PERIPHERAL_SELECT_4= 1<<16,
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CPMU_PERIPHERAL_SELECT_5= 1<<17,
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CPMU_PERIPHERAL_SELECT_6= 1<<18,
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CPMU_PERIPHERAL_SELECT_7= 1<<19,
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//CPMU_PERIPHERAL_MODEMS= 1<<20 // this oeripheral isn't available
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CPMU_ALL_COMMON_RESET_ASSERTION_PER = 0xFF000,
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CPMU_ALL_REGULAR_PER = 0xFFF
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}CPMU_PeripheralE;
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typedef enum
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{ // enum eumeration matches field value for suitable control bits
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// no power mode change
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//CPMU_PM_NO_CHANGE = 0,
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CPMU_PM_D0 = 0,
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// enter D2 state after both cores enter C1
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CPMU_PM_ENTER_D2_AFTER_BOTH_CORES_IN_C1,
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// enter D2 state after both cores enter C1 AND
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// the modem slow clock has bb_d2_entry_ok signal is asserted
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CPMU_PM_ENTER_D2_AFTER_BOTH_CORES_IN_C1_AND_MODEM_SIGNAL,
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// enter D4 state after both cores enter C1
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CPMU_PM_ENTER_D4_AFTER_BOTH_CORES_IN_C1
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}CPMU_PowerModeE;
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typedef enum
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{
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CWESR_WAKE_UP_EN =1,
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CWESR_RST_STICKY ,
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SW_BIT_BOTH
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} PmD2Swbits ;
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// due to compiler warnings on enum with value of 0xffffffff - it is now a define.
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#define CPMU_ENABLE 0xFFFFFFFF
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#define CPMU_DISABLE 0x00000000
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typedef UINT32 CPMU_State;
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typedef enum
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{// to assemble a combination of any events use
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// bitwise "or" operator
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CPMU_WAKEUP_UART_EVENT_0 = 1, // reset bit WRST_WR/RD[5]
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CPMU_WAKEUP_CGPIO_EVENT_1 = 1<<1, // reset bit WRST_WR/RD[6]
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//CPMU_WAKEUP_GP_EVENT_2 = 1<<2,
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CPMU_WAKEUP_WBCDM_EVENT = 1<<2,
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//CPMU_WAKEUP_GP_EVENT_3 = 1<<3,
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CPMU_WAKEUP_GSSP1_EVENT = 1<<3, // reset bit WRST_WR/RD[2]
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CPMU_WAKEUP_ACIPC_EVENT_4 = 1<<4, // AC IPC from APPS
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//CPMU_WAKEUP_GP_EVENT_5 = 1<<5,
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CPMU_WAKEUP_GSSP2_EVENT = 1<<5, // reset bit WRST_WR/RD[3]
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CPMU_WAKEUP_GP_EVENT_6 = 1<<6,
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//CPMU_WAKEUP_GP_EVENT_7 = 1<<7,
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CPMU_WAKEUP_USIM_EVENT = 1<<7, // reset bit WRST_WR/RD[1]
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CPMU_WAKEUP_GP_EVENT_8 = 1<<8, // not connected for A0
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CPMU_WAKEUP_GP_EVENT_9 = 1<<9, // not connected for A0
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//CPMU_WAKEUP_GP_EVENT_10 = 1<<10,
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CPMU_WAKEUP_I2C_EVENT = 1<<10, // common I2C for A0; reset bit WRST_WR/RD[0]
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CPMU_WAKEUP_GP_EVENT_11 = 1<<11, // not connected for A0
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CPMU_WAKEUP_GP_EVENT_12 = 1<<12, // not connected for A0
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//CPMU_WAKEUP_GP_EVENT_13 = 1<<13,
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CPMU_WAKEUP_PMIC_EVENT = 1<<13, // reset bit WRST_WR/RD[4]
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CPMU_WAKEUP_GP_EVENT_14 = 1<<14,
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CPMU_WAKEUP_GP_EVENT_15 = 1<<15,
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CPMU_WAKEUP_MSL_EVENT = 1<<16, // reserved for A0
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CPMU_WAKEUP_TIMER_EVENT = 1<<17,
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CPMU_WAKEUP_WDT_EVENT = 1<<18,
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CPMU_WAKEUP_MODEM_SCK_EVENT = 1<<19,
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CPMU_WAKEUP_ALL_GP = 0xFFFF,
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CPMU_WAKEUP_ALL_ENABLE_DISABLE = 0x3FFFF,
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#ifdef PHS_SW_DEMO_TTC_PM
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CPMU_NUMBER_OF_WAKEUP_SOURCES = 32
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#else
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CPMU_NUMBER_OF_WAKEUP_SOURCES = 20
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#endif
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}CPMU_WakeUpEventE;
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typedef enum
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{// enum eumeration matches field value for suitable control bits
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CPMU_INTERRUPT_FREQUENCY_CHANGE = 1,
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CPMU_INTERRUPT_PMIC = 2,
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CPMU_INTERRUPT_DETECT_MODULE_CHANGE = 4
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}CPMU_InterruptE;
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typedef enum
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{
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CPMU_EDGE_RISING = 0, // positive
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CPMU_EDGE_FALLING, // negative
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CPMU_EDGE_DONT_CARE
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}CPMU_EdgeE;
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typedef enum
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{
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CPMU_RESET_BUS = 2,
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CPMU_RESET_FUNCTIONAL = 1,
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CPMU_RESET_BOTH = 3,
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CPMU_RESET_DONT_CARE
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}CPMU_ResetTypeE;
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typedef enum
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{
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CPMU_ET_WAKEUP_EVENT,
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CPMU_ET_INTERRUPT
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}CPMU_EventTypeE;
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typedef enum
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{
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CPMU_RC_WRONG_PARAMETER,
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CPMU_RC_INTC_ERROR,
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CPMU_RC_OK
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}CPMU_ReturnCodeE;
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typedef enum
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{
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// enum numeration matches numbers of appropriate bits in status register
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CPMU_EDR_WDT_ACTIVATION = 27,
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CPMU_EDR_WCDMA_MODEM = 5,
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CPMU_EDR_DDR = 4,
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CPMU_EDR_READ_DISABLE_HOLD = 3
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}CPMU_EnableDisableResourcesE;
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// TBD - Yohai
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typedef enum
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{
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// the enum numeration matches to a value of suitable control bits
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CPMU_PMIC_COMMAND_SET_0 = 0,
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CPMU_PMIC_COMMAND_SET_1,
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CPMU_PMIC_COMMAND_SET_2,
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CPMU_PMIC_COMMAND_SET_3
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}CPMU_PMICCommandSetE;
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// Reasons of Last Reset -
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// TEMPORARY DEFINITION from previous version of module
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typedef enum
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{
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CPMU_LRR_COMM_SUBSYTEM_RESET = 0,
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CPMU_LRR_WATCHDOG_TIMEOUT_RESET,
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CPMU_LRR_D2_EXIT_RESET,
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CPMU_LRR_ERROR
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}CPMU_LastResetReasonE;
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typedef enum
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{
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CPMU_BIT_DISABLE = 0,
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CPMU_BIT_ENABLE,
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}CPMU_Bit_StatusE;
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// On A0 some bits PM related where added in different registres set at the top (not specific HW macro),
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// add control to them ...
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typedef enum
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{ //GPBMCSR(bit0) - 0
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CPMU_WB_GSM_TCU_CE_SEL = 0, //TCU_CE_SEL (bit 0)
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//MVT_CTL (bit 0, 2, 3) - 1,2,3,4
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CPMU_WB_GSM_SLP_TIMER_SEL, //SGW (bit 0)
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CPMU_GSM_STKY_RST, //GWE_STKY_RST (bit 2)
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CPMU_WB_SLEEP_MODULE_POLARITY_FIX, //(not documented yet) (bit 3)
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//GPBMCSR (bit 1,2) - 6,7
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CPMU_UART_CLK_EN, //HUCE (bit1)
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CPMU_USIM_NMOS_DISENGAGE, //UPEND (bit2)
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CPMU_NUM_OF_CONROL_BITS
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}CPMU_Control_BitsE;
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// TBD - adjust these definition with Raviv
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typedef void (*CPMUL2PowerChangeNotifyFn) (void);
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typedef void (*CPMUPMICCOmmandSetNotifyFn) (void);
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typedef void (*CPMUFrequencyChangeNotifyFn) (void);
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typedef UINT32 CPMU_EventStatus;
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typedef UINT32 CPMU_L2Status;
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typedef UINT32 CPMU_WakeupEventCombination;
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#define CPMU_IS_THIS_EVENT_DETECTED(status, event) (status & event)
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//primary definition of CPMU API
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// events
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CPMU_EventStatus CPMUEventDetect (CPMU_EventTypeE eventType);
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void CPMUEventStatusClear (CPMU_EventTypeE eventType,
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UINT32 mask);
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//CPCR
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void CPMUWCDMAPowerStateSet (CPMU_State enableDisable);
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void CPMURetainResourceInD2StateSet
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(UINT32 resource,
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CPMU_State enableDisable);
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void CPMUPowerModeSet (CPMU_PowerModeE mode);
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// CPSR status
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// pay attention this bit is only SW, without HW implication
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void CPMUEventTrackingFieldSet (UINT8 event /*0-0xF*/);
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UINT8 CPMUEventTrackingFieldGet (void);
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void CPMU_set_GPB_Users_Counter (INT32 *pUserCount);
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void CPMUWDTControlBitSet (CPMU_State enableDisable);
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CPMU_State CPMUStateGet (CPMU_EnableDisableResourcesE res);
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//CPMU_State CPMUWDTControlBitGet (void);
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// end of SW bits
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//CPMU_State CPMUWCDMAPowerStateGet (void);
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//CPMU_State CPMUDDRStateGet (void);
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//CPMU_State CPMUGPIOReadHoldStateGet (void);
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void CPMUGPIOReadHoldStateClear (void);
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//CPR
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BOOL CPMUPMICIsCommandBeingRequested (void);
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void CPMUPMICCommandStatusClear (void);
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void CPMUPMICCommandSetDetermine (CPMU_PMICCommandSetE set);
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void CPMUPMICCOmmandInD2StateSet (CPMU_State enableDisable);
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// CWER
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void CPMUWakeupEventStateSet (CPMU_WakeupEventCombination wakeupEvent,
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CPMU_EdgeE edge,
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CPMU_State enableDisable);
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CPMU_State CPMUWakeupEventStateGet (CPMU_WakeUpEventE wakeupEvent);
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//CRAR
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CPMU_ReturnCodeE CPMUPeripheralHeldInResetStateSet
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(UINT32 peripheral,
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CPMU_ResetTypeE reset,
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CPMU_State enableDisable);
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//CIER
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CPMU_ReturnCodeE CPMUInterruptStateSet (UINT32 interrupt,
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CPMU_State enableDisable);
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void CPMURegister (CPMUL2PowerChangeNotifyFn l2PowerChangeNotifyFn,
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CPMUPMICCOmmandSetNotifyFn pmicCommnadSetNotifyFn,
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CPMUFrequencyChangeNotifyFn freqChangeNotifyFn);
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void CPMUPhase1Init (void);
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CPMU_ReturnCodeE CPMUPhase2Init (void);
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void CPMUD1AutoEntyStateSet (CPMU_State enableDisable);
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void CPMUExternalWakeUpControl (CPMU_WakeUpEventE event, CPMU_State enableDisable);
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//CGRAR, CCRAR
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void CPMUD2AddressSet (void* armD2ResetAddress,
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void* gbD2ResetAddress);
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void CPMUControlBitSet (CPMU_Control_BitsE controlBit ,CPMU_Bit_StatusE enableDisable); //rafiagiv 27.12
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CPMU_Bit_StatusE CPMUControlBitGet (CPMU_Control_BitsE controlBit);
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void CPMUChangeCPCRVoltageLevelValue(CommCCU_SystemPLLFreqE FreqValue, UINT32 VoltageLevel);
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void CPMUCwesrSwBitSet (PmD2Swbits Bit_num);
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BOOL CPMUUsimNmosEngageInUse(void);
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void CpmuGetSysCOMMcapabilities (void);
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void CpmuWaitAndClearFreqChangeInt(void);
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/**************************************************************************
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***************** Internal API used by COMM PM SW *******************
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**************************************************************************/
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CPMU_ReturnCodeE CPMUGetLastResetReason(CPMU_LastResetReasonE *retVal);
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CPMU_ReturnCodeE CPMUClearLastResetReason(void);
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void CpmuSetD2FreqWithPP3VoltageLevel(void);
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void commccuSetVoltageChangeInHW(CommCCU_SystemPLLFreqE Freq);
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#endif //_CPMU_H_
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