100 lines
5.7 KiB
C
100 lines
5.7 KiB
C
/*------------------------------------------------------------
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(C) Copyright [2006-2008] Marvell International Ltd.
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All Rights Reserved
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------------------------------------------------------------*/
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/************************************************************************/
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/* COPYRIGHT (C) 2002 Intel Corporation. */
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/* */
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/* This file and the software in it is furnished under */
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/* license and may only be used or copied in accordance with the terms */
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/* of the license. The information in this file is furnished for */
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/* informational use only, is subject to change without notice, and */
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/* should not be construed as a commitment by Intel Corporation. */
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/* Intel Corporation assumes no responsibility or liability for any */
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/* errors or inaccuracies that may appear in this document or any */
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/* software that may be provided in association with this document. */
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/* Except as permitted by such license, no part of this document may */
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/* be reproduced, stored in a retrieval system, or transmitted in any */
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/* form or by any means without the express written consent of Intel */
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/* Corporation. */
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/* */
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/* Title: Communication Subsystem Power Management Unit HW Header File */
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/* */
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/* Filename: cpmu_hw.h */
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/* */
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/* Author: Arik Chikvashvili */
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/* */
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/* Project, Target, subsystem: Tavor, Arbel, HOP */
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/* */
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/* Remarks: Note that this code controls all of Grayback's registers */
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/* eventhough it runs from Arbel !!! */
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/* The purpose is to provide with a TEMPORARY tool that will */
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/* turn all the clocks on. */
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/* */
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/* Created: 8/11/2004 */
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/* */
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/* Modified: */
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/************************************************************************/
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#ifndef _CPMU_HW_H_
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#define _CPMU_HW_H_
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#include "global_types.h" // needed for the UINT32 definition.
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#define CPMU_BASE_ADDRESS 0xF00E0100L
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// Defines the Grayback CCU HW-Structure
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/** (See GB IAS for special limitaions regarding reserved bits and other remarks) **/
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typedef volatile struct
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{
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UINT32 CPCR; //Communication Subsystem Power Control Register R/W
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UINT32 CL1CR; //Communication Subsystem L1 Memory Configuration Register R/W N O T E: Does not exists in TAVOR_P products
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UINT32 CL2CR; //Communication Subsystem L2 Memory Configuration Register R/W N O T E: Does not exists in TAVOR_P products
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UINT32 CL2DR; //Communication Subsystem L2 Memory Detection Register R/S N O T E: Does not exists in TAVOR_P products
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UINT32 CL2SR; //Communication Subsystem L2 Memory Status Register R N O T E: Does not exists in TAVOR_P products
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UINT32 CMCR; //Communication Subsystem Miscellaneous Counters Register R/W
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UINT32 CPSR; //Communication Subsystem Power Status Register R/W or R
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UINT32 CPR; //Communication Subsystem PMIC Register R/S
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UINT32 CWER; //Communication Subsystem Wakeup Enable Register R/W
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UINT32 CGPDR; //Communication Subsystem General Purpose Detector Register R/W
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UINT32 CWESR; //Communication Subsystem Wakeup Events Status Register R/W
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UINT32 CRAR; //Communication Subsystem Reset Assertion Register R/W
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UINT32 CIER; //Communication Subsystem Interrupt Enable Register R/W
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UINT32 CISR; //Communication Subsystem Interrupt Status Register R/W
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UINT32 CGRAR; //Communication Grayback Core Reset Address Register R/W
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UINT32 CCRAR; //Communication Controller Reset Address Register R/W
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UINT32 CGDES; //Communication Grayback D2 Entry Status R/W
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UINT32 CCDES; //Communication Controller D2 Entry Status R/W
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UINT32 CGDEC; //Communication Grayback Core D2 Entry Control
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UINT32 CCDEC; //Communication Controller D2 Entry Control
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UINT32 reserved [(0x200-0x150)/sizeof(UINT32)]; // 0x150...0x1FC reserved
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UINT32 CSSR; //Communication Subsystem Spare Register R/W only half
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} CPMU_HW_Registers;
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// additional registers
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#define CPMU_GPBLCSR_REG_ADDR 0xF0260010
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#define CPMU_WRST_WR_REG_ADDR 0xF0240000
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#define CPMU_WRST_RD_REG_ADDR 0xF0240004
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#define CPMU_MCSR_GPB_REG_ADDR 0xF024000C
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#define CPMU_MVT_CTL_REG_ADDR 0xF0203030
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#define CISR_FC_IS_MASK 0x00000001
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//acording to CPCR definitions
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#define CPCR_FREQ_52MHZ_MASK 0x000000C0UL //bits 6,7
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#define CPCR_FREQ_104MHZ_MASK 0x00000300UL //bits 8,9
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#define CPCR_FREQ_156MHZ_MASK 0x00000C00UL //bits 10,11
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#define CPCR_FREQ_208MHZ_MASK 0x00003000UL //bits 12,13
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#define CPCR_FREQ_312MHZ_MASK 0x00030000UL //bits 16,17
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#define CPCR_FREQ_52MHZ_OFFSET 6
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#define CPCR_FREQ_104MHZ_OFFSET 8
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#define CPCR_FREQ_156MHZ_OFFSET 10
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#define CPCR_FREQ_208MHZ_OFFSET 12
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#define CPCR_FREQ_312MHZ_OFFSET 16
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#endif /* _CPMU_HW_H_ */
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