574 lines
32 KiB
C
574 lines
32 KiB
C
/*********************************************************************
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* *
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* Copyright (c) 2010 Shanghai FuDan MicroElectronic Inc, Ltd. *
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* All rights reserved. Licensed Software Material. *
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* *
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* Unauthorized use, duplication, or distribution is strictly *
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* prohibited by law. *
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* *
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**********************************************************************/
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#ifndef _READER_REG_H
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#define _READER_REG_H
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#define JREG_PAGE0 0x00 //Page register in page 0
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#define JREG_COMMAND 0x01 //Contains Command bits, PowerDown bit and bit to switch receiver off.
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#define JREG_COMMIEN 0x02 //Contains Communication interrupt enable bits andbit for Interrupt inversion.
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#define JREG_DIVIEN 0x03 //Contains RfOn, RfOff, CRC and Mode Interrupt enable and bit to switch Interrupt pin to PushPull mode.
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#define JREG_COMMIRQ 0x04 //Contains Communication interrupt request bits.
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#define JREG_DIVIRQ 0x05 //Contains RfOn, RfOff, CRC and Mode Interrupt request.
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#define JREG_ERROR 0x06 //Contains Protocol, Parity, CRC, Collision, Buffer overflow, Temperature and RF error flags.
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#define JREG_STATUS1 0x07 //Contains status information about Lo- and HiAlert, RF-field on, Timer, Interrupt request and CRC status.
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#define JREG_STATUS2 0x08 //Contains information about internal states (Modemstate),Mifare states and possibility to switch Temperature sensor off.
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#define JREG_FIFODATA 0x09 //Gives access to FIFO. Writing to register increments theFIFO level (register 0x0A), reading decrements it.
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#define JREG_FIFOLEVEL 0x0A //Contains the actual level of the FIFO.
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#define JREG_WATERLEVEL 0x0B //Contains the Waterlevel value for the FIFO
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#define JREG_CONTROL 0x0C //Contains information about last received bits, Initiator mode bit, bit to copy NFCID to FIFO and to Start and stopthe Timer unit.
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#define JREG_BITFRAMING 0x0D //Contains information of last bits to send, to align received bits in FIFO and activate sending in Transceive*/
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#define JREG_COLL 0x0E //Contains all necessary bits for Collission handling
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#define JREG_RFU0F 0x0F //Currently not used.
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#define JREG_PAGE1 0x10 //Page register in page 1
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#define JREG_MODE 0x11 //Contains bits for auto wait on Rf, to detect SYNC byte in NFC mode and MSB first for CRC calculation
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#define JREG_TXMODE 0x12 //Contains Transmit Framing, Speed, CRC enable, bit for inverse mode and TXMix bit.
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#define JREG_RXMODE 0x13 //Contains Transmit Framing, Speed, CRC enable, bit for multiple receive and to filter errors.
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#define JREG_TXCONTROL 0x14 //Contains bits to activate and configure Tx1 and Tx2 and bit to activate 100% modulation.
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#define JREG_TXAUTO 0x15 //Contains bits to automatically switch on/off the Rf and to do the collission avoidance and the initial rf-on.
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#define JREG_TXSEL 0x16 //Contains SigoutSel, DriverSel and LoadModSel bits.
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#define JREG_RXSEL 0x17 //Contains UartSel and RxWait bits.
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#define JREG_RXTRESHOLD 0x18 //Contains MinLevel and CollLevel for detection.
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#define JREG_DEMOD 0x19 //Contains bits for time constants, hysteresis and IQ demodulator settings.
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#define JREG_FELICANFC 0x1A //Contains bits for minimum FeliCa length received and for FeliCa syncronisation length.
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#define JREG_FELICANFC2 0x1B //Contains bits for maximum FeliCa length received.
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#define JREG_MIFARE 0x1C //Contains Miller settings, TxWait settings and MIFARE halted mode bit.
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#define JREG_MANUALRCV 0x1D //Currently not used.
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#define JREG_RFU1E 0x1E //Currently not used.
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#define JREG_SERIALSPEED 0x1F //Contains speed settings for serila interface.
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#define JREG_PAGE2 0x20 //Page register in page 2
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#define JREG_CRCRESULT1 0x21 //Contains MSByte of CRC Result.
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#define JREG_CRCRESULT2 0x22 //Contains LSByte of CRC Result.
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#define JREG_GSNLOADMOD 0x23 //Contains the conductance and the modulation settings for the N-MOS transistor only for load modulation (See difference to JREG_GSN!).
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#define JREG_MODWIDTH 0x24 //Contains modulation width setting.
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#define JREG_TXBITPHASE 0x25 //Contains TxBitphase settings and receive clock change.
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#define JREG_RFCFG 0x26 //Contains sensitivity of Rf Level detector, the receiver gain factor and the RfLevelAmp.
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#define JREG_GSN 0x27 //Contains the conductance and the modulation settings for the N-MOS transistor during active modulation (no load modulation setting!).
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#define JREG_CWGSP 0x28 //Contains the conductance for the P-Mos transistor.
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#define JREG_MODGSP 0x29 //Contains the modulation index for the PMos transistor.
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#define JREG_TMODE 0x2A //Contains all settings for the timer and the highest 4 bits of the prescaler.
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#define JREG_TPRESCALER 0x2B //Contais the lowest byte of the prescaler.
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#define JREG_TRELOADHI 0x2C //Contains the high byte of the reload value.
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#define JREG_TRELOADLO 0x2D //Contains the low byte of the reload value.
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#define JREG_TCOUNTERVALHI 0x2E //Contains the high byte of the counter value.
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#define JREG_TCOUNTERVALLO 0x2F //Contains the low byte of the counter value.
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#define JREG_PAGE3 0x30 //Page register in page 3
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#define JREG_TESTSEL1 0x31 //Test register
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#define JREG_TESTSEL2 0x32 //Test register
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#define JREG_TESTPINEN 0x33 //Test register
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#define JREG_TESTPINVALUE 0x34 //Test register
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#define JREG_TESTBUS 0x35 //Test register
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#define JREG_AUTOTEST 0x36 //Test register
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#define JREG_VERSION 0x37 //Contains the product number and the version .
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#define JREG_ANALOGTEST 0x38 //Test register
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#define JREG_TESTDAC1 0x39 //Test register
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#define JREG_TESTDAC2 0x3A //Test register
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#define JREG_TESTADC 0x3B //Test register
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#define JREG_ANALOGUETEST1 0x3C //Test register
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#define JREG_ANALOGUETEST0 0x3D //Test register
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#define JREG_ANALOGUETPD_A 0x3E //Test register
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#define JREG_ANALOGUETPD_B 0x3F //Test register
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#define CMD_MASK 0xF0
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#define CMD_IDLE 0x00
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#define CMD_CONFIGURE 0x01
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#define CMD_GEN_RAND_ID 0x02
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#define CMD_CALC_CRC 0x03
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#define CMD_TRANSMIT 0x04
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#define CMD_NOCMDCHANGE 0x07
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#define CMD_RECEIVE 0x08
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#define CMD_TRANSCEIVE 0x0C
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#define CMD_AUTOCOLL 0x0D
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#define CMD_AUTHENT 0x0E
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#define CMD_SOFT_RESET 0x0F
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/* /////////////////////////////////////////////////////////////////////////////
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* Bit Definitions
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* ////////////////////////////////////////////////////////////////////////// */
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/*name FM5114B_RF Bit definitions of Page 0 */
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/* Command Register (01) */
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#define JBIT_RCVOFF 0x20 /*Switches the receiver on/off. */
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#define JBIT_POWERDOWN 0x10 /*Switches FM5114B_RF to Power Down mode. */
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/* CommIEn Register (02) */
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#define JBIT_IRQINV 0x80 /*Inverts the output of IRQ Pin. */
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/* DivIEn Register (03) */
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#define JBIT_IRQPUSHPULL 0x80 /*Sets the IRQ pin to Push Pull mode. */
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/* CommIEn and CommIrq Register (02, 04) */
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#define JBIT_TXI 0x40 /*Bit position for Transmit Interrupt Enable/Request.*/
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#define JBIT_RXI 0x20 /*Bit position for Receive Interrupt Enable/Request. */
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#define JBIT_IDLEI 0x10 /*Bit position for Idle Interrupt Enable/Request. */
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#define JBIT_HIALERTI 0x08 /*Bit position for HiAlert Interrupt Enable/Request. */
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#define JBIT_LOALERTI 0x04 /*Bit position for LoAlert Interrupt Enable/Request. */
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#define JBIT_ERRI 0x02 /*Bit position for Error Interrupt Enable/Request. */
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#define JBIT_TIMERI 0x01 /*Bit position for Timer Interrupt Enable/Request. */
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/* DivIEn and DivIrq Register (03, 05) */
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#define JBIT_SIGINACT 0x10 /*Bit position for SiginAct Interrupt Enable/Request. */
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#define JBIT_MODEI 0x08 /*Bit position for Mode Interrupt Enable/Request. */
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#define JBIT_CRCI 0x04 /*Bit position for CRC Interrupt Enable/Request. */
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#define JBIT_RFONI 0x02 /*Bit position for RF On Interrupt Enable/Request. */
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#define JBIT_RFOFFI 0x01 /*Bit position for RF Off Interrupt Enable/Request. */
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/* CommIrq and DivIrq Register (04, 05) */
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#define JBIT_SET 0x80 /*Bit position to set/clear dedicated IRQ bits. */
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/* Error Register (06) */
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#define JBIT_WRERR 0x40 /*Bit position for Write Access Error. */
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#define JBIT_TEMPERR 0x40 /*Bit position for Temerature Error. */
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#define JBIT_RFERR 0x20 /*Bit position for RF Error. */
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#define JBIT_BUFFEROVFL 0x10 /*Bit position for Buffer Overflow Error. */
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#define JBIT_COLLERR 0x08 /*Bit position for Collision Error. */
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#define JBIT_CRCERR 0x04 /*Bit position for CRC Error. */
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#define JBIT_PARITYERR 0x02 /*Bit position for Parity Error. */
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#define JBIT_PROTERR 0x01 /*Bit position for Protocol Error. */
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/* Status 1 Register (07) */
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#define JBIT_CRCOK 0x40 /*Bit position for status CRC OK. */
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#define JBIT_CRCREADY 0x20 /*Bit position for status CRC Ready. */
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#define JBIT_IRQ 0x10 /*Bit position for status IRQ is active. */
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#define JBIT_TRUNNUNG 0x08 /*Bit position for status Timer is running. */
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#define JBIT_RFON 0x04 /*Bit position for status RF is on/off. */
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#define JBIT_HIALERT 0x02 /*Bit position for status HiAlert. */
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#define JBIT_LOALERT 0x01 /*Bit position for status LoAlert. */
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/* Status 2 Register (08) */
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#define JBIT_TEMPSENSOFF 0x80 /*Bit position to switch Temperture sensors on/off. */
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#define JBIT_I2CFORCEHS 0x40 /*Bit position to forece High speed mode for I2C Interface. */
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#define JBIT_MFSELECTED 0x10 /*Bit position for card status Mifare selected. */
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#define JBIT_CRYPTO1ON 0x08 /*Bit position for reader status Crypto is on. */
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/* FIFOLevel Register (0A) */
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#define JBIT_FLUSHFIFO 0x80 /*Clears FIFO buffer if set to 1 */
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/* Control Register (0C) */
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#define JBIT_TSTOPNOW 0x80 /*Stops timer if set to 1. */
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#define JBIT_TSTARTNOW 0x40 /*Starts timer if set to 1. */
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#define JBIT_WRNFCIDTOFIFO 0x20 /*Copies internal stored NFCID3 to actual position of FIFO. */
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#define JBIT_INITIATOR 0x10 /*Sets Initiator mode. */
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/* BitFraming Register (0D) */
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#define JBIT_STARTSEND 0x80 /*Starts transmission in transceive command if set to 1. */
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/* BitFraming Register (0E) */
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#define JBIT_VALUESAFTERCOLL 0x80 /*Activates mode to keep data after collision. */
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/*name FM5114B_RF Bit definitions of Page 1
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* Below there are useful bit definition of the FM5114B_RF register set of Page 1.*/
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/* Mode Register (11) */
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#define JBIT_MSBFIRST 0x80 /*Sets CRC coprocessor with MSB first. */
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#define JBIT_DETECTSYNC 0x40 /*Activate automatic sync detection for NFC 106kbps. */
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#define JBIT_TXWAITRF 0x20 /*Tx waits until Rf is enabled until transmit is startet, else
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transmit is started immideately. */
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#define JBIT_RXWAITRF 0x10 /*Rx waits until Rf is enabled until receive is startet, else
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receive is started immideately. */
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#define JBIT_POLSIGIN 0x08 /*Inverts polarity of SiginActIrq, if bit is set to 1 IRQ occures
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when Sigin line is 0. */
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#define JBIT_MODEDETOFF 0x04 /*Deactivates the ModeDetector during AutoAnticoll command. The settings
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of the register are valid only. */
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/* TxMode Register (12) */
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#define JBIT_TXCRCEN 0x80 /*enables the CRC generation during data transmissio. */
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#define JBIT_INVMOD 0x08 /*Activates inverted transmission mode. */
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#define JBIT_TXMIX 0x04 /*Activates TXMix functionality. */
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/* RxMode Register (13) */
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#define JBIT_RXCRCEN 0x80 /*enables the CRC generation during reception.. */
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#define JBIT_RXNOERR 0x08 /*If 1, receiver does not receive less than 4 bits. */
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#define JBIT_RXMULTIPLE 0x04 /*Activates reception mode for multiple responses. */
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/* Definitions for Tx and Rx (12, 13) */
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#define JBIT_106KBPS 0x00 /*Activates speed of 106kbps. */
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#define JBIT_212KBPS 0x10 /*Activates speed of 212kbps. */
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#define JBIT_424KBPS 0x20 /*Activates speed of 424kbps. */
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#define JBIT_848KBPS 0x30 /*Activates speed of 848kbps. */
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#define JBIT_1_6MBPS 0x40 /*Activates speed of 1.6Mbps. */
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#define JBIT_3_2MBPS 0x50 /*Activates speed of 3_3Mbps. */
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#define JBIT_MIFARE 0x00 /*Activates Mifare communication mode. */
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#define JBIT_NFC 0x01 /*Activates NFC/Active communication mode. */
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#define JBIT_FELICA 0x02 /*Activates FeliCa communication mode. */
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#define JBIT_CRCEN 0x80 /*Activates transmit or receive CRC. */
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/* TxControl Register (14) */
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#define JBIT_INVTX2ON 0x80 /*Inverts the Tx2 output if drivers are switched on. */
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#define JBIT_INVTX1ON 0x40 /*Inverts the Tx1 output if drivers are switched on. */
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#define JBIT_INVTX2OFF 0x20 /*Inverts the Tx2 output if drivers are switched off. */
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#define JBIT_INVTX1OFF 0x10 /*Inverts the Tx1 output if drivers are switched off. */
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#define JBIT_TX2CW 0x08 /*Does not modulate the Tx2 output, only constant wave. */
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#define JBIT_CHECKRF 0x04 /*Does not activate the driver if an external RF is detected.
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Only valid in combination with JBIT_TX2RFEN and JBIT_TX1RFEN. */
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#define JBIT_TX2RFEN 0x02 /*Switches the driver for Tx2 pin on. */
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#define JBIT_TX1RFEN 0x01 /*Switches the driver for Tx1 pin on. */
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/* TxAuto Register (15) */
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#define JBIT_AUTORFOFF 0x80 /*Switches the RF automatically off after transmission is finished. */
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#define JBIT_FORCE100ASK 0x40 /*Activates 100%ASK mode independent of driver settings. */
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#define JBIT_AUTOWAKEUP 0x20 /*Activates automatic wakeup of the FM5114B_RF if set to 1. */
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#define JBIT_CAON 0x08 /*Activates the automatic time jitter generation by switching
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on the Rf field as defined in ECMA-340. */
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#define JBIT_INITIALRFON 0x04 /*Activate the initial RF on procedure as defined iun ECMA-340. */
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#define JBIT_TX2RFAUTOEN 0x02 /*Switches on the driver two automatically according to the
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other settings. */
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#define JBIT_TX1RFAUTOEN 0x01 /*Switches on the driver one automatically according to the
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other settings. */
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/* Demod Register (19) */
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#define JBIT_FIXIQ 0x20 /*If set to 1 and the lower bit of AddIQ is set to 0, the receiving is fixed to I channel.
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If set to 1 and the lower bit of AddIQ is set to 1, the receiving is fixed to Q channel. */
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/* Felica/NFC 2 Register (1B) */
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#define JBIT_WAITFORSELECTED 0x80 /*If this bit is set to one, only passive communication modes are possible.
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In any other case the AutoColl Statemachine does not exit. */
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#define JBIT_FASTTIMESLOT 0x40 /*If this bit is set to one, the response time to the polling command is half as normal. */
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/* Mifare Register (1C) */
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#define JBIT_MFHALTED 0x04 /*Configures the internal state machine only to answer to
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Wakeup commands according to ISO 14443-3. */
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/* RFU 0x1D Register (1D) */
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#define JBIT_PARITYDISABLE 0x10 /*Disables the parity generation and sending independent from the mode. */
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#define JBIT_LARGEBWPLL 0x08 /* */
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#define JBIT_MANUALHPCF 0x04 /* */
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/*@}*/
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/* FM5114B_RF Bit definitions of Page 2
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* Below there are useful bit definition of the FM5114B_RF register set.
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*/
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/* TxBitPhase Register (25) */
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#define JBIT_RCVCLKCHANGE 0x80 /*If 1 the receive clock may change between Rf and oscilator. */
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/* RfCFG Register (26) */
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#define JBIT_RFLEVELAMP 0x80 /*Activates the RF Level detector amplifier. */
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/* TMode Register (2A) */
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#define JBIT_TAUTO 0x80 /*Sets the Timer start/stop conditions to Auto mode. */
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#define JBIT_TAUTORESTART 0x10 /*Restarts the timer automatically after finished
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counting down to 0. */
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/*@}*/
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/* FM5114B_RF Bit definitions of Page 3
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* Below there are useful bit definition of the FM5114B_RF register set.
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*/
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/* AutoTest Register (36) */
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#define JBIT_AMPRCV 0x40 /* */
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/*@}*/
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/* /////////////////////////////////////////////////////////////////////////////
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* Bitmask Definitions
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* ////////////////////////////////////////////////////////////////////////// */
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/* Command register (0x01)*/
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#define JMASK_COMMAND 0x0F /*Bitmask for Command bits in Register JREG_COMMAND. */
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#define JMASK_COMMAND_INV 0xF0 /*Inverted bitmask of JMASK_COMMAND. */
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/* Waterlevel register (0x0B)*/
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#define JMASK_WATERLEVEL 0x3F /*Bitmask for Waterlevel bits in register JREG_WATERLEVEL. */
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/* Control register (0x0C)*/
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#define JMASK_RXBITS 0x07 /*Bitmask for RxLast bits in register JREG_CONTROL. */
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/* Mode register (0x11)*/
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#define JMASK_CRCPRESET 0x03 /*Bitmask for CRCPreset bits in register JREG_MODE. */
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/* TxMode register (0x12, 0x13)*/
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#define JMASK_SPEED 0x70 /*Bitmask for Tx/RxSpeed bits in register JREG_TXMODE and JREG_RXMODE. */
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#define JMASK_FRAMING 0x03 /*Bitmask for Tx/RxFraming bits in register JREG_TXMODE and JREG_RXMODE. */
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/* TxSel register (0x16)*/
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#define JMASK_LOADMODSEL 0xC0 /*Bitmask for LoadModSel bits in register JREG_TXSEL. */
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#define JMASK_DRIVERSEL 0x30 /*Bitmask for DriverSel bits in register JREG_TXSEL. */
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#define JMASK_SIGOUTSEL 0x0F /*Bitmask for SigoutSel bits in register JREG_TXSEL. */
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/* RxSel register (0x17)*/
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#define JMASK_UARTSEL 0xC0 /*Bitmask for UartSel bits in register JREG_RXSEL. */
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#define JMASK_RXWAIT 0x3F /*Bitmask for RxWait bits in register JREG_RXSEL. */
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/* RxThreshold register (0x18)*/
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#define JMASK_MINLEVEL 0xF0 /*Bitmask for MinLevel bits in register JREG_RXTHRESHOLD. */
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#define JMASK_COLLEVEL 0x07 /*Bitmask for CollLevel bits in register JREG_RXTHRESHOLD. */
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/* Demod register (0x19)*/
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#define JMASK_ADDIQ 0xC0 /*Bitmask for ADDIQ bits in register JREG_DEMOD. */
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#define JMASK_TAURCV 0x0C /*Bitmask for TauRcv bits in register JREG_DEMOD. */
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#define JMASK_TAUSYNC 0x03 /*Bitmask for TauSync bits in register JREG_DEMOD. */
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/* FeliCa / FeliCa2 register (0x1A, 0x1B)*/
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#define JMASK_FELICASYNCLEN 0xC0 /*Bitmask for FeliCaSyncLen bits in registers JREG_FELICANFC. */
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#define JMASK_FELICALEN 0x3F /*Bitmask for FeliCaLenMin and FeliCaLenMax in
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registers JREG_FELICANFC and JREG_FELICANFC2. */
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/* Mifare register (0x1C)*/
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#define JMASK_SENSMILLER 0xE0 /*Bitmask for SensMiller bits in register JREG_MIFARE. */
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#define JMASK_TAUMILLER 0x18 /*Bitmask for TauMiller bits in register JREG_MIFARE. */
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#define JMASK_TXWAIT 0x03 /*Bitmask for TxWait bits in register JREG_MIFARE. */
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/* Manual Rcv register (0x1D)*/
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#define JMASK_HPCF 0x03 /*Bitmask for HPCF filter adjustments. */
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/* TxBitPhase register (0x25)*/
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#define JMASK_TXBITPHASE 0x7F /*Bitmask for TxBitPhase bits in register JREG_TXBITPHASE. */
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/* RFCfg register (0x26)*/
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#define JMASK_RXGAIN 0x70 /*Bitmask for RxGain bits in register JREG_RFCFG. */
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#define JMASK_RFLEVEL 0x0F /*Bitmask for RfLevel bits in register JREG_RFCFG. */
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/* GsN register (0x27)*/
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#define JMASK_CWGSN 0xF0 /*Bitmask for CWGsN bits in register JREG_GSN. */
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#define JMASK_MODGSN 0x0F /*Bitmask for ModGsN bits in register JREG_GSN. */
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/* CWGsP register (0x28)*/
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#define JMASK_CWGSP 0x3F /*Bitmask for CWGsP bits in register JREG_CWGSP. */
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/* ModGsP register (0x29)*/
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#define JMASK_MODGSP 0x3F /*Bitmask for ModGsP bits in register JREG_MODGSP. */
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/* TMode register (0x2A)*/
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#define JMASK_TGATED 0x60 /*Bitmask for TGated bits in register JREG_TMODE. */
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#define JMASK_TPRESCALER_HI 0x0F /*Bitmask for TPrescalerHi bits in register JREG_TMODE. */
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#define JREG_LpcdQuad_H 0x1E
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#define JREG_LpcdQuad_M 0x1F
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#define JREG_LpcdQuad_L 0x20
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#define JREG_LPCDTEST 0x21
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//============================================================================
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#define JREG_EXT_REG_ENTRANCE 0x0F //ext register entrance
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//============================================================================
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#define JBIT_EXT_REG_WR_ADDR 0X40 //wrire address cycle
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#define JBIT_EXT_REG_RD_ADDR 0X80 //read address cycle
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#define JBIT_EXT_REG_WR_DATA 0XC0 //write data cycle
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#define JBIT_EXT_REG_RD_DATA 0X00 //read data cycle
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//============================================================================
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#define JREG_LPCDDELTA_HI 0x26
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//============================================================================
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//============================================================================
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#define JREG_LPCDDELTA_LO 0x27
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//============================================================================
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//============================================================================
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#define JREG_LPCDICURR_HI 0x28
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//============================================================================
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//============================================================================
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#define JREG_LPCDICURR_LO 0x29
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//============================================================================
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//============================================================================
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#define JREG_LPCDQCURR_HI 0x2A
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//============================================================================
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//============================================================================
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#define JREG_LPCDQCURR_LO 0x2B
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//============================================================================
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//============================================================================
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#define JREG_LPCDILAST_HI 0x2C
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//============================================================================
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//============================================================================
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#define JREG_LPCDILAST_LO 0x2D
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//============================================================================
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//============================================================================
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#define JREG_LPCDQLAST_HI 0x2E
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//============================================================================
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//============================================================================
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#define JREG_LPCDQLAST_LO 0x2F
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//============================================================================
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//============================================================================
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#define JREG_LPCDAUX 0x30
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//============================================================================
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#define IBN2U 0x00
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#define TEST_BG 0x01
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#define TEST_SAMPLE_I 0x02
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#define TEST_AMP_OUT_IN 0x03
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#define TEST_AMP_OUT_IP 0x04
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#define TEST_AMP_OUT_QN 0x05
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#define TEST_AMP_OUT_QP 0x06
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#define OSC_64K 0x07
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#define VBN2 0x08
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#define VBN1 0x09
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#define TEST_BG_VREF 0x0A
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#define AVSS 0x0B
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#define TEST_SAMPLE_Q 0x0C
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#define DVDD 0x0D
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#define TEST_CRYSTAL_VDD 0x0E
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#define AVDD 0x0F
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#define FLOAT_IN 0x10
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//============================================================================
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#define JREG_LPCDSLEEPTIMER 0x33
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//============================================================================
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//============================================================================
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#define JREG_LPCDTHRESH_H 0x34
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//============================================================================
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//============================================================================
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#define JREG_LPCDTHRESH_L 0x35
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//============================================================================
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//============================================================================
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#define JREG_LPCDREQATIMER 0x37
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//============================================================================
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#define LPCD_REQA_TIME_80us 0x00
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#define LPCD_REQA_TIME_100us 0x01
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#define LPCD_REQA_TIME_120us 0x02
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#define LPCD_REQA_TIME_150us 0x03
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#define LPCD_REQA_TIME_200us 0x04
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#define LPCD_REQA_TIME_250us 0x05
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#define LPCD_REQA_TIME_300us 0x06
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#define LPCD_REQA_TIME_400us 0x07
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#define LPCD_REQA_TIME_500us 0x08
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#define LPCD_REQA_TIME_600us 0x09
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#define LPCD_REQA_TIME_800us 0x0A
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#define LPCD_REQA_TIME_1ms 0x0B
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#define LPCD_REQA_TIME_1ms2 0x0C
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#define LPCD_REQA_TIME_1ms6 0x0D
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#define LPCD_REQA_TIME_2ms 0x0E
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#define LPCD_REQA_TIME_2ms5 0x0F
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#define LPCD_REQA_TIME_3ms 0x10
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#define LPCD_REQA_TIME_3ms5 0x11
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#define LPCD_REQA_TIME_4ms 0x12
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#define LPCD_REQA_TIME_5ms 0x13
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#define LPCD_REQA_TIME_7ms 0x14
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//============================================================================
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#define JREG_LPCDREQAANA 0x38
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//============================================================================
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#define LPCD_RXGAIN_23DB 0x00
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#define LPCD_RXGAIN_33DB 0x10 //default
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#define LPCD_RXGAIN_38DB 0x20
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#define LPCD_RXGAIN_43DB 0x30
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#define LPCD_MINLEVEL_3 0x00
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#define LPCD_MINLEVEL_6 0x04
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#define LPCD_MINLEVEL_9 0x08
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#define LPCD_MINLEVEL_C 0x0C
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#define LPCD_MODWIDTH_32 0x00
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#define LPCD_MODWIDTH_38 0x02
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//============================================================================
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#define JREG_LPCDDETECTMODE 0x39
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//============================================================================
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#define LPCD_TXSCALE_0 0x00 //1/8 of the TX power configured by CWGSP/CWGSNON
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#define LPCD_TXSCALE_1 0x08 //1/4 of the TX power configured by CWGSP/CWGSNON
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#define LPCD_TXSCALE_2 0x10 //1/2 of the TX power configured by CWGSP/CWGSNON
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#define LPCD_TXSCALE_3 0x18 //3/4 of the TX power configured by CWGSP/CWGSNON
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#define LPCD_TXSCALE_4 0x20 //equal to of the TX power configured by CWGSP/CWGSNON
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#define LPCD_TXSCALE_5 0x28 //twice of the TX power configured by CWGSP/CWGSNON
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#define LPCD_TXSCALE_6 0x30 //3 times of the TX power configured by CWGSP/CWGSNON
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#define LPCD_TXSCALE_7 0x38 //4 times of the TX power configured by CWGSP/CWGSNON
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#define LPCD_RX_CHANGE_MODE 0x00
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#define LPCD_REQA_MODE 0x01
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#define LPCD_COMBINE_MODE 0x02
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//============================================================================
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#define JREG_LPCDCTRLMODE 0x3A
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//============================================================================
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#define RF_DET_ENABLE 0x20
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#define RF_DET_DISABLE 0x00
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#define RF_DET_SEN_00 0x00 //������
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#define RF_DET_SEN_01 0x08
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#define RF_DET_SEN_10 0x10
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#define RF_DET_SEN_11 0x18 //������
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#define LPCD_DISABLE 0x00
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#define LPCD_ENABLE 0x02 //FM17622
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//============================================================================
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#define JREG_LPCDIRQ 0x3B
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//============================================================================
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//============================================================================
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#define JREG_LPCDRFTIMER 0x3C
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//============================================================================
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#define LPCD_IRQINV_ENABLE 0x20
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#define LPCD_IRQINV_DISABLE 0x00
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#define LPCD_IRQ_PUSHPULL 0x10
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#define LPCD_IRQ_OD 0x00
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#define LPCD_RFTIME_5us 0x00
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#define LPCD_RFTIME_10us 0x01
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#define LPCD_RFTIME_15us 0x02
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#define LPCD_RFTIME_20us 0x03
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#define LPCD_RFTIME_25us 0x04 //default
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#define LPCD_RFTIME_30us 0x05
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#define LPCD_RFTIME_35us 0x06
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#define LPCD_RFTIME_40us 0x07
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#define LPCD_RFTIME_50us 0x08
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#define LPCD_RFTIME_60us 0x09
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#define LPCD_RFTIME_70us 0x0A
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#define LPCD_RFTIME_80us 0x0B
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#define LPCD_RFTIME_100us 0x0C
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#define LPCD_RFTIME_120us 0x0D
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#define LPCD_RFTIME_150us 0x0E
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#define LPCD_RFTIME_200us 0x0F
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//============================================================================
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#define JREG_LPCDTXCTRL1 0x3D
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//============================================================================
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#define LPCD_TX2_ENABLE 0x20
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#define LPCD_TX2_DISABLE 0x00
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#define LPCD_TX1_ENABLE 0x10
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#define LPCD_TX1_DISABLE 0x00
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#define LPCD_TX2ON_INV_ENABLE 0x08
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#define LPCD_TX2ON_INV_DISABLE 0x00
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#define LPCD_TX1ON_INV_ENABLE 0x04
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#define LPCD_TX1ON_INV_DISABLE 0x00
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#define LPCD_TX2OFF_INV_ENABLE 0x02
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#define LPCD_TX2OFF_INV_DISABLE 0x00
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#define LPCD_TX1OFF_INV_ENABLE 0x01
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#define LPCD_TX1OFF_INV_DISABLE 0x00
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//============================================================================
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#define JREG_LPCDTXCTRL2 0x3E
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//============================================================================
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//============================================================================
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#define JREG_LPCDTXCTRL3 0x3F
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//============================================================================
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#endif
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