558 lines
17 KiB
ArmAsm
558 lines
17 KiB
ArmAsm
;==================================================================
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; Copyright ARM Ltd 2006-2014. All rights reserved.
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;
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; Cortex-R5(F) Embedded example - Startup Code
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;==================================================================
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; MPU region defines
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Region_32B EQU 2_00100
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Region_64B EQU 2_00101
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Region_128B EQU 2_00110
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Region_256B EQU 2_00111
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Region_512B EQU 2_01000
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Region_1K EQU 2_01001
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Region_2K EQU 2_01010
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Region_4K EQU 2_01011
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Region_8K EQU 2_01100
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Region_16K EQU 2_01101
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Region_32K EQU 2_01110
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Region_64K EQU 2_01111
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Region_128K EQU 2_10000
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Region_256K EQU 2_10001
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Region_512K EQU 2_10010
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Region_1M EQU 2_10011
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Region_2M EQU 2_10100
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Region_4M EQU 2_10101
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Region_8M EQU 2_10110
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Region_16M EQU 2_10111
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Region_32M EQU 2_11000
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Region_64M EQU 2_11001
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Region_128M EQU 2_11010
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Region_256M EQU 2_11011
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Region_512M EQU 2_11100
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Region_1G EQU 2_11101
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Region_2G EQU 2_11110
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Region_4G EQU 2_11111
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Region_Enable EQU 2_1
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Execute_Never EQU 0x1000 ; Bit 12
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Normal_nShared EQU 0x03 ; Outer and Inner write-back, no write-allocate
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Device_nShared EQU 0x10
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Normal_nShared_nCacheable EQU 0x08 ; normal memory, non-shared, non-cacheable.
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Normal_nShared_Cacheable EQU 0x03 ; normal memory, non-shared, cacheable.
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Normal_Shared_nCacheable EQU 0x0C ; normal memory, shared, non-cacheable.
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Full_Access EQU 2_011
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Read_Only EQU 2_110
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Mode_USR EQU 0x10
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Mode_FIQ EQU 0x11
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Mode_IRQ EQU 0x12
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Mode_SVC EQU 0x13
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Mode_ABT EQU 0x17
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Mode_UND EQU 0x1B
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Mode_SYS EQU 0x1F
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I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
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F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
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UND_Stack_Size EQU 0x00000000
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SVC_Stack_Size EQU 0x00004000 ; Supervisor Mode stack size
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ABT_Stack_Size EQU 0x00000000
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FIQ_Stack_Size EQU 0x00000000
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IRQ_Stack_Size EQU 0x00001000 ; interrupt stack size
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USR_Stack_Size EQU 0x00000000
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Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
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FIQ_Stack_Size + IRQ_Stack_Size)
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MODE_MASK EQU 0x1F ; Processor Mode Mask
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SUP_MODE EQU 0x13 ; Supervisor Mode (SVC)
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IRQ_MODE EQU 0x12 ; Interrupt Mode (IRQ)
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FIQ_MODE EQU 0x11 ; Fast Interrupt Mode (FIQ)
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UND_MODE EQU 0x1B ; Undefined Mode (UND)
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ABT_MODE EQU 0x17 ; Abort Mode (ABT)
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IMPORT ||Load$$INIT$$Base||
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MAGIC_NUMBER EQU 0xBABE5F5F
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IMAGE_LOAD_ADDRESS EQU ImageHeader ;||Load$$INIT$$Base|| ;;0x7E030000 ;0x7E060000
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LOGO_DISPLAY_MAGIC_ADDRESS EQU IMAGE_LOAD_ADDRESS ;magic number to make sure logo.bin is correct in its partition.
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LOGO_DISPLAY_EXEC_ADDRESS EQU IMAGE_LOAD_ADDRESS+4 ;the entry address of logo.bin, so boot33 can call logo.bin from here.
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LOGO_DISPLAY_RET_ADDRESS EQU IMAGE_LOAD_ADDRESS+8 ;reserved
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LOGO_CONTEXT_SIZE EQU 256 ;the context data of boot33 before calling logo.bin
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PRESERVE8
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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StartAddress
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Stack_Mem SPACE Stack_Size
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Stack_Top
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AREA ImageHeader, CODE,READONLY
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;Need to make sure below setting are correct data and placed in designed address after generating logo.bin.
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_logoContextRegs SPACE LOGO_CONTEXT_SIZE ;space to store context registers from boot33
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_logoContextRegsEnd
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_pContextRegs
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DCD _logoContextRegs ;; cpuRegs is the first field.
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;; ENTRY
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EXPORT Reset_Handler
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;-------------------------------------------------------
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MACRO
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$saveCtext SAVECONTEXT
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;; load the backup struct's address
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LDR R0, _pContextRegs ; (R0 is intput, it contains the parameter we don't need so we can use it)
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;; Backup usr CPU registers. (r1-r14)
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STMIA R0, {R1-R14}^ ; Store the registers and increment the pointer.
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ADD R0,R0,#0x38 ; increment the pointer (4*14 registers)
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; (no real need to backup R0)
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;; Backup the CPSR
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MRS R1, CPSR ; Pickup current CPSR.
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STMIA R0!, {R1} ; Store the register and increment the pointer.
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;; Change mode to FIQ
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;MRS R1,CPSR ; Pickup current CPSR
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BIC R1,R1,#MODE_MASK ; Clear the mode bits
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ORR R1,R1,#FIQ_MODE ; Set the new mode bits to the CPSR image
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MSR CPSR_cxsf,R1 ; Setup the new CPSR
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;; Backup fiq CPU registers.
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STMIA R0!, {R8-R14} ; Store the registers and increment the pointer.
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;; Change mode to ABT
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MRS R1,CPSR ; Pickup current CPSR
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BIC R1,R1,#MODE_MASK ; Clear the mode bits
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ORR R1,R1,#ABT_MODE ; Set the new mode bits to the CPSR image
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MSR CPSR_cxsf,R1 ; Setup the new CPSR
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;; Backup abt CPU registers.
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STMIA R0!, {R13,R14} ; Store the registers and increment the pointer.
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;; Change mode to UND
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MRS R1,CPSR ; Pickup current CPSR
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BIC R1,R1,#MODE_MASK ; Clear the mode bits
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ORR R1,R1,#UND_MODE ; Set the new mode bits to the CPSR image
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MSR CPSR_cxsf,R1 ; Setup the new CPSR
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;; Backup und CPU registers.
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STMIA R0!, {R13,R14} ; Store the registers and increment the pointer.
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;; Change mode to IRQ
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MRS R1,CPSR ; Pickup current CPSR
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BIC R1,R1,#MODE_MASK ; Clear the mode bits
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ORR R1,R1,#IRQ_MODE ; Set the new mode bits to the CPSR image
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MSR CPSR_cxsf,R1 ; Setup the new CPSR
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;; Backup irq CPU registers.
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STMIA R0!, {R13,R14} ; Store the registers and increment the pointer.
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;; Change mode to SVC
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MRS R1,CPSR ; Pickup current CPSR
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BIC R1,R1,#MODE_MASK ; Clear the mode bits
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ORR R1,R1,#SUP_MODE ; Set the new mode bits to the CPSR image
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MSR CPSR_cxsf,R1 ; Setup the new CPSR
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;; Backup svc CPU registers.
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STMIA R0!, {R13,R14} ; Store the registers and increment the pointer.
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;BX LR
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MEND
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;----------------------------------------
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MACRO
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$restoreCtext RESTORECONTEXT
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LDR R0, _pContextRegs ; load the backup struct's address
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;; No use in restoring the CPSR and usr registers now.
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ADD R0, R0, #0x3C ; increment R0 by 15*UINT32 (the size of all registers)
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;; Change mode to FIQ
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MRS R1,CPSR ; Pickup current CPSR
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BIC R1,R1,#MODE_MASK ; Clear the mode bits
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ORR R1,R1,#FIQ_MODE ; Set the new mode bits to the CPSR image
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MSR CPSR_cxsf,R1 ; Setup the new CPSR
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;; Restore fiq CPU registers.
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LDMIA R0!, {R8-R14} ; Restore the registers and increment the pointer.
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;; Change mode to ABT
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MRS R1,CPSR ; Pickup current CPSR
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BIC R1,R1,#MODE_MASK ; Clear the mode bits
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ORR R1,R1,#ABT_MODE ; Set the new mode bits to the CPSR image
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MSR CPSR_cxsf,R1 ; Setup the new CPSR
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;; Restore abt CPU registers.
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LDMIA R0!, {R13,R14} ; Restore the registers and increment the pointer.
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;; Change mode to UND
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MRS R1,CPSR ; Pickup current CPSR
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BIC R1,R1,#MODE_MASK ; Clear the mode bits
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ORR R1,R1,#UND_MODE ; Set the new mode bits to the CPSR image
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MSR CPSR_cxsf,R1 ; Setup the new CPSR
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;; Restore und CPU registers.
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LDMIA R0!, {R13,R14} ; Restore the registers and increment the pointer.
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;; Change mode to IRQ
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MRS R1,CPSR ; Pickup current CPSR
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BIC R1,R1,#MODE_MASK ; Clear the mode bits
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ORR R1,R1,#IRQ_MODE ; Set the new mode bits to the CPSR image
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MSR CPSR_cxsf,R1 ; Setup the new CPSR
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;; Restore irq CPU registers.
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LDMIA R0!, {R13,R14} ; Restore the registers and increment the pointer.
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;; Change mode to SVC
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MRS R1,CPSR ; Pickup current CPSR
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BIC R1,R1,#MODE_MASK ; Clear the mode bits
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ORR R1,R1,#SUP_MODE ; Set the new mode bits to the CPSR image
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MSR CPSR_cxsf,R1 ; Setup the new CPSR
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;; Restore svc CPU registers.
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LDMIA R0!, {R13,R14} ; Restore the registers and increment the pointer.
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;; Restore usr CPU registers.
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LDR R0, _pContextRegs ; Reload the struct's address.
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LDMIA R0, {R1-R14}^ ; Restore the registers and increment the pointer.
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ADD R0,R0,#0x38 ; increment the pointer (4*14 registers)
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;; Restore the CPSR
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LDMIA R0, {R0} ; Restore to the register.
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MSR CPSR_cxsf,R0 ; Recover the CPSR itself.
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MEND
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ENTRY
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Reset_Handler
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;Firstly, to store context of boot33 before they are destroyed,
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;r0 and r1 is not protected, so set them as input parameters.
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saveContext SAVECONTEXT ;r0 and r1 are input parameters before calling context.
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; normal vector address selected
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MRC p15, 0, r1, c1, c0, 0
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BIC r1, r1, #0x2000
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MCR p15, 0, r1, c1, c0, 0
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;==================================================================
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; Disable MPU and caches
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;==================================================================
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; Disable MPU and cache in case it was left enabled from an earlier run
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; This does not need to be done from a cold reset
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MRC p15, 0, r0, c1, c0, 0 ; Read CP15 Control Register
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BIC r0, r0, #0x05 ; Disable MPU (M bit) and data cache (C bit)
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BIC r0, r0, #0x1000 ; Disable instruction cache (I bit)
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DSB ; Ensure all previous loads/stores have completed
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MCR p15, 0, r0, c1, c0, 0 ; Write CP15 Control Register
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ISB ; Ensure subsequent insts execute wrt new MPU settings
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;==================================================================
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; Disable Branch prediction
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;==================================================================
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; In the Cortex-R5, the Z-bit of the SCTLR does not control the program flow prediction.
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; Some control bits in the ACTLR control the program flow and prefetch features instead.
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; These are enabled by default, but are shown here for completeness.
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MRC p15, 0, r0, c1, c0, 1 ; Read ACTLR
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ORR r0, r0, #(0x1 << 17) ; Enable RSDIS bit 17 to disable the return stack
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ORR r0, r0, #(0x1 << 16) ; Clear BP bit 15 and set BP bit 16:
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BIC r0, r0, #(0x1 << 15) ; Branch always not taken and history table updates disabled
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MCR p15, 0, r0, c1, c0, 1 ; Write ACTLR
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; Setup Stack for each mode
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LDR R0, =Stack_Top
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; Enter Undefined Instruction Mode and set its Stack Pointer
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MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
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MOV SP, R0
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SUB R0, R0, #UND_Stack_Size
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; Enter Abort Mode and set its Stack Pointer
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MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
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MOV SP, R0
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SUB R0, R0, #ABT_Stack_Size
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; Enter FIQ Mode and set its Stack Pointer
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MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
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MOV SP, R0
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SUB R0, R0, #FIQ_Stack_Size
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; Enter IRQ Mode and set its Stack Pointer
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MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
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MOV SP, R0
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SUB R0, R0, #IRQ_Stack_Size
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; Enter Supervisor Mode and set its Stack Pointer
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MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
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MOV SP, R0
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; Open Interrupt
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MRS r0, cpsr
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BIC r0, r0, #0xc0
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MSR cpsr_c, r0
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;==================================================================
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; Cache invalidation
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;==================================================================
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DSB ; Complete all outstanding explicit memory operations
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MOV r0, #0
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MCR p15, 0, r0, c7, c5, 0 ; Invalidate entire instruction cache
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MCR p15, 0, r0, c15, c5, 0 ; Invalidate entire data cache
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;==================================================================
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; Enable Branch prediction
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;==================================================================
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; In the Cortex-R5, the Z-bit of the SCTLR does not control the program flow prediction.
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; Some control bits in the ACTLR control the program flow and prefetch features instead.
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; These are enabled by default, but are shown here for completeness.
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MRC p15, 0, r0, c1, c0, 1 ; Read ACTLR
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BIC r0, r0, #(0x1 << 17) ; Clear RSDIS bit 17 to enable return stack
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BIC r0, r0, #(0x1 << 16) ; Clear BP bit 15 and BP bit 16:
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BIC r0, r0, #(0x1 << 15) ; Normal operation, BP is taken from the global history table.
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MCR p15, 0, r0, c1, c0, 1 ; Write ACTLR
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;*********************************************************************************
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; Initialize memory required by C code
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;**********************************************************************************
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IMPORT ||Load$$CODE$$Base||
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IMPORT ||Image$$CODE$$Base||
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IMPORT ||Image$$CODE$$Length||
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LDR r0, =||Load$$CODE$$Base||
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LDR r1, =||Image$$CODE$$Base||
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LDR r2, =||Image$$CODE$$Length||
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ADD r2, r2, #3
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MOV r2, r2, LSR #2
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CMP r2, #0
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BEQ copy_itcm
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CopyCODE
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LDR r3, [r0], #4
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STR r3, [r1], #4
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SUBS r2, r2, #1
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BNE CopyCODE
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copy_itcm
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IMPORT ||Load$$ITCM$$Base||
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IMPORT ||Image$$ITCM$$Base||
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IMPORT ||Image$$ITCM$$Length||
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LDR r0, =||Load$$ITCM$$Base||
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LDR r1, =||Image$$ITCM$$Base||
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LDR r2, =||Image$$ITCM$$Length||
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ADD r2, r2, #3
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MOV r2, r2, LSR #2
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CMP r2, #0
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BEQ copy_rw
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COPYITCM
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LDR r3, [r0], #4
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STR r3, [r1], #4
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SUBS r2, r2, #1
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BNE COPYITCM
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copy_rw
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IMPORT ||Load$$DATA$$RW$$Base||
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IMPORT ||Image$$DATA$$RW$$Base||
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IMPORT ||Image$$DATA$$RW$$Length||
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LDR r0, =||Load$$DATA$$RW$$Base||
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LDR r1, =||Image$$DATA$$RW$$Base||
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LDR r2, =||Image$$DATA$$RW$$Length||
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; copy rw data from back to front
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ADD r0, r2
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SUBS r0, r0, #4
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ADD r1, r2
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SUBS r1, r1, #4
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ADD r2, r2, #3
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MOV r2, r2, LSR #2
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CMP r2, #0
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BEQ copy_zi
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CopyRW
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LDR r3, [r0], #-4
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STR r3, [r1], #-4
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SUBS r2, r2, #1
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BNE CopyRW
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copy_zi
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IMPORT ||Image$$DATA$$ZI$$Base||
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IMPORT ||Image$$DATA$$ZI$$Length||
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LDR r1, =||Image$$DATA$$ZI$$Base||
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LDR r2, =||Image$$DATA$$ZI$$Length||
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ADD r2, r2, #3
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MOV r2, r2, LSR #2
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CMP r2, #0
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BEQ copy_end
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MOV r0, #0
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CopyZI
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STR r0, [r1], #4
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SUBS r2, r2, #1
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BNE CopyZI
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copy_end
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IMPORT logo
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IMPORT printlog
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BL logo ;to show logo and execute PrepareToExecuteCp
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;BL printlog
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;To restore the context of boot33 before back to run boot33 code.
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;SHOULD NOT destroy registers any more before exit to boot33.
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restoreContext RESTORECONTEXT
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NOP
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BX lr ;return to boot33
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LOOPFOREVER B LOOPFOREVER ; forever loop
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EXPORT getLR_reg
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EXPORT getSP_reg
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getLR_reg
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mov r0, lr
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bx lr
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getSP_reg
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mov r0, SP
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bx lr
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;************************************************************
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; DisableIrqInterrupts
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;************************************************************
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DisableIrqInterrupts
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STMFD SP!, {R0-R4, LR}
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MRS r0,CPSR ; get the processor status
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ORR r0,r0,#0x80 ; Disable IRQ interrupts
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MSR cpsr_cf,r0 ; SVC 32 mode with interrupts disabled
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LDMFD SP!, {R0-R4, PC}
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;***********************************************************************************
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; r0 = Boot Image Load Address
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;***********************************************************************************
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EXPORT TransferControl
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TransferControl
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mov pc, r0
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transfer_control
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DCD 0xF57FF04F ;DSB
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DCD 0xF57FF06F ;ISB
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DCD 0xF8900A00 ;RFEIA r0
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EXPORT sctlr_get
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sctlr_get
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mrc p15, 0, r0, c1, c0, 0
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bx lr
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EXPORT sctlr_set
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sctlr_set
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mcr p15, 0, r0, c1, c0, 0
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DCD 0xF57FF06F ;ISB
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bx lr
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EXPORT mpu_get_region_num
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mpu_get_region_num
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mrc p15, 0, r0, c6, c2, 0
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bx lr
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EXPORT mpu_set_region_num
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mpu_set_region_num
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mcr p15, 0, r0, c6, c2, 0
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DCD 0xF57FF06F ;ISB
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bx lr
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EXPORT mpu_get_region_base_addr
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mpu_get_region_base_addr
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mrc p15, 0, r0, c6, c1, 0
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bx lr
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EXPORT mpu_set_region_base_addr
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mpu_set_region_base_addr
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mcr p15, 0, r0, c6, c1, 0
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DCD 0xF57FF06F ;ISB
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bx lr
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EXPORT mpu_get_region_size
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mpu_get_region_size
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mrc p15, 0, r0, c6, c1, 2
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and r0, r0, #0x3E
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mov r0, r0, lsr #1
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bx lr
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EXPORT mpu_set_region_size
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mpu_set_region_size
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STMFD SP!, {R0-R4, LR}
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mov r1, r0
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mrc p15, 0, r0, c6, c1, 2
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bic r0, r0, #0x3E
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mov r1, r1, LSL #1
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orr r0, r0, r1
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mcr p15, 0, r0, c6, c1, 2
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DCD 0xF57FF06F ;ISB
|
|
LDMFD SP!, {R0-R4, PC}
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EXPORT mpu_get_region_size_enable
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mpu_get_region_size_enable
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mrc p15, 0, r0, c6, c1, 2
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bx lr
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EXPORT mpu_get_region_access_ctrl
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mpu_get_region_access_ctrl
|
|
mrc p15, 0, r0, c6, c1, 4
|
|
bx lr
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|
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EXPORT mpu_set_region_access_ctrl
|
|
mpu_set_region_access_ctrl
|
|
mcr p15, 0, r0, c6, c1, 4
|
|
DCD 0xF57FF06F ;ISB
|
|
bx lr
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EXPORT mpu_enable_region
|
|
mpu_enable_region
|
|
STMFD SP!, {R0-R4, LR}
|
|
bl mpu_set_region_num
|
|
mrc p15, 0, r0, c6, c1, 2
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orr r0, r0, #0x1 ;set bit 0 to enable
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|
mcr p15, 0, r0, c6, c1, 2
|
|
DCD 0xF57FF06F ;ISB
|
|
LDMFD SP!, {R0-R4, PC}
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|
|
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EXPORT CPUCleanDCacheLine
|
|
CPUCleanDCacheLine
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|
DSB ;ensure ordering with previous memory access
|
|
MCR p15, 0, R0, c7, c10, 1
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DSB ;ensure ordering with previous memory access
|
|
BX LR
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|
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EXPORT CPUInvalidateDCacheLine
|
|
CPUInvalidateDCacheLine
|
|
DSB ;ensure ordering with previous memory access
|
|
MCR p15, 0, R0, c7, c6, 1 ;invalidate L1 Cache
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|
DSB ;ensure ordering with previous memory access
|
|
BX LR
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;-------------------------------------------------------
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END
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