81 lines
4.3 KiB
C
81 lines
4.3 KiB
C
/*
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* Copyright (C) 2016 ASR MICROELECTRONICS Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*************************************************
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* Automatically generated C header: do not edit *
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*************************************************
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*/
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#define APBC_PWM0_CLK_RST (0xd401500C)
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enum{
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PWM_13M = 0,
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PWM_32K,
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PWM_CLK_LIMIT
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};
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#define REGS_PWM0_BASE (0xd401a000)
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#define REGS_PWM1_BASE (0xd401a400)
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#define REGS_PWM2_BASE (0xd401a800)
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#define REGS_PWM3_BASE (0xd401ac00)
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#ifndef __H_REGS_PWM0PWM1PWM2PWM3_HEADFILE_H__
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#define __H_REGS_PWM0PWM1PWM2PWM3_HEADFILE_H__ __FILE__
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#define REGS_PWM0
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#define ASR_ADDR(_BASE_, _OFFSET_) (unsigned int)((_BASE_) + (_OFFSET_))
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/* registers definitions for PWM0PWM1PWM2PWM3 */
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#define REG_PWM0_PWM_CRx ASR_ADDR(REGS_PWM0_BASE, 0X00)/*PWM Control Registers*/
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#define REG_PWM1_PWM_CRx ASR_ADDR(REGS_PWM1_BASE, 0X00)/*PWM Control Registers*/
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#define REG_PWM2_PWM_CRx ASR_ADDR(REGS_PWM2_BASE, 0X00)/*PWM Control Registers*/
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#define REG_PWM3_PWM_CRx ASR_ADDR(REGS_PWM3_BASE, 0X00)/*PWM Control Registers*/
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#define REG_PWM0_PWM_DCR ASR_ADDR(REGS_PWM0_BASE, 0X04)/*PWM Duty Cycle Registers*/
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#define REG_PWM1_PWM_DCR ASR_ADDR(REGS_PWM1_BASE, 0X04)/*PWM Duty Cycle Registers*/
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#define REG_PWM2_PWM_DCR ASR_ADDR(REGS_PWM2_BASE, 0X04)/*PWM Duty Cycle Registers*/
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#define REG_PWM3_PWM_DCR ASR_ADDR(REGS_PWM3_BASE, 0X04)/*PWM Duty Cycle Registers*/
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#define REG_PWM0_PWM_PCR ASR_ADDR(REGS_PWM0_BASE, 0X08)/*PWM Period Control Registers*/
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#define REG_PWM1_PWM_PCR ASR_ADDR(REGS_PWM1_BASE, 0X08)/*PWM Period Control Registers*/
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#define REG_PWM2_PWM_PCR ASR_ADDR(REGS_PWM2_BASE, 0X08)/*PWM Period Control Registers*/
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#define REG_PWM3_PWM_PCR ASR_ADDR(REGS_PWM3_BASE, 0X08)/*PWM Period Control Registers*/
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/* bits definitions for register REG_PWM3_PWM_CRx */
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#define BIT_SD ( BIT(6) )
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#define BITS_PWM0_PRESCALE25(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
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/* bits definitions for register REG_PWM3_PWM_DCR */
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#define BIT_FD ( BIT(10) )
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#define BITS_DCYCLE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
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/* bits definitions for register REG_PWM3_PWM_PCR */
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#define BITS_PV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
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/* added by schan 2021-01-28 */
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#define write64(addr, val) (*(volatile unsigned long long *)(addr) = (val))
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#define read64(addr) (*(volatile unsigned long long *)(addr))
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#define write32(addr, val) (*(volatile unsigned int *)(addr) = (val))
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#define read32(addr) (*(volatile unsigned int *)(addr))
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#define write16(addr, val) (*(volatile uint16 *)(addr) = (val))
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#define read16(addr) (*(volatile uint16 *)(addr))
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#define ARR_SIZE( _a ) ( sizeof( (_a) ) / sizeof( (_a[0]) ) )
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#define CHIP_REG_OR(reg_addr, value) (*(volatile uint32_t *)(reg_addr) |= (uint32_t)(value))
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#define CHIP_REG_AND(reg_addr, value) (*(volatile uint32_t *)(reg_addr) &= (uint32_t)(value))
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#define CHIP_REG_GET(reg_addr) (*(volatile uint32_t *)(reg_addr))
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#define CHIP_REG_SET(reg_addr, value) (*(volatile uint32_t *)(reg_addr) = (uint32_t)(value))
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#endif
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