396 lines
9.0 KiB
C
396 lines
9.0 KiB
C
#include "common.h"
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#include "bsp.h"
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#include "guilin_lite.h"
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/****************************************************************
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* console output
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****************************************************************/
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#define CP_UART2_BASE 0xd4018000
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#define CP_UART_BASE 0xd4017000
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#ifdef QUECTEL_FOTA
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#include "lfs.h"
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#include "lfs_api.h"
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#define QUEC_CP_BAUDRATE_INI "quec_cp_baudrate.ini"
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#define UART_CLOCK 14745600L /* the UART clock Hz input clock */
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typedef enum /* All the UART Baud Rate that the UART Package supplay */
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{
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UART_BAUD_150 = 150,
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UART_BAUD_300 = 300,
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UART_BAUD_600 = 600,
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UART_BAUD_1200 = 1200,
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UART_BAUD_2400 = 2400,
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UART_BAUD_3600 = 3600,
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UART_BAUD_4800 = 4800,
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UART_BAUD_7200 = 7200,
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UART_BAUD_9600 = 9600,
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UART_BAUD_14400 = 14400,
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UART_BAUD_19200 = 19200,
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UART_BAUD_28800 = 28800,
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UART_BAUD_38400 = 38400,
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UART_BAUD_57600 = 57600,
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UART_BAUD_115200 = 115200,
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UART_BAUD_230400 = 230400,
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UART_BAUD_460800 = 460800,
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UART_BAUD_921600 = 921600,
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UART_BAUD_1000000 = 1000000,
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UART_BAUD_1842000 = 1842000,
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UART_BAUD_3686400 = 3686400,
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UART_MAX_NUM_BAUD
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}UART_BaudRates;
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UART_BaudRates quec_get_cp_baudrate()
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{
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UART_BaudRates tmp_baudrate = UART_BAUD_115200;
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int filehandle = 0;
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int read_size = -1;
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filehandle = lfs_io_open(QUEC_CP_BAUDRATE_INI,LFS_O_RDONLY,0);
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if(filehandle < 0)
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{
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uart_printf("function:%s,quec_cp_baudrate.ini open fail.\r\n",__func__);
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tmp_baudrate = UART_BAUD_115200;
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return tmp_baudrate;
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}
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read_size = lfs_io_read(filehandle,(void*)&tmp_baudrate,sizeof(tmp_baudrate));
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if(sizeof(tmp_baudrate) != read_size )
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{
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uart_printf("update file read error: %d\r\n",read_size);
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tmp_baudrate = UART_BAUD_115200;
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lfs_io_close(filehandle);
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return tmp_baudrate;
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}
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uart_printf("quec_cp_baudrate.ini read success baudrate = %d\r\n",tmp_baudrate);
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lfs_io_close(filehandle);
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return tmp_baudrate;
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}
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#endif
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void cp_uart_init()
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{
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volatile unsigned long temp, *r;
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/* PMUM_ACGR */
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writel(0xffffffff,0xd4050024);
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writel(0x03,0xd401503c); //AIB
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/* UART clock control/UCER */
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writel(0x13,0xd4015000);
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if (CHIP_IS_CRANELR || CHIP_IS_CRANELG || CHIP_IS_CRANELRH)
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{
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/* MFPR GPIO 71 */
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r = (volatile unsigned long*)0xd401e1bc; //AP_UART1_RXD
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*r = 0xd0c1;
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/* MFPR GPIO 72 */
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r = (volatile unsigned long*)0xd401e1c0; //AP_UART1_TXD
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*r = 0xd0c1;
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}
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else if (CHIP_IS_CRANELS_A0)
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{
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/* MFPR GPIO 27 */
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r = (volatile unsigned long*)0xd401e148; //AP_UART1_RXD
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*r = 0xd0c1;
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/* MFPR GPIO 28 */
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r = (volatile unsigned long*)0xd401e14C; //AP_UART1_TXD
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*r = 0xd0c1;
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}
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else
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{
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/* MFPR GPIO 29 */
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r = (volatile unsigned long*)0xd401e150; //UART1_RXD
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*r = 0xd0c1;
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/* MFPR GPIO 30 */
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r = (volatile unsigned long*)0xd401e154; //UART1_TXD
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*r = 0xd0c1;
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}
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// UALCR
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r = (volatile unsigned long*)(CP_UART_BASE + 0xc);
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*r = 0x83;
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// UADLL
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r = (volatile unsigned long*)(CP_UART_BASE + 0x0);
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*r = 0x08; //0x08 for 14.7456M on DKB, 0x7 for 13M on FPGA;
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temp = *r;
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// UADLH
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r = (volatile unsigned long*)(CP_UART_BASE + 0x4);
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*r = 0;
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// UALCR
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r = (volatile unsigned long*)(CP_UART_BASE + 0xC);
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*r &= ~0x80;
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// UAFCR
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r = (volatile unsigned long*)(CP_UART_BASE + 0x8);
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*r = 0x07;
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// UAIER
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r = (volatile unsigned long*)(CP_UART_BASE + 0x4);
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*r = 0x40;
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}
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void cp_uart_putc(const char ch)
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{
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volatile unsigned long* ualsr;
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volatile unsigned long* uathr;
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ualsr = (volatile unsigned long*)(CP_UART_BASE + 0x14);
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uathr = (volatile unsigned long*)(CP_UART_BASE);
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while (!(*ualsr & 0x20));
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*uathr = ch;
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}
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int uart_printf(const char *fmt, ...)
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{
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#if !defined (ENABLE_SLT_FEATURE)
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va_list ap;
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char buffer[128], *ptr;
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void (*console_output)(const char ch);
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memset(buffer, 0, sizeof(buffer));
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va_start(ap, fmt);
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vsnprintf(buffer, sizeof(buffer), fmt, ap);
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va_end(ap);
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console_output = cp_uart_putc;
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ptr = &buffer[0];
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while (*ptr)
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{
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console_output(*ptr);
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ptr ++;
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}
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return ptr - buffer;
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#else
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return 0;
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#endif
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}
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void display_binary(void *data, size_t len)
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{
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#define XK_BYTE_COUNT_EACH_LINE 8
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static const char hex[] = "0123456789ABCDEF";
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static const char seperator = ' ';
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unsigned char *p = (unsigned char *)data;
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char stash[XK_BYTE_COUNT_EACH_LINE * (2 + 2 + 1) + 1];
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size_t j = 0;
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size_t i;
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uart_printf("\r\n----------------------------\r\n");
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uart_printf("BASE=[%0.8x]LEN=[%0.8x]",data,len);
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for (i = 0; i < len; i=i+2) {
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//stash[j++] = '0';
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//stash[j++] = 'x';
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stash[j++] = hex[(p[i] >> 4) & 0xF];
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stash[j++] = hex[p[i] & 0xF];
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stash[j++] = hex[(p[i+1] >> 4) & 0xF];
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stash[j++] = hex[p[i+1] & 0xF];
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stash[j++] = seperator;
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if (j == sizeof(stash) - 1) {
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stash[j] = '\0';
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uart_printf("\r\n[%0.8x]%s",((unsigned int)data + i - 0xe), stash);
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j = 0;
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}
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}
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if (j) {
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stash[j] = '\0';
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uart_printf("\r\n[%0.8x]%s",((unsigned int)data + i - 0xe + XK_BYTE_COUNT_EACH_LINE), stash);
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}
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uart_printf("\r\n----------------------------\r\n");
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}
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#define AIB_UART_IO_REG 0xD401E81C
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extern int GuilinLite_LDO_Set_VOUT(unsigned char reg, unsigned char value);
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void _AIB_Secure_Write(unsigned int address, unsigned int value)
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{
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BU_REG_WRITE(0xd4015050, 0xBABA);
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BU_REG_WRITE(0xd4015054, 0xEB10);
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BU_REG_WRITE(address, value);
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}
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UINT32 _AIB_Secure_Read(unsigned int address)
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{
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UINT32 val;
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BU_REG_WRITE(0xd4015050, 0xBABA);
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BU_REG_WRITE(0xd4015054, 0xEB10);
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val = BU_REG_READ(address);
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return val;
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}
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void AIB_UART_IO_Set_1_8V(void)
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{
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volatile unsigned int val = 0;
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val = _AIB_Secure_Read(AIB_UART_IO_REG); //AIB_UART_IO_REG
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val |= 0x85;
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_AIB_Secure_Write(AIB_UART_IO_REG, val);
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}
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void PMIC_Set_UART_1_8V(void)
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{
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if(PMIC_IS_PM803())
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{
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GuilinLite_LDO_Set_VOUT(GUILIN_LITE_LDO7_ACTIVE_VOUT_REG, GUILIN_LITE_LDO7_ACTIVE_1V80);
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}
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AIB_UART_IO_Set_1_8V();
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}
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void PMIC_Set_UART_Poweron(void)
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{
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if(PMIC_IS_PM803())
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{
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GuilinLite_Ldo_7_set(TRUE);
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}
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}
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void cp_uart2_init()
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{
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volatile unsigned long temp, *r;
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if (IsChipCraneL() || IsChipCraneL_Z1() || IsChipCraneLS()) {
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PMIC_Set_UART_1_8V();
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PMIC_Set_UART_Poweron();
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}
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#ifdef QUECTEL_FOTA
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UART_BaudRates baudrate = UART_BAUD_115200;
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UINT32 divisor;
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UINT8 DLHval, DLLval;
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//baudrate = quec_get_cp_baudrate();
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#endif
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#if 0
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/* PMUM_ACGR */
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writel(0xdffefffe,0xd4051024); //0x2DFFFF; //0xdffefffe;
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writel(0x03,0xd401503c); //AIB
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/* UART clock control/UCER */
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writel(0x3,0xd403b01c);
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/* MFPR GPIO 120 */
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r = (volatile unsigned long*)0xd401e384;
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*r = 0xd0c2;
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/* MFPR GPIO 121 */
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r = (volatile unsigned long*)0xd401e388;
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*r = 0xd0c2;
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#else
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/* PMUM_ACGR */
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writel(0xfffffffe,0xd4050024);
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writel(0x03,0xd401503c); //AIB
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/* UART clock control/UCER */
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writel(0x13,0xd4015004);
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/* MFPR GPIO 51 */
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r = (volatile unsigned long*)0xd401e1a8;
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*r = 0xd0c1;
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/* MFPR GPIO 52 */
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r = (volatile unsigned long*)0xd401e1ac;
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*r = 0xd0c1;
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#endif
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// UALCR
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r = (volatile unsigned long*)(CP_UART2_BASE + 0xc);
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*r = 0x83;
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#ifdef QUECTEL_FOTA
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divisor = (UINT32)(UART_CLOCK / (16L*baudrate));
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DLLval = (UINT8)(divisor & 0xFF);
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DLHval = (UINT8)((divisor & 0xFF00) >> 8);
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// UADLL
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r = (volatile unsigned long*)(CP_UART2_BASE + 0x0);
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*r = DLLval; //0x08 for 14.7456M on DKB, 0x7 for 13M on FPGA;
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// UADLH
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r = (volatile unsigned long*)(CP_UART2_BASE + 0x4);
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*r = DLHval;
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#else
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// UADLL
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r = (volatile unsigned long*)(CP_UART2_BASE + 0x0);
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*r = 0x08; //0x08 for 14.7456M on DKB, 0x7 for 13M on FPGA;
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// UADLH
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r = (volatile unsigned long*)(CP_UART2_BASE + 0x4);
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*r = 0;
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#endif
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temp = *r;
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// UALCR
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r = (volatile unsigned long*)(CP_UART2_BASE + 0xC);
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*r &= ~0x80;
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// UAFCR
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r = (volatile unsigned long*)(CP_UART2_BASE + 0x8);
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*r = 0x07;
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// UAIER
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r = (volatile unsigned long*)(CP_UART2_BASE + 0x4);
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*r = 0x40;
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}
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void cp_uart2_putc(const char ch)
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{
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volatile unsigned long* ualsr;
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volatile unsigned long* uathr;
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ualsr = (volatile unsigned long*)(CP_UART2_BASE + 0x14);
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uathr = (volatile unsigned long*)(CP_UART2_BASE);
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while (!(*ualsr & 0x20));
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*uathr = ch;
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}
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int uart2_printf(const char *fmt, ...)
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{
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va_list ap;
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char buffer[128], *ptr;
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void (*console_output)(const char ch);
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memset(buffer, 0, sizeof(buffer));
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va_start(ap, fmt);
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vsnprintf(buffer, sizeof(buffer), fmt, ap);
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va_end(ap);
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console_output = cp_uart2_putc;
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ptr = &buffer[0];
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while (*ptr)
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{
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console_output(*ptr);
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ptr ++;
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}
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return ptr - buffer;
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}
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