104 lines
3.6 KiB
C
104 lines
3.6 KiB
C
#include "mfp-drv.h"
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#include "mfp.h"
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#include "syscall-arom.h"
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#include "cpu.h"
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/* Pin register definitions */
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/* --------------------------------------------------------------- */
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#define QSPI_DAT3_MPFI (0x2C4)
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#define QSPI_DAT2_MPFI (0x2C8)
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#define QSPI_DAT1_MPFI (0x2CC)
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#define QSPI_DAT0_MPFI (0x2D0)
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#define QSPI_CLK_MPFI (0x2D4)
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#define QSPI_CS1_MPFI (0x2D8)
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#define QSPI_CS2_MPFI (0x2DC)
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#define QSPI_DQM_MPFI (0x2E0)
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/* --------------------------------------------------------------- */
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#define AP_UART1_CRANEGML_RXD 0x150
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#define AP_UART1_CRANELR_RXD 0x1BC
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#define AP_UART1_CRANELS_RXD 0x148
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/* --------------------------------------------------------------- */
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#if AROM_VERSION == AROM_VER_2020_07_30_CRANEGM_A0
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/*
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* eg: MX25U12835F, DAT3 has other function(WP/Hold pin) when spi mode. mx need always pull up dat3 when quad read.
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* bootrom use standard spi mode, so use Dat0 and Dat1.
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* bootrom need pull up Dat2 and Dat3 to disable other function of the pins.
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* bootloader will read device id to judge whether the flash is common, can recover Dat2 and Dat3 to pull down mode(hardware default).
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*/
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static const uint32_t mfp_cfgs_spi[] = {
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MFP_REG(QSPI_DAT3_MPFI) | MFP_DRIVE_MEDIUM | MFP_AF0 | MFP_PULL_HIGH,
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MFP_REG(QSPI_DAT2_MPFI) | MFP_DRIVE_MEDIUM | MFP_AF0 | MFP_PULL_HIGH,
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MFP_EOC
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};
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#endif
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/* --------------------------------------------------------------- */
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/* recover default mode(hardware default is pull down mode) for common flashes */
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static const uint32_t mfp_cfgs_quad_spi[] = {
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MFP_REG(QSPI_DAT3_MPFI) | MFP_DRIVE_MEDIUM | MFP_AF0,
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MFP_REG(QSPI_DAT2_MPFI) | MFP_DRIVE_MEDIUM | MFP_AF0,
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MFP_EOC
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};
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/* --------------------------------------------------------------- */
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static const uint32_t mfp_cfgs_mx[] = {
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MFP_REG(QSPI_DAT3_MPFI) | MFP_DRIVE_MEDIUM | MFP_AF0 | MFP_PULL_HIGH,
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MFP_EOC
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};
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/* --------------------------------------------------------------- */
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/* if AROM_NEXT_DELIVER, mfp_cfgs_spi can be removed.
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* pull up Dat3 and Dat2 for read id always successfully for speacial flash. eg mx
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*/
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void
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spi_mfp_config(void)
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{
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#if AROM_VERSION == AROM_VER_2020_07_30_CRANEGM_A0
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mfp_config((uint32_t *)mfp_cfgs_spi);
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#endif
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}
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/* --------------------------------------------------------------- */
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void
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qspi_mfp_config(void)
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{
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mfp_config((uint32_t *)mfp_cfgs_quad_spi);
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}
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/* --------------------------------------------------------------- */
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void
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qspi_mfp_config_mx(void)
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{
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mfp_config((uint32_t *)mfp_cfgs_mx);
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}
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/* --------------------------------------------------------------- */
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static const uint32_t uart1_mfp_cranelr_cfgs[] = {
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MFP_REG(AP_UART1_CRANELR_RXD) | MFP_DRIVE_MEDIUM | MFP_PULL_NONE | MFP_AF0,
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MFP_EOC
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};
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/* --------------------------------------------------------------- */
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static const uint32_t uart1_mfp_cranels_cfgs[] = {
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MFP_REG(AP_UART1_CRANELS_RXD) | MFP_DRIVE_MEDIUM | MFP_PULL_NONE | MFP_AF0,
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MFP_EOC
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};
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/* --------------------------------------------------------------- */
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static const uint32_t uart1_mfp_cranegml_cfgs[] = {
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MFP_REG(AP_UART1_CRANEGML_RXD) | MFP_DRIVE_MEDIUM | MFP_PULL_NONE | MFP_AF0,
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MFP_EOC
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};
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/* --------------------------------------------------------------- */
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int
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uart_rx_gpio_config(void)
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{
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switch(hw_chip_id()) {
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case CHIP_ID_CRANELR:
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mfp_config((uint32_t *)uart1_mfp_cranelr_cfgs);
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return 1;
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case CHIP_ID_CRANELS:
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mfp_config((uint32_t *)uart1_mfp_cranels_cfgs);
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return 1;
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case CHIP_ID_CRANEG:
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case CHIP_ID_CRANEM:
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case CHIP_ID_CRANEL:
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mfp_config((uint32_t *)uart1_mfp_cranegml_cfgs);
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return 1;
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}
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return 0;
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}
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/* --------------------------------------------------------------- */
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