354 lines
13 KiB
C
354 lines
13 KiB
C
/*------------------------------------------------------------
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(C) Copyright [2006-2008] Marvell International Ltd.
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All Rights Reserved
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------------------------------------------------------------*/
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#ifndef _TIMER_HW_H
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#define _TIMER_HW_H (1)
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/*--------- Local defines ---------------------------------------------------*/
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/* Manitoba VTCXO = 13M ; fast_clk = 3,250,000 hz = 13M/4 ==> 1 Clk = 307.692307 nSec = 0.3077 MicroSec */
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/* Full Cycle = 32bit * 307.692307 nSec = ~21.9 Minutes. */
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//#define MAX_MICRO_SEC_INTERVAL_IN_32_BIT_REGISTER 0xFFFFFFFFL/307*100
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/*alex added*/
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/*#define MAX_MICRO_SEC_INTERVAL_32kHz_IN_32_BIT_REGISTER (0xFFFFFFFFL-1)/327*10000*/ // why these actions can leav it fffff..ff
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/*lena changed alex addings*/
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#define MAX_MICRO_SEC_INTERVAL_32kHz_IN_32_BIT_REGISTER (0xFFFFFFFFUL)
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#define MAX_MICRO_SEC_INTERVAL_FAST_IN_32_BIT_REGISTER (TIMER_USECS_IN_SECOND*(0xFFFFFFFFUL/FAST_TIMER_CLOCK_RATE_IN_HZ))
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//#define FAST_TIMER_CLOCK_RATE_IN_HZ 3250000
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#define TIMER_USECS_IN_SECOND 1000000
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#define FAST_TIMER_CLOCK_RATE_IN_HZ 13000000
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#define SLOW_TIMER_CLOCK_RATE_IN_HZ 32768
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#define SECONDS_TO_MICRO_SEC_RATIO 1000000
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#define MILISEC_TO_MICRO_SEC_RATIO 1000L
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//Fast clock (13Mhz/4)
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/*alex added*/
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#define MICRO_SEC_TO_CLOCK_TICKS(uSec) (uSec*13)
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#define CLOCK_TICKS_TO_MICRO_SEC(clockTicks) (clockTicks/13)
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#define CLOCK_TICKS_TO_MICRO_SEC_CLK_32KHZ(x) ((x)>(0xFFFFFFFF/15625)?((x/512)*15625+((x%512)*15625)/512):(((UINT32)(x)*15625)/512))
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#define CLOCK_TICKS_TO_MICRO_SEC_32K CLOCK_TICKS_TO_MICRO_SEC_CLK_32KHZ
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#define MICRO_SEC_TO_CLOCK_TICKS_CLK_32KHZ(x) ((x)>(0xFFFFFFFF/512)?((x/15625)*512+((x%15625)*512)/15625):(((UINT32)(x)*512)/15625))
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#define MICRO_SEC_TO_CLOCK_TICKS_CLK_FAST MICRO_SEC_TO_CLOCK_TICKS
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#define MICRO_SEC_TO_CLOCK_TICKS_CLK_1KHZ(uSec) ((uSec*1)/1000) // 0.001 * Tick = 1USec, Min value = 100 Usec, resolution 100 Usec
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/*#define MICRO_SEC_TO_CLOCK_TICKS_CLK_EXT(microSecInterval_4) ((microSecInterval_4 * 1) / 6) */ /* There is no pin for ext. clk */
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/************* Timers HW defenitions *****************************************/
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#define HALF_MAX_TCR 3 // First half is NDR, second - drowsy (if exists)
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#define NON_DROWSY_TIMERS_BASE_ADDRESS 0x40A00000UL
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#define DROWSY_TIMERS_BASE_ADDRESS 0x41A00000UL // _HERMON_, not implemented in Manitoba
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#define TIMER_BASE_ADDRESS 0xd4080000
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#define TIMER_EXT_BASE_ADDRESS 0xd403a000
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/******* 3 Match registers per TCR ******************************************/
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typedef struct {
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UINT32 match_reg_0 ; /* R/W */
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UINT32 match_reg_1 ; /* R/W */
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UINT32 match_reg_2 ; /* R/W */
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} T_MATCH_STR;
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/******* TCCR = Timer Clock Control Register *******************************/
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/*clock Source of tcr 0 */
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/*#define C_TCCR_CS_0_MASK 0xfffffffc */
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typedef enum
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{
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C_TCCR_CS_3_25MHZ,
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C_TCCR_CS_1KHZ,
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C_TCCR_CS_32KHz,
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C_TCCR_CS_EXT
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}Timer_TCCR_Clock_Type;
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#ifdef PHS_SW_DEMO_TTC
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#define C_TCCR_1_CS_3_25MHZ 0x00
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#define C_TCCR_2_CS_3_25MHZ 0x00
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#define C_TCCR_3_CS_3_25MHZ 0x00
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#define C_TCCR_1_CS_1KHZ NULL
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#define C_TCCR_2_CS_1KHZ 0x02
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#define C_TCCR_3_CS_1KHZ 0x01
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#define C_TCCR_1_CS_32KHz 0x01
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#define C_TCCR_2_CS_32KHz 0x01
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#define C_TCCR_3_CS_32KHz 0x02
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#define C_TCCR_1_CS_EXT 0x02
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#define C_TCCR_2_CS_EXT 0x03
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#define C_TCCR_3_CS_EXT NULL
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#else
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#define C_TCCR_CS_13MHZ 0x01
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#define C_TCCR_CS_32KHz 0x00
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//#define C_TCCR_CS_0_EXT 0x02
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#endif
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#define C_TCCR_CS_ERROR -1
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#ifdef PHS_SW_DEMO_TTC
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typedef union{
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UINT32 reg ;
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struct {
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unsigned
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cs_0 :2, /* R/W */
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cs_1 :3, /* R/W */
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cs_2 :2, /* R/W */
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cs_wdt :2, /* R/W */
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null :23;
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} tccr_bits;
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} T_TCCR;
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#else
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typedef union{
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UINT32 reg ;
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struct {
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unsigned
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cs_1 :2, /* R/W */
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cs_2 :2, /* R/W */
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cs_3 :2, /* R/W */
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cs_4 :2, /* R/W */
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null :24;
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} tccr_bits;
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} T_TCCR;
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#endif
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/******* TPLCR = Timer Preload Control Register ****************************/
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typedef struct {
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unsigned
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mcs :2, /* R/W Match Comperator Select */
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null :30;
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} T_TPLCR;
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/******* TSR = Timer Status Register ***********************/
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#define C_TSR_TIMER_NOT_MATCH_THE_COUNTER 0
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#define C_TSR_TIMER_MATCH_THE_COUNTER 1
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typedef union
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{
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UINT32 reg;
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struct {
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unsigned
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m_1 :1, /* R/w */
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m_2 :1, /* R/w */
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m_3 :1, /* R/w */
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m_4 :1, /* R/w */
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null :28;
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} tsr_bits;
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}
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T_TSR;
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/******** TIER = Timer Interrupt Enable Register ************/
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#define C_TIER_TIMER_DISABLE_MATCH 0
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#define C_TIER_TIMER_ENABLE_MATCH 1
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#define C_TIER_MATCH_0_MASK 0x00000001
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#define C_TIER_MATCH_1_MASK 0x00000002
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#define C_TIER_MATCH_2_MASK 0x00000004
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typedef union {
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UINT32 reg;
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struct {
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unsigned
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ie_0 :1, /* R/W interrupt enable for Match register 0 of TRCn */
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ie_1 :1, /* R/W interrupt enable for Match register 1 of TRCn */
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ie_2 :1, /* R/W interrupt enable for Match register 2 of TRCn */
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null :29;
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} tier_bits;
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}T_TIER;
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/******** TICR = Timer Interrupt Clear Register ************/
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#define C_TICR_TIMER_NO_AFFECT 0
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#define C_TICR_TIMER_CLEAR_INTERRUPT_AND_STATUS 1
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/******** TCER = Timer Coiunt Enable Register *******************************/
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typedef struct {
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unsigned
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ten_0 :1, /* R/W TCR_0 count enable */
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ten_1 :1, /* R/W TCR_1 count enable */
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ten_2 :1, /* R/W TCR_2 count enable */
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null :29;
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} T_TCER;
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/******** TCMR = Timer Count Mode Register **********************************/
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#ifdef PHS_SW_DEMO_TTC
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typedef union {
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UINT32 reg;
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struct {
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unsigned
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tmode_1 :1, /* R/W TCR_0 count mode */
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tmode_2 :1, /* R/W TCR_1 count mode */
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tmode_3 :1, /* R/W TCR_2 count mode */
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null :29;
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} tcmr_bits;
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} T_TCMR;
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#else
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typedef union {
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UINT32 reg;
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struct {
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unsigned
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tmode_1 :2, /* R/W TCR_0 count mode */
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tmode_2 :2, /* R/W TCR_1 count mode */
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tmode_3 :2, /* R/W TCR_2 count mode */
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tmode_4 :2, /* R/W TCR_2 count mode */
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null :24;
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} tcmr_bits;
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} T_TCMR;
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#endif
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#define TCR_TCMR_MASK (0x03)
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/******* TILR = Timer Interrupt Mode (Length) Register *********************/
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typedef enum
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{
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C_TILR_LEVEL, /* 0 */
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C_TILR_EDGE /* 1 */
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}TILR_MODES;
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typedef union
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{
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unsigned reg;
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struct
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{
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unsigned til_1 : 1; /* R/W interrupt mode for Match register 1 of TRCn */
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unsigned til_2 : 1; /* R/W interrupt mode for Match register 2 of TRCn */
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unsigned til_3 : 1; /* R/W interrupt mode for Match register 3 of TRCn */
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unsigned null : 29;
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} rcrd;
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} TIMER_T_TILR;
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#ifndef PHS_SW_DEMO_TTC
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typedef struct
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{
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UINT32 tmr;
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UINT32 tcr ;
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}
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T_MATCH_COUNT_STR;
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#endif
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typedef union
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{
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unsigned reg;
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struct
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{
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unsigned WE : 1; /* R/W watchdag enable counting */
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unsigned WMS : 1; /* R/W 0 - Generate interrupt , 1 - generate reset */
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unsigned null : 30;
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} wer_str;
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} T_WER_STR; /* watch dog enable reg */
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typedef struct {
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unsigned
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tclr_0 :1, /* W clear interrupt and status bit, for Match register 0 of TRCn */
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tclr_1 :1, /* W clear interrupt and status bit, for Match register 1 of TRCn */
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tclr_2 :1, /* W clear interrupt and status bit, for Match register 2 of TRCn */
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null :29;
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} T_TICR;
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/*******************************************************************/
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#ifdef PHS_SW_DEMO_TTC
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struct TIMER_HW_REGISTERS
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{
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T_TCCR tccr; /* R/W Timer Clock Control Reg */
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T_MATCH_STR tmr [MAX_HW_TCR_NUMBER]; /* R/W 3-match Reg per timer */
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UINT32 tcr [MAX_HW_TCR_NUMBER]; /* Read Only Timer Count Reg */
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T_TSR tsr [MAX_HW_TCR_NUMBER]; /* Read only Timer Status Register */
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T_TIER tier [MAX_HW_TCR_NUMBER]; /* R/W Timer Interrupt Enable Reg */
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UINT32 tplvr [MAX_HW_TCR_NUMBER]; /* R/W Timer Preload Value Reg */
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UINT32 tplcr [MAX_HW_TCR_NUMBER]; /* R/W Timer Preload Control Reg */
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UINT32 wd_regs[4]; /* Implemented in saperate WD driver */
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T_TICR ticr [MAX_HW_TCR_NUMBER]; /* Write only Timer Interrupt Clear Reg */
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UINT32 wd_twicr;
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UINT32 tcer; /* R/W Timer Count Enable Reg */
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T_TCMR tcmr; /* R/W Timer Count Mode Reg */
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TIMER_T_TILR tilr [MAX_HW_TCR_NUMBER]; /* R/W Timer Interrupt Mode (Level, Edge) */
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UINT32 dummy_twcr;
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UINT32 dummy_twfar;
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UINT32 dummy_twsar;
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UINT32 tcvwr [MAX_HW_TCR_NUMBER]; /* R/W Timer value wr-rd request */
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};
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#else
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struct TIMER_HW_REGISTERS
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{
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T_TCMR tcmr ; /* R/W Timer Count Mode Reg */
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T_TSR tsr ; /* Timer Status Register */
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T_TCCR tccr; /* R/W Timer Clock Control Reg */
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T_TIER tier ; /* R/W Timer Interrupt Enable Reg */
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T_MATCH_COUNT_STR tmatch_count[MAX_TCR_NUMBER]; /* R/W match & count regs per timer */
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/* WatchDog Registers*/
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UINT32 wtpr;
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UINT32 wcr;
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T_WER_STR wer;
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UINT32 wfar;
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UINT32 wsar;
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UINT32 wcrr;
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UINT32 Reserved_1;
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UINT32 Reserved_2;
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/* Shadow registers for COMM--MSA dual core access*/
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T_TCMR tcmr_A; /* R/W Timer Count Mode Shadow Reg */
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T_TSR tccr_A; /* R/W Timer Clock Control Shadow Reg */
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T_TIER tier_A; /* R/W Timer Interrupt Enable Shadow Reg*/
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}; /* TIMER_HW_REGISTERS */
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#endif
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/* Setting physical addresses for Timers HW registers */
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#define NON_DROWSY_HW_REG (* (volatile struct TIMER_HW_REGISTERS *) NON_DROWSY_TIMERS_BASE_ADDRESS)
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#define DROWSY_HW_REG (* (volatile struct TIMER_HW_REGISTERS *) DROWSY_TIMERS_BASE_ADDRESS)
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//#define TIMER_USE_TCVWR //TCVWR latching time is too long, therefore not recommended
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/*--------- Global constants definitions ------------------------------------*/
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/*--------- Local constants definitions -------------------------------------*/
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/*-------- Local macro definitions ------------------------------------------*/
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/*-------- Local type definitions -------------------------------------------*/
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/* This structure holds all important information regarding a specific tcr */
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typedef struct
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{
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UINT32 microSec; /*timer interval in microseconds */
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UINT32 timerAddingValue; /*time interval to add in SW periodic mode */
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TCMR_MODES repetative_mode; /*one shot or HW periodic or SW preiodic */
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TCMR_MODES real_mode ;
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TIMER_CALLBACK_FUNCTION timerNotificationPtr; /*a pointer to the callback function at timer experation */
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UINT8 cookie; /* this parameter is return uchanged from Callback routine */
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/* additions for whitesail */
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/*MATCH_NUMBER match_number; */ /* range [0..2] */
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CLOCK_MODES clock_mode; /* fast = vtcxo/4, 32Khz, 1Khz, 256 Hz and Ext. */
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BOOL busy;
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UINT8 interrupt_required; /* cause an interrupt when timer expiered ? */
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UINT32 last32kValue; /* last read 32kHz value. May be used as "cached"*/
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} TIMER_CONFIG_STR;
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typedef struct
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{
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volatile struct TIMER_HW_REGISTERS *timer_hw_ptr; /* according to Drowsy Non-Drowsy regions */
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UINT8 ireg; /* register index (0..2) inside the timer module */
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UINT8 intcid; /* INTC interrupt ID */
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UINT8 apbclock;
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UINT8 pmuclock;
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}TIMER_CONST_STR;
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#endif
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