430 lines
17 KiB
C
430 lines
17 KiB
C
/*------------------------------------------------------------
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(C) Copyright [2006-2008] Marvell International Ltd.
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All Rights Reserved
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------------------------------------------------------------*/
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/*****************************************************************************************************************************
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* MODULE IMPLEMENTATION FILE
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*******************************************************************************************************************************
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* COPYRIGHT (C) 2001 Intel Corporation.
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*
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* This file and the software in it is furnished under
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* license and may only be used or copied in accordance with the terms of the
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* license. The information in this file is furnished for informational use
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* only, is subject to change without notice, and should not be construed as
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* a commitment by Intel Corporation. Intel Corporation assumes no
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* responsibility or liability for any errors or inaccuracies that may appear
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* in this document or any software that may be provided in association with
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* this document.
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* Except as permitted by such license, no part of this document may be
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* reproduced, stored in a retrieval system, or transmitted in any form or by
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* any means without the express written consent of Intel Corporation.
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*
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* Title: UART Package Hardware Access
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*
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* Filename: HW_Access.h
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*
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* Target, subsystem: Common Platform, HAL
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*
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* Authors: ILANA BEN-ARIE
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*
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* Description:
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*
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* Last Modified: <Initial> <date>
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*
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* Notes:
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*******************************************************************************************************************************/
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#ifndef _HW_ACCESS_D_H_
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#define _HW_ACCESS_D_H_
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#include "UART_config.h"
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#if defined (UART_SINGLE_PORT)
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//for tavor - only port number 2 (UART_PORT_STUART)
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#define HW_UART_WAKEUP(uartAddress) UARTWakeUp(UART_PORT_STUART);
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#else
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#define HW_UART_WAKEUP(uartAddress) \
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UARTWakeUp((((uartAddress) >> 20) & 0x03) - 1 );
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#endif
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/*************************** Register Addresses **********************************************************/
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#define MULT_BY_NUM 4L
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#define UART_RHR_ADD (0x0*MULT_BY_NUM) /* Receiver Holding Register offset */
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#define UART_THR_ADD (0x0*MULT_BY_NUM) /* Transmiter Holding Register offset */
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#define UART_IER_ADD (0x1*MULT_BY_NUM) /* Interrupt Enable Register offset */
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#define UART_IIR_ADD (0x2*MULT_BY_NUM) /* Interrupt Identification Register offset */
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#define UART_FCR_ADD (0x2*MULT_BY_NUM) /* FIFO Control Register offset */
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#define UART_LCR_ADD (0x3*MULT_BY_NUM) /* Line Control Register offset */
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#define UART_MCR_ADD (0x4*MULT_BY_NUM) /* Modem Control Register offset */
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#define UART_LSR_ADD (0x5*MULT_BY_NUM) /* Line Status Register offset */
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#define UART_MSR_ADD (0x6*MULT_BY_NUM) /* Modem Status Register offset*/
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#define UART_SPR_ADD (0x7*MULT_BY_NUM) /* Scratch Pad Register offset */
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#define UART_ISR_ADD (0x8*MULT_BY_NUM) /* Infrared Selection Register offset */
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#define UART_FOR_ADD (0x9*MULT_BY_NUM) /* Receive FIFO Occupancy Register offset */
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#define UART_DLL_ADD (0x0*MULT_BY_NUM) /* LSB divisor latch register offset */
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#define UART_DLM_ADD (0x1*MULT_BY_NUM) /* MSB divisor latch register offset */
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#define UART_ABR_ADD (0x28) /* Auto-Baud Control Register offset for crane */
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#define UART_ACR_ADD (0x2C) /* Auto-Baud Control Register offset for crane */
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/* bit affects the selection of some UART register */
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#define UART_AB_MCR_ADD (0x8*MULT_BY_NUM) /* Mode Control Register */
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/*************************** Register Bit Definitions *****************************************************************/
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/***** IER ******/
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#define IER_RCV_DATA_AVAILABLE 0x01L /* Enable Received Data Available interrupt (in FIFO mode) */
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#define IER_TRN_HOLDING_EMPTY 0x02L /* Enable Transmit Data Request Interrupt */
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#define IER_RCV_LINE_STATUS 0x04L /* Enable Receiver Line Status interrupt */
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#define IER_MODEM_STATUS 0x08L /* Enable Modem interrupt */
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#define IER_TIME_OUT 0x10L /* Enable Receive Time Out Interupt */
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#define IER_NRZE 0x20L /* Enable NRZ */
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#define IER_UART_UNIT 0x40L /* Enable UART Unit */
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#define IER_DMA 0x80L /* Enable DMA requests */
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#define IER_ALL_BITS 0xFFL /* Enable all the IER bits */
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#define IER_ALL_BITS_EXCEPT_DMA (IER_RCV_DATA_AVAILABLE | IER_TRN_HOLDING_EMPTY| IER_TIME_OUT | IER_RCV_LINE_STATUS | IER_MODEM_STATUS /* | IER_NRZE */| IER_UART_UNIT ) /* Enable the 4 -LSB except trensmit */
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#define IER_ALL_BITS_EXCEPT_TRANS_AND_MODEM_AND_DMA (IER_RCV_DATA_AVAILABLE | IER_TIME_OUT | IER_RCV_LINE_STATUS/* | IER_MODEM_STATUS*/ )
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#define IER_ALL_BITS_EXCEPT_TRANS (IER_RCV_DATA_AVAILABLE | IER_TIME_OUT | IER_RCV_LINE_STATUS | IER_MODEM_STATUS )
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#define IER_ALL_BITS_EXCEPT_MODEM (IER_RCV_DATA_AVAILABLE | IER_TRN_HOLDING_EMPTY| IER_TIME_OUT | IER_RCV_LINE_STATUS )
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#define IER_ALL_BITS_EXCEPT_TRANS_AND_MODEM_AND_TMIE (IER_RCV_DATA_AVAILABLE | IER_RCV_LINE_STATUS)
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#define IER_ALL_BITS_EXCEPT_TRANS_AND_RCV_AND_MODEM (IER_TIME_OUT | IER_RCV_LINE_STATUS | IER_UART_UNIT | IER_DMA) /* Enable the 4 -LSB except trensmit */
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#define IER_ALL_BITS_EXCEPT_TRANS_AND_RCV (IER_TIME_OUT | IER_RCV_LINE_STATUS | IER_UART_UNIT | IER_DMA | IER_MODEM_STATUS )
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#define IER_ALL_BITS_EXCEPT_TRANS_AND_MODEM (IER_RCV_DATA_AVAILABLE | IER_TIME_OUT | IER_RCV_LINE_STATUS | IER_UART_UNIT | IER_DMA) /* Enable the 4 -LSB except trensmit */
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#define IER_ALL_BITS_EXCEPT_TRANS_AND_DMA (IER_RCV_DATA_AVAILABLE | IER_TIME_OUT | IER_RCV_LINE_STATUS | IER_MODEM_STATUS )
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/***** IIR ******/
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/* Possible interrupt values */
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#define IIR_NO_PENDING_INT 0x01L /* Interrupt pending */
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#define IIR_MODEM_STATUS 0x00L /* modem status */
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#define IIR_TRANS_FIFO_REQ 0x02L /* transmit fifo request data */
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#define IIR_REC_DATA 0x04L /* Reveived Data Available */
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#define IIR_REC_ERROR 0x06L /* Received error framing */
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#define IIR_TIME_OUT 0x0cL /* Time-out Interrupt pending (on FIFI mode) */
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#define IIR_AUTO_BAUD_LOCK 0x10L /* Auto-baud Lock */
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#define IIR_SOURCE_MASKED 0x06L
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/* Possible FIFO section values */
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#define IIR_NON_FIFO 0x00L /* non-FIFO mode selection */
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#define IIR_FIFO_ENABLED 0xc0L /* FIFO enabled selection */
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#define IIR_FIFO_UNUSABLE 0x80L /* FIFO enabled but unusable */
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#define IIR_INT_MASK 0x06L /* data concerning interrupt (not FIFO) */
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#define IIR_FIFO_MASK 0xC0L /* data concerning FIFO (not interrupt) */
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/***** FCR ******/
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#define FCR_DISABLE_FIFO 0x00L /* Disable FIFO's */
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#define FCR_ENABLE_FIFO 0x01L /* Enable FIFO's */
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#define FCR_CLEAR_RCV 0x02L /* Clear Receive FIFO */
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#define FCR_CLEAR_TRANS 0x04L /* Clear Transmit FIFO */
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/* TX Interrupt trigger level definitions */
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#define FCR_TX_ZERO_INT 0x08L /* Interrupt when TX FIFO empty */
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#define FCR_TX_HALF_INT 0x00L /* Interrupt when TX FIFO at least half empty */
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#define FCR_TRAIL_INT 0x00L /* Rx trailing bytes read by Processor */
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#define FCR_TRAIL_DMA 0x10L /* Rx trailing bytes read by DMA engine */
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#define FCR_BUS_8BIT 0x00L /* 8bit bus interface (default) */
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#define FCR_BUS_32BIT 0x20L /* 32bit bus interface */
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/* RX Interrupt trigger level definitions */
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#define FCR_INT_TRIGGER_L0 0x00L /* set Int Trigger Level 1 */
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#define FCR_INT_TRIGGER_L8 0x40L /* -"-"-"-"-"-"-"-"-"-"-"8 */
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#define FCR_INT_TRIGGER_L16 0x80L /* -"-"-"-"-"-"-"-"-"-"-"16 */
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#define FCR_INT_TRIGGER_L32 0xC0L /* -"-"-"-"-"-"-"-"-"-"-"32 */
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/***** LCR ******/
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#define LCR_WORD_LEN_5 0x00L /* set Word Lengto to 5 Bits */
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#define LCR_WORD_LEN_6 0x01L /* set Word Lengto to 6 Bits */
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#define LCR_WORD_LEN_7 0x02L /* set Word Lengto to 7 Bits */
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#define LCR_WORD_LEN_8 0x03L /* set Word Lengto to 8 Bits */
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#define LCR_ONE_STOP_BIT 0x00L /* set One Stop Bit */
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#define LCR_TWO_STOP_BITS 0x04L /* Two Stop bits when words of length 6,7 or 8 bits, */
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/* 1.5 Stop Bits when words of length 5 bits */
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#define LCR_NO_PARITY 0x00L /* No Parity */
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#define LCR_ODD_PARITY 0x08L /* Odd Parity */
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#define LCR_EVEN_PARITY 0x18L /* Even Parity */
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#define LCR_STICKY_PARITY_LOW 0x38L /* Low Parity (Sticky) */
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#define LCR_STICKY_PARITY_HIGH 0x28L /* High Parity (Sticky) */
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#define LCR_BREAK_DISABLE 0xBFL /* Clear Break Enable */
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#define LCR_BREAK_ENABLE 0x40L /* Set Break Enable */
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#define LCR_DLAB_SET 0x80L /* Divisor Latch Access Bit */
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#define LCR_DLAB_UNSET 0x00L /* Access BRB,THR, IER */
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/***** MCR ******/
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#define MCR_FORCE_DTR 0x00L /* Force Data Terminal Ready */
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#define MCR_FORCE_RTS 0x02L /* Force Request to Send */
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#define MCR_ENABLE_INTS 0x08L /* Aux Output 2 -Ring Indication */
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#define MCR_AFE 0x20L /* Auto Flow Control */
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#define MCR_CLEAR_FORCE_RTS_MASK 0xfffffffdL /* Request To send */
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#define MCR_CLEAR_FORCE_DTR_MASK 0xfffffffeL /* Data Terminal Ready */
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/***** LSR ******/
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#define LSR_DATA_READY 0x01L /* Data ready in the RX FIFO */
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#define LSR_OVRRUN_ERR 0x02L /* Framing Error */
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#define LSR_PARITY_ERR 0x04L /* Parity error detected */
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#define LSR_FRAMING_ERR 0x08L /* Framing error detected */
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#define LSR_BREAK_INT 0x10L /* break Interrupt */
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#define LSR_EMP_TREG 0x20L /* Empty Transmitter Holding Register - more then 32 byte inthe fIFO are free */
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#define LSR_EMP_DATA 0x40L /* Empty Data Holding Registers - 64 byte in the FIFO are free */
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#define LSR_FIFO_ERR 0x80L /* Error in Received FIFO */
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#define LSR_FIFO_EMPTY 0x60L /* Both TREG & DATA are empty -> FIFO empty on FIFO mode */
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#define LSR_ERROR_MASK 0x0EL /* masking error bits out of LSR */
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/***** MSR ******/
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#define MSR_DELTA_CTS 0x01L /* Delta Clear to Send */
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#define MSR_DELTA_DSR 0x02L /* Delta Data Set Ready */
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#define MSR_TRAILING_RI 0x04L /* Trailing Edge Ring Indicator */
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#define MSR_DELTA_DATA_CD 0x08L /* Delta Data Carrier Detect */
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#define MSR_CTS 0x10L /* Clear To Send */
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#define MSR_DSR 0x20L /* Data Set Ready */
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#define MSR_RI 0x40L /* Ring Indicator */
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#define MSR_CD 0x80L /* Carrier Detect */
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/***** IrDa ******/
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#define UART_ISR_RXPL 0x10 /* SIR decoder takes negative pulses as zeros */
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#define UART_ISR_TXPL 0x08 /* SIR encoder takes negative pulses as zeros */
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#define UART_ISR_XMODE 0x04 /* Transmit 1.6 microsec width pulses */
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#define UART_ISR_RCVEIR 0x02 /* Receiver input is in infrared mode */
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#define UART_ISR_XMITIR 0x01 /* Transmitter output is in infrared mode */
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#define UART_ISR_ALL_ZERO_UART_DEFUALT 0 /* postive pulses as zeros, normal pulse, UART input/output mode */
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/***** Auto-Baud ******/
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#define UART_ABR_ABT 0x08 /* Formula used to calculate baud rates */
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#define UART_ABR_ABUP 0x04 /* Programs Divisor Latch registers */
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#define UART_ABR_ABLIE 0x02 /* Auto-baud-lock interrupt, 0-disabled, 1-enabled */
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#define UART_ABR_ABE 0x01 /* Auto-baud enable*/
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/*************** WRITE to UART registers - inline functions **********************************************************/
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//TBD these macro's used from outside UART as well as from inside it.
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#define UARTWakeUp(port) UARTOn((UART_Port)(port),UART_ACTIVITY_EXT)
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#define HW_UART_WRITE_THR(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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(*((volatile UINT32 *)((uart) + UART_THR_ADD)) = (val));\
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}
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#define HW_UART_WRITE_DLL(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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(*((volatile UINT32 *)((uart) + UART_DLL_ADD)) = (val));\
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}
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#define HW_UART_WRITE_DLM(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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(*((volatile UINT32 *)((uart) + UART_DLM_ADD)) = (val));\
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}
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#define HW_UART_WRITE_IER(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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(*((volatile UINT32 *)((uart) + UART_IER_ADD)) = (val));\
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}
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#define HW_UART_IER_DISABLE_INT(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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((*((volatile UINT32 *)((uart) + UART_IER_ADD))) &= (~(val)));\
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}
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#define HW_UART_IER_ENABLE_INT(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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((*((volatile UINT32 *)((uart) + UART_IER_ADD))) |= (val));\
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}
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#define HW_UART_WRITE_FCR(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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(*((volatile UINT32 *)((uart) + UART_FCR_ADD)) = (val));\
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}
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#define HW_UART_WRITE_IIR(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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(*((volatile UINT32 *)((uart) + UART_IIR_ADD)) = (val));\
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}
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#define HW_UART_WRITE_LCR(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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(*((volatile UINT32 *)((uart) + UART_LCR_ADD)) = (val));\
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}
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#define HW_UART_WRITE_MCR(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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(*((volatile UINT32 *)((uart) + UART_MCR_ADD)) = (val));\
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}
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#define HW_UART_WRITE_LSR(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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(*((volatile UINT32 *)((uart) + UART_LSR_ADD)) = (val));\
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}
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#define HW_UART_WRITE_SPR(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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(*((volatile UINT32 *)((uart) + UART_SPR_ADD)) = (val)); \
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}
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#define HW_UART_WRITE_ISR(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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(*((volatile UINT32 *)((uart) + UART_ISR_ADD)) = (val)); \
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}
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#define HW_UART_WRITE_AB_MCR(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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(*((volatile UINT32 *)((uart) + UART_AB_MCR_ADD)) = (val)); \
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}
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#define HW_UART_WRITE_ABR(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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(*((volatile UINT32 *)((uart) + UART_ABR_ADD)) = (val)); \
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}
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/*************** READ from UART registers - inline functions *********************************************************/
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#define HW_UART_READ_RHR(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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((val) = (BYTE)(*((volatile UINT32 *)((uart) + UART_RHR_ADD)))); \
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}
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#define HW_UART_READ_DLL(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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((val) = *((volatile UINT32 *)((uart) + UART_DLL_ADD))); \
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}
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#define HW_UART_READ_DLM(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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((val) = *((volatile UINT32 *)((uart) + UART_DLM_ADD))); \
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}
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#define HW_UART_READ_IER(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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((val) = *((volatile UINT32 *)((uart) + UART_IER_ADD))); \
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}
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#define HW_UART_READ_IIR(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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((val) = *((volatile UINT32 *)((uart) + UART_IIR_ADD))); \
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}
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#define HW_UART_READ_LCR(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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((val) = *((volatile UINT32 *)((uart) + UART_LCR_ADD))); \
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}
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#define HW_UART_READ_MCR(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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((val) = *((volatile UINT32 *)((uart) + UART_MCR_ADD))); \
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}
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#define HW_UART_READ_LSR(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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((val) = *((volatile UINT32 *)((uart) + UART_LSR_ADD))); \
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}
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#define HW_UART_READ_MSR(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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((val) = *((volatile UINT32 *)((uart) + UART_MSR_ADD))); \
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}
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#define HW_UART_READ_SPR(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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((val) = *((volatile UINT32 *)((uart) + UART_SPR_ADD))); \
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}
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#define HW_UART_READ_ISR(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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((val) = *((volatile UINT32 *)((uart) + UART_ISR_ADD))); \
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}
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#define HW_UART_READ_FOR(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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((val) = *((volatile UINT32 *)((uart) + UART_FOR_ADD))); \
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}
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#define HW_UART_READ_FCR(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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((val) = *((volatile UINT32 *)((uart) + UART_FCR_ADD))); \
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}
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#define HW_UART_READ_ABR(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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((val) = *((volatile UINT32 *)((uart) + UART_ABR_ADD))); \
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}
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#define HW_UART_READ_ACR(uart,val) \
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{ \
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HW_UART_WAKEUP(uart); \
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((val) = *((volatile UINT32 *)((uart) + UART_ACR_ADD))); \
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}
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#define SET_DLAB_BIT (*((volatile UINT32*)0xd40a000c) |= 0x80)
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#define RESET_DLAB_BIT (*((volatile UINT32*)0xd40a000c) &= 0xFFFFFF7F)
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#endif /* __HW_ACCESS_D_H__ */
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