182 lines
7.0 KiB
C
182 lines
7.0 KiB
C
/*------------------------------------------------------------
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(C) Copyright [2006-2008] Marvell International Ltd.
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All Rights Reserved
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------------------------------------------------------------*/
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/*******************************************************************
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*
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*
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* HISTORY:
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* YK 21 March 2007 duplicated APIs to reside on both DDR (for init) and TCM (for D2 exit)
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* SE 05 Decemeber 2007 TTC modifications
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* NOTE:
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* APIs with _DS _TCS mean they are duplicated twice, to run at init from DDR
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* and to run from TCM on D2 exit. The source files are duplicated in CC and controlled
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* by compilation switch and MACROS of FUNCNAME_CTRL, TABLENAME_CTRL
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*
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**********************************************************************************/
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#ifndef __ARM496E_MPU_H__
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#define __ARM496E_MPU_H__
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#include "arm946e_config.h"
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#include "global_types.h"
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// Access permission encoding
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#define ARM946E_MPU_ATT_SUP_NO_ACCESS_USR_NO_ACCESS (0x0L) // (b0000)
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#define ARM946E_MPU_ATT_SUP_RW_USR_NO_ACCESS (0x1L) // (b0001)
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#define ARM946E_MPU_ATT_SUP_RW_USR_R (0x2L) // (b0010)
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#define ARM946E_MPU_ATT_SUP_RW_USR_RW (0x3L) // (b0011)
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#define ARM946E_MPU_ATT_SUP_R_USR_NO_ACCESS (0x5L) // (b0101)
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#define ARM946E_MPU_ATT_SUP_R_USR_R (0x6L) // (b0110)
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// Instruction & data access permission masks
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#define ARM946E_MPU_AP_MASK (0x0000000F)
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#define ARM946E_MPU_AP0_MASK (0xFFFFFFF0)
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#define ARM946E_MPU_AP1_MASK (0xFFFFFF0F)
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#define ARM946E_MPU_AP2_MASK (0xFFFFF0FF)
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#define ARM946E_MPU_AP3_MASK (0xFFFF0FFF)
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#define ARM946E_MPU_AP4_MASK (0xFFF0FFFF)
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#define ARM946E_MPU_AP5_MASK (0xFF0FFFFF)
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#define ARM946E_MPU_AP6_MASK (0xF0FFFFFF)
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#define ARM946E_MPU_AP7_MASK (0x0FFFFFFF)
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// Region size encoding
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#define ARM946E_MPU_REGION_SIZE_4K (0xBL) // (b01011)
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#define ARM946E_MPU_REGION_SIZE_8K (0xCL) // (b01100)
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#define ARM946E_MPU_REGION_SIZE_16K (0xDL) // (b01101)
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#define ARM946E_MPU_REGION_SIZE_32K (0xEL) // (b01110)
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#define ARM946E_MPU_REGION_SIZE_64K (0xFL) // (b01111)
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#define ARM946E_MPU_REGION_SIZE_128K (0x10L) // (b10000)
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#define ARM946E_MPU_REGION_SIZE_256K (0x11L) // (b10001)
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#define ARM946E_MPU_REGION_SIZE_512K (0x12L) // (b10010)
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#define ARM946E_MPU_REGION_SIZE_1M (0x13L) // (b10011)
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#define ARM946E_MPU_REGION_SIZE_2M (0x14L) // (b10100)
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#define ARM946E_MPU_REGION_SIZE_4M (0x15L) // (b10101)
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#define ARM946E_MPU_REGION_SIZE_8M (0x16L) // (b10110)
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#define ARM946E_MPU_REGION_SIZE_16M (0x17L) // (b10111)
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#define ARM946E_MPU_REGION_SIZE_32M (0x18L) // (b11000)
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#define ARM946E_MPU_REGION_SIZE_64M (0x19L) // (b11001)
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#define ARM946E_MPU_REGION_SIZE_128M (0x1AL) // (b11010)
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#define ARM946E_MPU_REGION_SIZE_256M (0x1BL) // (b11011)
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#define ARM946E_MPU_REGION_SIZE_512M (0x1CL) // (b11100)
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#define ARM946E_MPU_REGION_SIZE_1G (0x1DL) // (b11101)
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#define ARM946E_MPU_REGION_SIZE_2G (0x1EL) // (b11110)
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#define ARM946E_MPU_REGION_SIZE_4G (0x1FL) // (b11111)
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typedef struct{
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U32Bits iattributs;
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U32Bits dattributs;
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}CMpuRegionAttributes;
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// General definitions
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typedef enum{
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ARM946E_MPU_NO_REGION =-1,
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ARM946E_MPU_REGION_0 = 0,
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ARM946E_MPU_REGION_1,
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ARM946E_MPU_REGION_2,
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ARM946E_MPU_REGION_3,
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ARM946E_MPU_REGION_4,
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ARM946E_MPU_REGION_5,
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ARM946E_MPU_REGION_6,
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ARM946E_MPU_REGION_7,
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ARM946E_MPU_REGIONS_NUM
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}EMpuRegionsId;
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typedef enum{
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ARM946E_MPU_REGION_DISABLE,
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ARM946E_MPU_REGION_ENABLE
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}EMpuRegionMode;
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typedef struct{
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EMpuRegionsId regionId;
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UINT32 baseAddress;
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UINT32 regionSize;
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BOOL isICachable;
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BOOL isDCachable;
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BOOL isBufferable;
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CMpuRegionAttributes attributes;
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EMpuRegionMode regionEnableDisable;
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}Arm946eMpuMemoryRegion;
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#if defined (TTC_CORE_ARM946_CP15)
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extern const Arm946eMpuMemoryRegion _arm946eMpuRegions_DS[ARM946E_MPU_REGIONS_NUM];
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#else
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extern const Arm946eMpuMemoryRegion _arm946eMpuRegions_UpRO_DS[ARM946E_MPU_REGIONS_NUM];
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extern const Arm946eMpuMemoryRegion _arm946eMpuRegions_10MB_DS[ARM946E_MPU_REGIONS_NUM];
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extern const Arm946eMpuMemoryRegion _arm946eMpuRegions_12MB_DS[ARM946E_MPU_REGIONS_NUM];
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extern const Arm946eMpuMemoryRegion _arm946eMpuRegions_UpRO_TCS[ARM946E_MPU_REGIONS_NUM];
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extern const Arm946eMpuMemoryRegion _arm946eMpuRegions_10MB_TCS[ARM946E_MPU_REGIONS_NUM];
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extern const Arm946eMpuMemoryRegion _arm946eMpuRegions_12MB_TCS[ARM946E_MPU_REGIONS_NUM];
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#endif
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#if defined (TTC_CORE_ARM946_CP15)
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/*added to keep current common API for Tavor & TTC*/
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#define Arm946MpuInitRegion_TCS Arm946MpuInitRegion_DS
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#define Arm946eMpuInit_TCS Arm946eMpuInit_DS
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#define EnableITCM_TCS EnableITCM_DS
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#endif
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// functions prototypes
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void Arm946MpuRegionsDelete(void);
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void Arm946eMpuInit_DS(BOOL bEnableMpu);
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void Arm946eMpuInit_TCS(BOOL bEnableMpu);
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void Arm946eMpuLoadToITCM(UINT32 srcAddress,UINT32 destAddress,UINT32 length);
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void Arm946eMpuLoadToDTCM(UINT32 srcAddress,UINT32 destAddress,UINT32 length);
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void EnableITCM_DS(UINT32 ARM946E_TCM_SIZE_code);
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void EnableITCM_TCS(UINT32 ARM946E_TCM_SIZE_code);
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void Arm946eMpuITCMRegion_Init(void);
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void Arm946eSetRegionBufferedAttr(EMpuRegionsId regionId,BOOL enable);
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// function declaration to delegate between the regular and memRetain modules
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extern void Arm946MpuInitRegion_DS(const Arm946eMpuMemoryRegion * region);
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extern void Arm946MpuInitRegion_TCS(const Arm946eMpuMemoryRegion * region);
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extern void Arm946eMpuSetITCMRegionAttributs(CMpuRegionAttributes newAttributs );
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//#define MSA_L2_SRAM_BASE_ADDR 0xD1E00000
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//#define MSA_ARM_SHARED_BASE_ADDR 0xD1E00000
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//#define AHB_SRAM_BASE_ADDR 0xCFD00000
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//#define APB_DEVICES_BASE_ADDR 0xD4000000
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//#define GB_SYS_MMR_BASE_ADDR 0xFFD00000
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#define ITCM_BASE_ADDR 0x00000000 // Shaul - should be removed from here. Should use arbel.h
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//Refer also DDR_NONCACHE_REGION in scatter file and correct region size in SMPU
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//Refer also preprocessor's define DDR_RO_SIZE in scatter file.
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//Refer also preprocessor's define HARBELL_DDR_BASE_ADDR in scatter file.
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#if !defined (TTC_CORE_ARM946_CP15)
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#define HARBELL_DDR_BASE_ADDR ((UINT32)(&Load$$LOAD_TABLE$$Base))
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extern UINT32 Load$$LOAD_TABLE$$Base;
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#define DDR_NON_CACH_BASE_ADDR ((UINT32)(&Image$$DDR_NONCACHE_REGION$$Base))
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extern UINT32 Image$$DDR_NONCACHE_REGION$$Base;
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#endif
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#if defined (TTC_CORE_ARM946_CP15)
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#define MPU_ITCM_REGION ARM946E_MPU_REGION_0
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#define MPU_ITCM_REGION_TABLE_IDX MPU_ITCM_REGION
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#define MPU_DTCM_REGION ARM946E_MPU_REGION_1
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#define MPU_DTCM_REGION_TABLE_IDX MPU_DTCM_REGION
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#define MPU_MSA_SRAM_REGION ARM946E_MPU_REGION_5
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// is TTC_CORE_ARM946_CP15
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#else
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// not TTC_CORE_ARM946_CP15
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#define MPU_ITCM_REGION ARM946E_MPU_REGION_6
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#define MPU_ITCM_REGION_TABLE_IDX MPU_ITCM_REGION
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#define MPU_DTCM_REGION ARM946E_MPU_REGION_0
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#define MPU_DTCM_REGION_TABLE_IDX MPU_DTCM_REGION
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#endif//TTC_CORE_ARM946_CP15
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#endif //__ARM496E_MPU_H__
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