215 lines
8.9 KiB
C
215 lines
8.9 KiB
C
/*------------------------------------------------------------
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(C) Copyright [2006-2008] Marvell International Ltd.
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All Rights Reserved
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------------------------------------------------------------*/
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/* ###########################################################################
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### Intel Confidential
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### Copyright (c) Intel Corporation 1995-2001
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### All Rights Reserved.
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### -------------------------------------------------------------------------
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### Project: BSP
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###
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### Module: MMAP.H - This module consists of memory map configuration definitions
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###
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###########################################################################*/
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#ifndef _MMAP_H_
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#define _MMAP_H_
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#include "gbl_types.h"
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#include "mmu.h"
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#include "bsp.h"
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#include "loadTable.h" // for ADDR_CONVERT definition
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extern UINT32 Image$$EXT_RAM_FIRST$$Base;
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/****************************************************************************************
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* Non FULL_SYSTEM (PLATFORM_ONLY for example) Target by default has reduced memory mapping
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* But it may be forced to INT+EXT upon Target Variant request
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* In that case the MMAP_EXTENDED_INT_EXT_RAM_FLASH may be already defined in makefile
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******/
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#if defined(FULL_SYSTEM) && !defined(MMAP_EXTENDED_INT_EXT_RAM_FLASH)
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#define MMAP_EXTENDED_INT_EXT_RAM_FLASH
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#endif
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// VIRTUAL MEMORY MAP: SHOULD BE ALIGNED WITH THE LINK CONTROL FILE
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//=== ALLOC management ===
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#if !defined (MMAP_EXTENDED_INT_EXT_RAM_FLASH) && !defined(_TAVOR_BOERNE_)
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// !FULL_SYSTEM is PLATFORM-Only
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#define MALLOC_ORDER_IS_INT2EXT
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#endif
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#if defined(_FDI_VER_71_) /*FDI7 small chunks workaround, but FDI5 doesn't need them */
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#define CSW_MEM_SMALL_PARTITION_COUNT 1500 /*Number of chunks*/
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//#define FDI_USES_STATIC_RAM_POOL /* Another possibility */
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#else
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#define CSW_MEM_SMALL_PARTITION_COUNT 0 /*Don't use chunks*/
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#endif
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// Top area of internal flash reserved (for MSA), affects FDI partition location
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//#define INT_FLASH_RESERVED_SIZE 0x10000
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//-----------------------------------------------------------------------------------------------------------------------------
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#if defined(INTEL_2CHIP_PLAT_BVD) || defined(_TAVOR_BOERNE_)
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#if !defined (NO_INT_FLASH_USAGE)
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#define NO_INT_FLASH_USAGE
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#endif
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#endif
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#if defined (NO_INT_FLASH_USAGE)
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// no INT-flash
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#else//BVD
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#if !defined (MMAP_EXTENDED_INT_EXT_RAM_FLASH)
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#define FDI_INTERNAL_FLASH
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#else
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#if ( defined(HERMON_MCP2_CFG) || defined(INTEL_2CHIP_PLAT) )
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#define FDI_INTERNAL_FLASH
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#endif
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#endif
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#endif//BVD
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#if defined(_FDI_VER_71_INT_)
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#define FDI_INTERNAL_FLASH
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#endif
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// Size of FDI partition
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// This MUST be a compile-time constant
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#if !defined(FDI_INTERNAL_FLASH)
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#if defined (MMAP_EXTENDED_INT_EXT_RAM_FLASH) && !(defined(INTEL_2CHIP_PLAT_BVD) || defined(_TAVOR_BOERNE_))
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#define FDI_PARTITION_SIZE 0x00800000
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#else
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#define FDI_PARTITION_SIZE 0x00100000
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#endif
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#else
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#define FDI_PARTITION_SIZE 0x00030000
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#endif
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// Size of Application Code + RO data
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#define APP_CODE_SIZE (_4MB - FDI_PARTITION_SIZE) /*bspGetProgramRomSize()*/
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// FDI partition offset from CS start (physical space)
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#define FDI_PARTITION_BASE_PH_OFFSET (APP_CODE_SIZE)
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// Start address of FDI partition - virtual address (same for all configurations)
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#if (!defined(_FDI_VER_71_) && !defined(DATALIGHT))
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#define FDI_PARTITION_BASE_ADDRESS (_64MB -_16MB)
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#else //for FDI71 or 2Chip Bulverde
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#define FDI_PARTITION_BASE_ADDRESS (CACHED_TO_NON_CACHED_OFFSET)
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#endif //_FDI_VER_71
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//-----------------------------------------------------------------------------------------------------------------------------
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// Disable cache for the QuickTurn:
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#ifdef _QT_
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//#define DISABLE_DCACHE
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#endif
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///////////////////////////////////////////////////////////////////////////////
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// Virtual address space for non-cacheable areas - mainly for DMA use
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///////////////////////////////////////////////////////////////////////////////
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#if !defined(SILICON_PV2) && !defined(SILICON_TTC_CORE_SEAGULL)
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#if defined(PHS_SW_DEMO_TTC)
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#define CACHED_TO_NON_CACHED_OFFSET 0x00000000
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#else
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#define CACHED_TO_NON_CACHED_OFFSET 0x20000000
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#endif
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#else
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#define CACHED_TO_NON_CACHED_OFFSET 0x00000000
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#endif
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// since there is an address space shared by Harbell & Boerne (seen by Boerne as 0xD... or by Harbel as 0xBF...)
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#if defined (_TAVOR_BOERNE_)
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#if defined(PHS_SW_DEMO_TTC)
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#define CACHED_TO_NON_CACHED(cACHED) ((void *)(((UINT32)(cACHED)) | (UINT32)CACHED_TO_NON_CACHED_OFFSET))
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#define NON_CACHED_TO_CACHED(nON_CACHED) ((void *)(((UINT32)(nON_CACHED)) & (~(UINT32)CACHED_TO_NON_CACHED_OFFSET)))
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#else
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#define CACHED_TO_NON_CACHED(cACHED) ((void *)(((UINT32)cACHED >= (0xD0000000)) ? ((UINT32)ADDR_CONVERT(cACHED)) \
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: ((((UINT32)(cACHED)) | (UINT32)CACHED_TO_NON_CACHED_OFFSET))))
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#define NON_CACHED_TO_CACHED(nON_CACHED) ((void *)(((UINT32)nON_CACHED < 0xD0000000 && (UINT32)nON_CACHED > 0xBF000000) \
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? ((UINT32)nON_CACHED + 0x11000000) \
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: ((((UINT32)(nON_CACHED)) & (~(UINT32)CACHED_TO_NON_CACHED_OFFSET)))))
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#endif
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#else
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#define CACHED_TO_NON_CACHED(cACHED) ((void *)(((UINT32)(cACHED)) | (UINT32)CACHED_TO_NON_CACHED_OFFSET))
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#define NON_CACHED_TO_CACHED(nON_CACHED) ((void *)(((UINT32)(nON_CACHED)) & (~(UINT32)CACHED_TO_NON_CACHED_OFFSET)))
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#endif
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// Re-define some public MMU-based services
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void* VirtualToPhysical(void* inAddress);
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void* PhysicalToVirtualCached(void* inAddress);
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void* PhysicalToVirtualNonCached(void* inAddress);
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// Other configuration switches
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// IMPORTANT: it is strongly not recommended to run with MMU protection disabled.
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// This allows the software to issue illegal accesses to the XSC Flash, e.g. 32-bit writes.
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// The Gasket in this case rejects the access causing an imprecise abort to the XSC core,
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// leaving caches corrupted, e.g. writing to 0+ area will leave the data written into the D-cache,
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// which may result in incorrect abort exception handling and case debug problems.
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#define ENABLE_PROTECTIONS
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// This definition allows internal-only heap allocation on certain conditions
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#if defined (MMAP_EXTENDED_INT_EXT_RAM_FLASH)
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#define HEAP_MIN_SIZE (0x5a000)
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#else
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#define HEAP_MIN_SIZE (4*0x400)
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#endif
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// for B0: temp until we'll move to SDRAM - use SRAM
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//#define USE_MB_SRAM
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// For HSL on SDK
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// When this define is used the SDK UART port has Rx/Tx only
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// At the moment we have a problem using this as the PS configures the data port as a full UART
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#define SDK_WITH_HSL
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//-----------------------------------------------------------------------------------------------------------------------------
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#if defined(_TAVOR_BOERNE_)
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#define BSP_RAM_IMAGE
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#define DDR_RO_BASE DDR_EXEC_REGION
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#define DDR_RO_SIZE _4MB
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#define DDR_RW_BASE (DDR_RO_BASE+DDR_RO_SIZE)
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#define DDR_RW_SIZE (DDR_EXEC_REGION_SIZE-DDR_RO_SIZE)
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#define EXCEPTION_VECTOR_PHY (UINT32)(&Image$$EXT_RAM_FIRST$$Base)
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#endif
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#if defined(SILICON_TTC)
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#define BSP_RAM_IMAGE
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#define DDR_CP_AREA_SIZE 0x01000000
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#define DDR_RO_BASE (TTC_DDR_BASE+DDR_CP_AREA_SIZE)
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#define DDR_RO_SIZE _4MB
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#define DDR_RW_BASE (DDR_RO_BASE+DDR_RO_SIZE)
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#define DDR_RW_SIZE (_64MB-DDR_RO_SIZE-DDR_CP_AREA_SIZE)
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#define EXCEPTION_VECTOR_PHY (UINT32)(&Image$$EXT_RAM_FIRST$$Base)
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#endif
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//-----------------------------------------------------------------------------------------------------------------------------
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#if defined(_HERMON_B0_SILICON_) && !defined(_TAVOR_BOERNE_)
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// XIP model:
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// - System starts running from flash and uses internal RAM only (these are mapped 1:1)
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// - External memories (RAM and Flash) are/can be mapped to virtual addresses for abstraction (RAM type/address) reasons
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// - or for optimization reasons (form one virtual areas containing both flashes)
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#define BSP_SDRAM_AS_IMAGE_FLASH_SUPPORT
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#define BSP_XIP_FLASH
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// Main external RAM space: default occupies the CS4 (physical only) space.
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//#define EXT_RAM_VIRTUAL 0x10000000 /*Occupy the physical address space of unused CS4 */
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#ifndef EXT_FLASH_VIRTUAL
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// NOTE: the address is chosen to make EXT_FLASH close enough to INT_FLASH.
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// ARM branches (BL) are limited to +/-32MB offset. The linker generates long branch veneers for
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// branches out of this range. The veneer cost is
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// * 1 extra instruction (and ICache line fetch): LDR pc,[pc-4] ;jump to the following address
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// * D-cache line fetch, i.e. stall : DCD target_address
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#define EXT_FLASH_VIRTUAL _4MB
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#endif
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#ifndef EXT_ROM_SIZE
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#define EXT_ROM_SIZE _32MB
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#endif
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#endif // Hermon - XIP
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//-----------------------------------------------------------------------------------------------------------------------------
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#endif //_MMAP_H_
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