82 lines
3.7 KiB
C
82 lines
3.7 KiB
C
/*--------------------------------------------------------------------------------------------------------------------
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(C) Copyright 2006, 2007 Marvell DSPC Ltd. All Rights Reserved.
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-------------------------------------------------------------------------------------------------------------------*/
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/*--------------------------------------------------------------------------------------------------------------------
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INTEL CONFIDENTIAL
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Copyright 2006 Intel Corporation All Rights Reserved.
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The source code contained or described herein and all documents related to the source code (“Material? are owned
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by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or
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its suppliers and licensors. The Material contains trade secrets and proprietary and confidential information of
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Intel or its suppliers and licensors. The Material is protected by worldwide copyright and trade secret laws and
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treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted,
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transmitted, distributed, or disclosed in any way without Intel’s prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual property right is granted to or
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conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement,
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estoppel or otherwise. Any license under such intellectual property rights must be express and approved by
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Intel in writing.
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-------------------------------------------------------------------------------------------------------------------*/
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/************************************************************************/
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/* */
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/* Title: ripc package configuration file */
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/* */
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/* Filename: ripc.h */
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/* */
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/* Authors: Adi Dayan */
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/* */
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/* Target, subsystem: Common Platform, HAL */
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/************************************************************************/
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#ifndef _RIPC_H_
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#define _RIPC_H_
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#define RIPC_SUCEESS 0
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#define RIPC_FAILURE -1
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// The RIPC registers offset
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#define RIPC_STATUS_REG 0x0000 // Status Register
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#define RIPC_AP_INT_REQ 0x0004 // AP INT REQ Register
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#define RIPC_CP_INT_REQ 0x0008 // CP INT REQ Register
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#define RIPC_MSA_INT_REQ 0x000C // MSA INT REQ Register
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#define RIPC_REGISTER_BASE_ADDRESS_0 0xD403D000
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#define RIPC_REGISTER_BASE_ADDRESS_1 0xD403D100
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#define RIPC_REGISTER_BASE_ADDRESS_2 0xD403D200
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#define RIPC_REGISTER_BASE_ADDRESS_3 0xD403D300
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#define RIPC_MAX_NUM 4
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#define RIPC_INT_SRC INTC_IPC_SRV0_CP
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#define RIPC_REG_WRITE(ripc_no,reg,wval) \
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( (* ( (volatile UINT32*)(RIPC_REGISTER_BASE_ADDRESS_0 + (ripc_no)*0x100 +(reg)) ) ) = wval);
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#define RIPC_REG_READ(ripc_no,reg,rval) \
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rval = (* ( (volatile UINT32*)(RIPC_REGISTER_BASE_ADDRESS_0 + (ripc_no)*0x100 + (reg)) ) );
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extern UINT32 ripc_read_status(int ripc_no);
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extern void Release_RIPC(int ripc_no);
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extern void ripc_interrupt_set(int ripc_no);
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extern void ripc_interrupt_clear(int ripc_no);
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extern int Get_RIPC(int ripc_no,int timeout);
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extern void Release_RIPC_ustica(int ripc_no);
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extern int Get_RIPC_ustica(int ripc_no,int timeout);
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#endif
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