232 lines
13 KiB
C
232 lines
13 KiB
C
/*------------------------------------------------------------
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(C) Copyright [2006-2008] Marvell International Ltd.
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All Rights Reserved
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------------------------------------------------------------*/
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/*--------------------------------------------------------------------------------------------------------------------
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INTEL CONFIDENTIAL
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Copyright 2006 Intel Corporation All Rights Reserved.
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The source code contained or described herein and all documents related to the source code ("Material") are owned
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by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or
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its suppliers and licensors. The Material contains trade secrets and proprietary and confidential information of
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Intel or its suppliers and licensors. The Material is protected by worldwide copyright and trade secret laws and
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treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted,
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transmitted, distributed, or disclosed in any way without Intel's prior express written permission.
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No license under any patent, copyright, trade secret or other intellectual property right is granted to or
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conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement,
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estoppel or otherwise. Any license under such intellectual property rights must be express and approved by
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Intel in writing.
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-------------------------------------------------------------------------------------------------------------------*/
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/************************************************************************/
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/* */
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/* Title: GPIO (General Purpose Input Output) HW Header File */
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/* */
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/* Filename: Gpio_Hw.h */
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/* */
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/* Author: Yossi Gabay */
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/* Eilam Ben-Dror */
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/* */
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/* Target, subsystem: Common Platform, HAL */
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/* */
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/* Yaeli Karni Mar 2006, Enhance driver to support Boerne */
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/* */
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/************************************************************************/
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#ifndef _GPIO_HW_H_
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#define _GPIO_HW_H_
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#include "gpio_config.h" // some configurations are shared as INTC and GPIO are coupled
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#define GPIO_PINS_PER_REG 32
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#define GPIO_MAX_PIN_NUMBER (GPIO_PINS_PER_REG - 1)
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#define GPIO_SHIFT_PINS_PER_REG 5
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#define GPIO_SHIFT_PINS_MASK (0x1F)
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#define ALL_HW_BITS 0xFFFFFFFFL
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// The legacy register map has 3 (GPIO_LEGACY_REG_AMOUNT) registers of each type (sequential), which allows for up to 96 GPIOs;
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// For 128 GPIO's option the 4th is in offset 0x100 bytes from the first one (hence, 0x40 words from the first register).
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// This is applicable for registers {GPLRx,GPDRx,GPSRx,GPCRx,GRERx,GFERx,GEDRx}
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// For new Set/Clear registers {GSDR,GCDR,GSFER,GCFER,GSRER,GCRER,AP_MASK,CP_MASK} two options exist:
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// - GPIO_SC_REGS_EMBEDDED: the same approach, while these registers follow previous ones in the register map (TTC layout)
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// - otherwise: 4 registers sequentially located in a separate space after all legacy registers (Tavor layout)
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#if !defined (GPIO_128_ENTRIES)
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#define GPIO_HW_REG_AMOUNT 3
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// next define to allign with changes needed for BVD/BOERNE (see below)
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#define GPIO_REG_INDEX(iNDEX) (iNDEX) // in Hermon platform - registers are sequential
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#define GPIO_SC_REG_INDEX(iNDEX) (iNDEX) // in Hermon platform - registers are sequential
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#else
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#define GPIO_HW_REG_AMOUNT 4
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#define GPIO_REG_INDEX(iNDEX) (((iNDEX)>2)? (0x40+(iNDEX-3)) : iNDEX)
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#if defined(GPIO_SC_REGS_EMBEDDED)
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#define GPIO_SC_REG_INDEX(iNDEX) (((iNDEX)>2)? (0x40+(iNDEX-3)) : iNDEX)
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#else
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#define GPIO_SC_REG_INDEX(iNDEX) (iNDEX)
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#endif
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#endif // GPIO_128_ENTRIES
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#define GPIO_LEGACY_REG_AMOUNT 3
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typedef enum
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{
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GPIO_HW_REG_0 = 0,
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GPIO_HW_REG_1,
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#if defined (GPIO_128_ENTRIES) // In bulverde and boerne we have 4 registers (128 GPIOs)
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GPIO_HW_REG_2,
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GPIO_HW_REG_3,
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#endif
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GPIO_HW_MAX_REG_NUMBER
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}GPIO_HwRegs;
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// Defines the GPIO Controller HW-Structure
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struct GpioController
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{
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UINT32 GPLR[GPIO_LEGACY_REG_AMOUNT]; //pin level register Read (*status)
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UINT32 GPDR[GPIO_LEGACY_REG_AMOUNT]; //pin direction register Read/Write
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UINT32 GPSR[GPIO_LEGACY_REG_AMOUNT]; //pin output set register Write
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UINT32 GPCR[GPIO_LEGACY_REG_AMOUNT]; //pin output clear register Write
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#if !defined (GPIO_APP_LAYOUT) // layouts are different starting at offset 0x30
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UINT32 GSTR[GPIO_LEGACY_REG_AMOUNT]; //source type register (edge/level) Read/Write
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UINT32 GRHR[GPIO_LEGACY_REG_AMOUNT]; //rising edge/high level detect enable Read/Write
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UINT32 GFLR[GPIO_LEGACY_REG_AMOUNT]; //falling edge/low level detect enable Read/Write
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UINT32 GRER[GPIO_LEGACY_REG_AMOUNT]; //rising edge detect register Read (*status)
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UINT32 GFER[GPIO_LEGACY_REG_AMOUNT]; //falling edge detect register Read (*status)
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UINT32 GDBR[GPIO_LEGACY_REG_AMOUNT]; //De-Bounce enable register Read/Write
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UINT32 GDCR; //De-Bounce clock control register Read/Write
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UINT32 GIMR[GPIO_LEGACY_REG_AMOUNT]; //interrupt mask register Read/Write
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UINT32 GIRR[GPIO_LEGACY_REG_AMOUNT]; //interrupt request register Read (*status)
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UINT32 GICR[GPIO_LEGACY_REG_AMOUNT]; //interrupt clear register Write
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UINT32 GSLR; //status latch register (dummy) Write
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UINT32 GPER[GPIO_LEGACY_REG_AMOUNT]; //pull up/down enable register Write
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UINT32 GUDR[GPIO_LEGACY_REG_AMOUNT]; //pull up/down select register Write
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#else
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UINT32 GRER[GPIO_LEGACY_REG_AMOUNT]; //rising edge detect register Read (*status)
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UINT32 GFER[GPIO_LEGACY_REG_AMOUNT]; //falling edge detect register Read (*status)
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UINT32 GEDR[GPIO_LEGACY_REG_AMOUNT];
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#endif
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#if !defined(GPIO_SC_REGS_EMBEDDED)
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UINT32 GAFR_FILLER[(0x100-0x54)/4]; // Filler up to offset 0x100
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#else
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// Bit-wise set/clear type registers for direction and edge detection configuration
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UINT32 GSDR[GPIO_LEGACY_REG_AMOUNT]; // BitWise set of GPIO direction reg
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UINT32 GCDR[GPIO_LEGACY_REG_AMOUNT]; // BitWise clear of GPIO direction reg
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UINT32 GSRER[GPIO_LEGACY_REG_AMOUNT]; // BitWise set of GPIO rising edge detect reg
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UINT32 GCRER[GPIO_LEGACY_REG_AMOUNT]; // BitWise clear of GPIO rising edge detect reg
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UINT32 GSFER[GPIO_LEGACY_REG_AMOUNT]; // BitWise set of GPIO falling edge detect reg
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UINT32 GCFER[GPIO_LEGACY_REG_AMOUNT]; // BitWise clear of GPIO falling edge detect reg
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#if defined(GPIO_CORE_INT_MASK_AP) // Offset 0x9C
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UINT32 INT_MASK_REG[GPIO_LEGACY_REG_AMOUNT]; // The actual core mask register
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#else
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UINT32 INT_MASK_RESERVED_AP[GPIO_LEGACY_REG_AMOUNT];
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#endif
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#if defined(GPIO_CORE_INT_MASK_CP) // Offset 0xA8
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UINT32 INT_MASK_REG[GPIO_LEGACY_REG_AMOUNT]; // The actual core mask register
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#else
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UINT32 INT_MASK_RESERVED_CP[GPIO_LEGACY_REG_AMOUNT];
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#endif
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UINT32 GAFR_FILLER[(0x100-0xb4)/4]; // Filler up to offset 0x100
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#endif
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// More registers exist - of 2 types:
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// 1. extra 4th register for each of the above types GPLR/GPDR/GPSR/ ... in offest 0x100 of the reg0 in the type
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// this is covered by the macro GPIO_REG_INDEX (in Bulverde and in Boerne)
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// 2. special registers to set/clear of specific pins without affecting the other pins:
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// (GSDR, GCDR, GSRER, GCRER, GSFER, GCFER) (BOERNE only)
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#if (GPIO_HW_REG_AMOUNT>3) // Additional registers
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UINT32 GPLR3; // pin level register #4 - accessed via the macro GPIO_REG_INDEX from GPLR
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UINT32 GPLR_FILLER[2]; // reserved registers
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UINT32 GPDR3; // pin direction register #4 - accessed via the macro GPIO_REG_INDEX from GPDR
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UINT32 GPDR_FILLER[2]; // reserved registers
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UINT32 GPSR3; // pin output set register #4 - accessed via the macro GPIO_REG_INDEX from GPSR
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UINT32 GPSR_FILLER[2]; // reserved registers
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UINT32 GPCR3; // pin output clear register #4 - accessed via the macro GPIO_REG_INDEX from GPCR
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UINT32 GPCR_FILLER[2]; // reserved registers
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UINT32 GRER3; // rising edge detect register #4 - accessed via the macro GPIO_REG_INDEX from GRER
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UINT32 GRER_FILLER[2]; // reserved registers
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UINT32 GFER3; // falling edge detect register #4 - accessed via the macro GPIO_REG_INDEX from GFER
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UINT32 GFER_FILLER[2]; // reserved registers
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UINT32 GEDR3; // Edge Detect status register #4 - accessed via the macro GPIO_REG_INDEX from GEDR
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UINT32 GEDR_FILLER[2]; // reserved registers
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#endif
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#if defined(GPIO_SETCLEAR_ACCESS) && !defined(GPIO_SC_REGS_EMBEDDED)
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// Bit-wise set/clear type registers for direction and edge detection configuration
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UINT32 FILLER[(0x400-0x154)/4]; // reserved (0x40e00154 -> 0x40e00400)
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UINT32 GSDR[GPIO_HW_REG_AMOUNT]; // BitWise set of GPIO direction reg
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UINT32 GSDR_FILLER[4]; // reserved registers
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UINT32 GCDR[GPIO_HW_REG_AMOUNT]; // BitWise clear of GPIO direction reg
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UINT32 GCDR_FILLER[4]; // reserved registers
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UINT32 GSRER[GPIO_HW_REG_AMOUNT]; // BitWise set of GPIO rising edge detect reg
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UINT32 GSRER_FILLER[4]; // reserved registers
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UINT32 GCRER[GPIO_HW_REG_AMOUNT]; // BitWise clear of GPIO rising edge detect reg
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UINT32 GCRER_FILLER[4]; // reserved registers
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UINT32 GSFER[GPIO_HW_REG_AMOUNT]; // BitWise set of GPIO falling edge detect reg
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UINT32 GSFER_FILLER[4]; // reserved registers
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UINT32 GCFER[GPIO_HW_REG_AMOUNT]; // BitWise clear of GPIO falling edge detect reg
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UINT32 GCFER_FILLER[4]; // reserved registers
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#endif
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};
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#define GpioHWRegisters (* (volatile struct GpioController *) GPIO_HW_ADDRESS)
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/* To be used by INTC package only */
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// A dummy write should be done before reading any status register: GPLR, GRER, GFER, GIRR
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#define GPIOReadPinLevelRegister(p) (GPIODummyWrite \
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GpioHWRegisters.GPLR[GPIO_REG_INDEX(p)])
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#define GPIOReadRisingEdgeDetectRegister(p) (GPIODummyWrite \
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GpioHWRegisters.GRER[GPIO_REG_INDEX(p)])
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#define GPIOReadFallingEdgeDetectRegister(p) (GPIODummyWrite \
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GpioHWRegisters.GFER[GPIO_REG_INDEX(p)])
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#if defined(GPIO_INT_MASK_REQ_REGS)
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#define GPIOReadRequestRegister(p) (GPIODummyWrite \
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GpioHWRegisters.GIRR[p])
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#define GPIOReadMaskRegister(p) (GPIODummyWrite \
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GpioHWRegisters.GIMR[p])
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#endif
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#if !defined (GPIO_APP_LAYOUT) /*---------------------------------*/
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#define GPIODummyWrite GpioHWRegisters.GSLR = 0,
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#define GPIOReadInterruptStatusReg(p) (GPIODummyWrite \
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GpioHWRegisters.GIRR[p])
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// Micha, Name should Changed to GPIOClearInterruptReg, the additional dummy write is for able to see correct info via Debugger
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//#define GPIOClearEdgeDetectionStatusReg(p,b) (GpioHWRegisters.GICR[p] = b, GPIODummyWrite)
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// REMOVED: Dummy Write after a write is not according to spec (obviously used once for debug as explained above)
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// This case also complicated the macro-definition (problem with comma).
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#define GPIOClearEdgeDetectionStatusReg(p,b) (GpioHWRegisters.GICR[p] = b)
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#else/*INTEL_2CHIP_PLAT_BVD-------------------------------------------*/
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#define GPIODummyWrite
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#define GPIOReadInterruptStatusReg(p) (GpioHWRegisters.GEDR[GPIO_REG_INDEX(p)])
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#define GPIOClearEdgeDetectionStatusReg(p,b) (GpioHWRegisters.GEDR[GPIO_REG_INDEX(p)] = (b))
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#endif/*INTEL_2CHIP_PLAT_BVD-------------------------------------------*/
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/* Clear Interrupt flag of GPIO Pin - GPIO Pin parameter is
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a GPIO pin from GPIO list */
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#define GPIOInterruptClear(gpioPin) (GPIOClearEdgeDetectionStatusReg((gpioPin)>> GPIO_SHIFT_PINS_PER_REG, \
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(0x01UL << ((gpioPin) & GPIO_SHIFT_PINS_MASK))))
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/* GPIO-INTC non-public interface: moved to GPIO_intc.h file due to compilation issues
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GPIO_ReturnCode GPIOEdgeDetectionEnable(GPIO_PinNumbers pinNum);
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GPIO_ReturnCode GPIOEdgeDetectionDisable(GPIO_PinNumbers pinNum);
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BOOL GPIOSetUsedForInterrupt(GPIO_PinNumbers pinNum);
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void GPIOClearUsedForInterrupt(GPIO_PinNumbers pinNum);
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*/
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#endif /* _GPIO_HW_H_ */
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