239 lines
9.9 KiB
C
239 lines
9.9 KiB
C
/*------------------------------------------------------------
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(C) Copyright [2006-2008] Marvell International Ltd.
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All Rights Reserved
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------------------------------------------------------------*/
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/************************************************************************/
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/* */
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/* Title: IPC Comm. pacakge header file */
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/* */
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/* Filename: HwAcs.h */
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/* */
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/* Authors: Adi Dayan */
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/* */
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/* Target, subsystem: Common Platform, HAL */
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/* */
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/* Notes: Addresses and definitions according to the document: */
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/* " Inter Processor Communication (IPC) HW definition, */
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/* WBCDMA EVB, 28-Jun-00, D-Core FPGA IPC Description " */
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/************************************************************************/
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#ifndef _WS_HwAcs_H_
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#define _WS_HwAcs_H_
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/*----------------------------------------------------------------------*/
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#include <gbl_config.h> //For DSP_ROM_MASK definition
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#include "global_types.h"
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/*----------------------------------------------------------------------*/
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/************ IPC Registers Addresses ****************************/
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//same for TTC,Nevo,Wukong,Wujing, segual family CP
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#define IPC_CONTROL_REGISTERS_BASE_ADD 0xD401d000/* base address of the IPC module (APB) */
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#define IPC_CMD_MSG_BUFFER_BASE_ADD BsramBaseAddr
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#define BSRAM_MEMORY_SIZE 0x8000 //32KB
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/************ Cyclic Buffers Parameters ****************************/
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#define TX_CMD_BUFFER_START (IPC_CMD_MSG_BUFFER_BASE_ADD + 0x0000)
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#define TX_CMD_BUFFER_END (IPC_CMD_MSG_BUFFER_BASE_ADD + 0x07fc) // buffer size 0x280 byte
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#define RX_MSG_BUFFER_START (IPC_CMD_MSG_BUFFER_BASE_ADD + 0x0800)
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#define RX_MSG_BUFFER_END (IPC_CMD_MSG_BUFFER_BASE_ADD + 0x0ffc) // buffer size 0x280 byte
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/*----------------------------------------------------------------------*/
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#define TX_CMD_BUFFER_BYTE_SIZE ( (TX_CMD_BUFFER_END+4) - TX_CMD_BUFFER_START )
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#define RX_MSG_BUFFER_BYTE_SIZE ( (RX_MSG_BUFFER_END+4) - RX_MSG_BUFFER_START )
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/************ Control Registers *********************************/
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#define PLP_INT_SET (IPC_CONTROL_REGISTERS_BASE_ADD + 0x0008) /* offset-address of the PLP_INT_SET register */
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#define ACP_INT_CLR (IPC_CONTROL_REGISTERS_BASE_ADD + 0x000C) /* offset-address of the ACP_INT_CLR register */
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#define ACP_DATA_ACK_INT_VEC (IPC_CONTROL_REGISTERS_BASE_ADD + 0x0010) /* offset-address of the ACP_DATA_ACK_INT_VEC register */
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// Poll-values (tail indexes) in DSP memory
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#define CPU2DSP_POLL_REG (IPC_CONTROL_REGISTERS_BASE_ADD + 0x0004) /* offset-address of the POLL_REG register */
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#define DSP2CPU_POLL_REG (IPC_CONTROL_REGISTERS_BASE_ADD + 0x0014) /* offset-address of the POLL_REG register */
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/************ Interrupts Definitions ***************************/
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/** NOTE: the required value to be put in one of the control registers - SET / CLEAR **/
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#define CLR_ACP_RD_INT 0x00000100 /* clears a RD_INT from the DSP */
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#define CLR_ACP_ACK_INT 0x00000200 /* clears an ACK_INT from the DSP */
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#define CLR_ACP_GP_INT 0x00000400 /* clears an GP_INT from the DSP */
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#define CLR_ACP_DATA_ACK_CH_0_INT 0x00000001 /* clears a DATA_ACK_INT on channel 0 from the DSP */
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#define CLR_ACP_DATA_ACK_CH_1_INT 0x00000002 /* clears a DATA_ACK_INT on channel 1 from the DSP */
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#define CLR_ACP_DATA_ACK_CH_2_INT 0x00000004 /* clears a DATA_ACK_INT on channel 2 from the DSP */
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#define CLR_ACP_DATA_ACK_CH_3_INT 0x00000008 /* clears a DATA_ACK_INT on channel 3 from the DSP */
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#define CLR_ACP_DATA_ACK_CH_4_INT 0x00000010 /* clears a DATA_ACK_INT on channel 4 from the DSP */
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#define CLR_ACP_DATA_ACK_CH_5_INT 0x00000020 /* clears a DATA_ACK_INT on channel 5 from the DSP */
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#define CLR_ACP_DATA_ACK_CH_6_INT 0x00000040 /* clears a DATA_ACK_INT on channel 6 from the DSP */
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#define CLR_ACP_DATA_ACK_CH_7_INT 0x00000080 /* clears a DATA_ACK_INT on channel 7 from the DSP */
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#define SET_PLP_RD_INT 0x00000100 /* issues a RD_INT to the DSP */
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#define SET_PLP_ACK_INT 0x00000200 /* issues an ACK_INT to the DSP */
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#define SET_PLP_GP_INT 0x00000400 /* issues an GP_INT to the DSP */
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#define SET_PLP_DATA_ACK_CH_0_INT 0x00000001 /* issues a DATA_ACK_INT on channel 0 to the DSP */
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#define SET_PLP_DATA_ACK_CH_1_INT 0x00000002 /* issues a DATA_ACK_INT on channel 1 to the DSP */
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#define SET_PLP_DATA_ACK_CH_2_INT 0x00000004 /* issues a DATA_ACK_INT on channel 2 to the DSP */
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#define SET_PLP_DATA_ACK_CH_3_INT 0x00000008 /* issues a DATA_ACK_INT on channel 3 to the DSP */
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#define SET_PLP_DATA_ACK_CH_4_INT 0x00000010 /* issues a DATA_ACK_INT on channel 4 to the DSP */
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#define SET_PLP_DATA_ACK_CH_5_INT 0x00000020 /* issues a DATA_ACK_INT on channel 5 to the DSP */
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#define SET_PLP_DATA_ACK_CH_6_INT 0x00000040 /* issues a DATA_ACK_INT on channel 6 to the DSP */
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#define SET_PLP_DATA_ACK_CH_7_INT 0x00000080 /* issues a DATA_ACK_INT on channel 7 to the DSP */
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/************ Interrupts Sources**** ************/
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typedef enum
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{
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RD_INT_SRC,
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ACK_INT_SRC,
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DATA_ACK_INT_SRC,
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GP_INT_SRC,
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MAX_IPC_INT_SRC
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} IpcIntSources;
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#define INTSRC(x) ((INTC_InterruptSources)(_IPCommInterruptSource[x]))
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/************ Control Registers Initiation (clear) Definition ************************/
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#define CLEAR_IPC_REGISTER 0x0000
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#define SET_IPC_REGISTER 0xFFFF
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/*----------------------------------------------------------------------*/
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/******************** Command ********************/
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#define hwAcs_IPC_32bits_WRITE(a) \
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{ ( *( (volatile UINT32*)(_CPU2DSPBufferCurrentPtr) ) = (a) ); \
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if ( _CPU2DSPBufferCurrentPtr == TX_CMD_BUFFER_END ) \
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{ \
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_CPU2DSPBufferCurrentPtr = TX_CMD_BUFFER_START; \
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} \
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else \
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{ \
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_CPU2DSPBufferCurrentPtr += 4; \
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} \
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}
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#define hwAcs_IPC_32bits_CMD_HEADER_WRITE(op,ln) \
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hwAcs_IPC_32bits_WRITE( ( (UINT32)(((ln) << 16) | (op)) ) )
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#define hwAcs_IPC_32bits_DATA_CMD_HEADER_WRITE(dh) \
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{ hwAcs_IPC_32bits_WRITE(*dh); \
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hwAcs_IPC_32bits_WRITE(*(++dh)); \
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}
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#define hwAcs_IPC_32bits_CMD_DATA_WRITE(dt,ln) \
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{ UINT32 x; \
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UINT16 rln = ln; \
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UINT8 *pArr = dt; \
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while (rln >= 4) \
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{ \
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x = ( *(pArr) | (((UINT32)(*(pArr+1)))<<8) | (((UINT32)(*(pArr+2)))<<16) | (((UINT32)(*(pArr+3)))<<24) ); \
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pArr += 4; \
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hwAcs_IPC_32bits_WRITE(x); \
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rln -= 4; \
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}; \
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if (rln == 3) \
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{ \
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x = ( *(pArr) | (((UINT32)(*(pArr+1)))<<8) | (((UINT32)(*(pArr+2)))<<16) ); \
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hwAcs_IPC_32bits_WRITE(x); \
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} \
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else if (rln == 2) \
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{ \
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x = ( *(pArr) | (((UINT32)(*(pArr+1)))<<8) ); \
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hwAcs_IPC_32bits_WRITE(x); \
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} \
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else if (rln == 1) \
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{ \
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x = *(pArr); \
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hwAcs_IPC_32bits_WRITE(x); \
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}; \
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}
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/******************** Message ********************/
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#define MOVE_DSP2CPU_BUFFER_NEXT_PTR(ln)
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#define hwAcs_IPC_32bits_READ(a) \
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{ ( (a) = *( (volatile UINT32*)(_DSP2CPUBufferCurrentPtr) ) ); \
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if ( _DSP2CPUBufferCurrentPtr == RX_MSG_BUFFER_END ) _DSP2CPUBufferCurrentPtr = RX_MSG_BUFFER_START; \
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else _DSP2CPUBufferCurrentPtr += 4; \
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}
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// Read message from DSP with length in bytes - in fragments of 8 bits
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#define hwAcs_IPC_32bits_MSG_HEADER_READ(op,ln) \
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{ UINT32 hd; \
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hwAcs_IPC_32bits_READ(hd); \
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op = (UINT16)(hd); \
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ln = (UINT16)(hd >> 16); \
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}
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/******************** Data ********************/
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#define DATA_TMP_ADD 0x12345678
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#define TMP_DATA_BUFF_SIZE 0x1234
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typedef UINT32 DataBuff[TMP_DATA_BUFF_SIZE];
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#define hwAcs_IPC_DATA_WRITE \
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(*((volatile DataBuff*)(DATA_TMP_ADD)))
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#define hwAcs_IPC_DATA_READ \
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(*((volatile DataBuff*)(DATA_TMP_ADD)))
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/************ Writing to the IPC Control Register ***************************/
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#define hwAcs_IPC_CONTROL_WRITE(IPCCtrlReg,interrupt) \
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(*((volatile UINT32 *)(IPCCtrlReg)) = (interrupt))
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/************ Writing to the Poll Register ***************************/
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#define hwAcs_IPC_POLL_WRITE(val) \
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(*((volatile UINT32 *)(CPU2DSP_POLL_REG)) = (val))
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/************ Reading a Register ***************************/
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UINT32 hwAcs_IPC_REG_READ(UINT32 reg);
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#ifndef IPC_POLL_SOFT_REG
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#ifndef IPC_SAFE_POLL_READ
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#define hwAcs_IPC_POLL_READ hwAcs_IPC_REG_READ(DSP2CPU_POLL_REG)
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#else //PROTO: h/w problem, read value may be corrupted if DSP writes to POLL at the same moment
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UINT32 hwAcs_SafePollRead(void);
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#define hwAcs_IPC_POLL_READ hwAcs_SafePollRead()
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#endif
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#else
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#define hwAcs_IPC_POLL_READ (*(volatile UINT32*)DSP2CPU_POLL_REG)
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#endif
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#define hwAcs_IPC_CONTROL_READ hwAcs_IPC_REG_READ
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/*----------------------------------------------------------------------*/
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/********************** Prototypes ****************************/
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void hwAcsBindLISRToINTC(void);
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void hwAcsUnBindLISRToINTC(void);
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void hwAcsEnableInterrupts(void);
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void hwAcsDisableInterrupts(void);
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void hwAcsLISRAckInt(UINT32 sourceNum);
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void hwAcsLISRRdInt(UINT32 sourceNum);
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void hwAcsLISRDataAckInt(UINT32 sourceNum);
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void hwAcsLISRTTPInt(UINT32 sourceNum);
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void hwAcsConfigureInterrupts(void);
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#define IPC_POLL_IN_ACK
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#endif /* _WS_HwAcs_H_ */
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