195 lines
8.1 KiB
C
195 lines
8.1 KiB
C
#ifndef _QSPI_COMMON_H
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#define _QSPI_COMMON_H
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// ---------------------------------------------------------------
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// Memory Map
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// ---------------------------------------------------------------
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#define QSPI0_REG_BASE 0xd420B000 //QSPI1_IPS_BASE_ADDR
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#define QSPI0_ARDB_BASE 0xa0000000 //AHB RX Data Buffer base addr(QSPI_ARDB0 to QSPI_ARDB31)
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#define QSPI0_AMBA_BASE 0x80000000 //AHB base addr
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#define QSPI0_FLASH_A1_BASE 0x80000000
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#define QSPI0_FLASH_A1_TOP 0x88000000
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#define QSPI0_FLASH_A2_BASE 0x88000000
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#define QSPI0_FLASH_A2_TOP 0x90000000
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#define QSPI0_FLASH_B1_BASE 0x90000000
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#define QSPI0_FLASH_B1_TOP 0x98000000
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#define QSPI0_FLASH_B2_BASE 0x98000000
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#define QSPI0_FLASH_B2_TOP 0xa0000000
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// ---------------------------------------------------------------
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// Register definitions
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// ---------------------------------------------------------------
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#define QSPI_MCR_OFFSET 0x000
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#define QSPI_IPCR_OFFSET 0x008
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#define QSPI_FLSHCR_OFFSET 0x00C
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#define QSPI_BUF0CR_OFFSET 0x010
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#define QSPI_BUF1CR_OFFSET 0x014
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#define QSPI_BUF2CR_OFFSET 0x018
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#define QSPI_BUF3CR_OFFSET 0x01C
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#define QSPI_BFGENCR_OFFSET 0x020
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#define QSPI_SOCCR_OFFSET 0x024
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#define QSPI_BUF0IND_OFFSET 0x030
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#define QSPI_BUF1IND_OFFSET 0x034
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#define QSPI_BUF2IND_OFFSET 0x038
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#define QSPI_SFAR_OFFSET 0x100
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#define QSPI_SFACR_OFFSET 0x104
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#define QSPI_SMPR_OFFSET 0x108
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#define QSPI_RBSR_OFFSET 0x10C
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#define QSPI_RBCT_OFFSET 0x110
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#define QSPI_TBSR_OFFSET 0x150
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#define QSPI_TBDR_OFFSET 0x154
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#define QSPI_TBCT_OFFSET 0x158
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#define QSPI_SR_OFFSET 0x15C
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#define QSPI_FR_OFFSET 0x160
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#define QSPI_RSER_OFFSET 0x164
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#define QSPI_SPNDST_OFFSET 0x168
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#define QSPI_SPTRCLR_OFFSET 0x16C
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#define QSPI_SFA1AD_OFFSET 0x180
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#define QSPI_SFA2AD_OFFSET 0x184
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#define QSPI_SFB1AD_OFFSET 0x188
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#define QSPI_SFB2AD_OFFSET 0x18C
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#define QSPI_DLPV_OFFSET 0x190
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#define QSPI_RBDR0_OFFSET 0x200
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#define QSPI_LUTKEY_OFFSET 0x300
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#define QSPI_LCKCR_OFFSET 0x304
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#define QSPI_LUT0_OFFSET 0x310
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#define QSPI_LUT1_OFFSET 0x314
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#define QSPI_LUT2_OFFSET 0x318
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#define QSPI_LUT3_OFFSET 0x31C
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// ---------------------------------------------------------------
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// Register definitions
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// ---------------------------------------------------------------
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#define QSPI0_MCR (QSPI0_REG_BASE+QSPI_MCR_OFFSET)
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#define QSPI0_IPCR (QSPI0_REG_BASE+QSPI_IPCR_OFFSET)
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#define QSPI0_FLSHCR (QSPI0_REG_BASE+QSPI_FLSHCR_OFFSET)
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#define QSPI0_BUF0CR (QSPI0_REG_BASE+QSPI_BUF0CR_OFFSET)
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#define QSPI0_BUF1CR (QSPI0_REG_BASE+QSPI_BUF1CR_OFFSET)
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#define QSPI0_BUF2CR (QSPI0_REG_BASE+QSPI_BUF2CR_OFFSET)
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#define QSPI0_BUF3CR (QSPI0_REG_BASE+QSPI_BUF3CR_OFFSET)
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#define QSPI0_BFGENCR (QSPI0_REG_BASE+QSPI_BFGENCR_OFFSET)
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#define QSPI0_SOCCR (QSPI0_REG_BASE+QSPI_SOCCR_OFFSET)
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#define QSPI0_BUF0IND (QSPI0_REG_BASE+QSPI_BUF0IND_OFFSET)
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#define QSPI0_BUF1IND (QSPI0_REG_BASE+QSPI_BUF1IND_OFFSET)
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#define QSPI0_BUF2IND (QSPI0_REG_BASE+QSPI_BUF2IND_OFFSET)
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#define QSPI0_SFAR (QSPI0_REG_BASE+QSPI_SFAR_OFFSET)
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#define QSPI0_SFACR (QSPI0_REG_BASE+QSPI_SFACR_OFFSET)
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#define QSPI0_SMPR (QSPI0_REG_BASE+QSPI_SMPR_OFFSET)
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#define QSPI0_RBSR (QSPI0_REG_BASE+QSPI_RBSR_OFFSET)
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#define QSPI0_RBCT (QSPI0_REG_BASE+QSPI_RBCT_OFFSET)
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#define QSPI0_TBSR (QSPI0_REG_BASE+QSPI_TBSR_OFFSET)
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#define QSPI0_TBDR (QSPI0_REG_BASE+QSPI_TBDR_OFFSET)
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#define QSPI0_TBCT (QSPI0_REG_BASE+QSPI_TBCT_OFFSET)
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#define QSPI0_SR (QSPI0_REG_BASE+QSPI_SR_OFFSET)
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#define QSPI0_FR (QSPI0_REG_BASE+QSPI_FR_OFFSET)
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#define QSPI0_RSER (QSPI0_REG_BASE+QSPI_RSER_OFFSET)
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#define QSPI0_SPNDST (QSPI0_REG_BASE+QSPI_SPNDST_OFFSET)
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#define QSPI0_SPTRCLR (QSPI0_REG_BASE+QSPI_SPTRCLR_OFFSET)
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#define QSPI0_SFA1AD (QSPI0_REG_BASE+QSPI_SFA1AD_OFFSET)
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#define QSPI0_SFA2AD (QSPI0_REG_BASE+QSPI_SFA2AD_OFFSET)
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#define QSPI0_SFB1AD (QSPI0_REG_BASE+QSPI_SFB1AD_OFFSET)
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#define QSPI0_SFB2AD (QSPI0_REG_BASE+QSPI_SFB2AD_OFFSET)
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#define QSPI0_DLPV (QSPI0_REG_BASE+QSPI_DLPV_OFFSET)
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#define QSPI0_RBDR0 (QSPI0_REG_BASE+QSPI_RBDR0_OFFSET)
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#define QSPI0_LUTKEY (QSPI0_REG_BASE+QSPI_LUTKEY_OFFSET)
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#define QSPI0_LCKCR (QSPI0_REG_BASE+QSPI_LCKCR_OFFSET)
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#define QSPI0_LUT0 (QSPI0_REG_BASE+QSPI_LUT0_OFFSET)
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#define QSPI0_LUT1 (QSPI0_REG_BASE+QSPI_LUT1_OFFSET)
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#define QSPI0_LUT2 (QSPI0_REG_BASE+QSPI_LUT2_OFFSET)
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#define QSPI0_LUT3 (QSPI0_REG_BASE+QSPI_LUT3_OFFSET)
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#define QSPI0_TBSR_TRBFL_SHIFT 8
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#define QSPI0_TBSR_TRBFL_MASK (0xff << QSPI0_TBSR_TRBFL_SHIFT)
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#define QSPI0_MCR_XIP_EN BIT_23
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#define QSPI0_MCR_SW_PROG_ERASE BIT_22
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#define QSPI0_MCR_SW_HANDLE_XIP BIT_13
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#define QSPI0_MCR_RETRY_XIP_ON BIT_12
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#define QSPI0_SR_AHB_ACC BIT_2
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#define QSPI0_SR_IP_ACC BIT_1
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#define QSPI0_SR_BUSY BIT_0
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#define QSPI0_FR_DLPFF BIT_31
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#define QSPI0_FR_TBFF BIT_27
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#define QSPI0_FR_TBUF BIT_26
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#define QSPI0_FR_ILLINE BIT_23
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#define QSPI0_FR_RBOF BIT_17
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#define QSPI0_FR_RBDF BIT_16
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#define QSPI0_FR_ABSEF BIT_15
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#define QSPI0_FR_AITEF BIT_14
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#define QSPI0_FR_AIBSEF BIT_13
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#define QSPI0_FR_ABOF BIT_12
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#define QSPI0_FR_IUEF BIT_11
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#define QSPI0_FR_IPAEF BIT_7
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#define QSPI0_FR_IPIEF BIT_6
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#define QSPI0_FR_IPGEF BIT_4
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#define QSPI0_FR_XIP_SUSPEND BIT_3
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#define QSPI0_FR_XIP_RESUME BIT_2
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#define QSPI0_FR_XIP_ON BIT_1
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#define QSPI0_FR_TFF BIT_0
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#define QSPI0_RSER_DLPFIE BIT_31
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#define QSPI0_RSER_TBFIE BIT_27
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#define QSPI0_RSER_TBUIE BIT_26
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#define QSPI0_RSER_TBFDE BIT_25
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#define QSPI0_RSER_ILLINIE BIT_23
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#define QSPI0_RSER_RBDDE BIT_21
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#define QSPI0_RSER_RBOIE BIT_17
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#define QSPI0_RSER_RBDIE BIT_16
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#define QSPI0_RSER_ABSEIE BIT_15
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#define QSPI0_RSER_AITIE BIT_14
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#define QSPI0_RSER_AIBSIE BIT_13
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#define QSPI0_RSER_ABOIE BIT_12
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#define QSPI0_RSER_IUEIE BIT_11
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#define QSPI0_RSER_IPAEIE BIT_7
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#define QSPI0_RSER_IPIEIE BIT_6
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#define QSPI0_RSER_IPGEIE BIT_4
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#define QSPI0_RSER_XIP_ON BIT_1
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#define QSPI0_RSER_TFIE BIT_0
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// ---------------------------------------------------------------
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// Enumeration & Structure
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// ---------------------------------------------------------------
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enum QSPI_INST_E {
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QSPI_INSTR_STOP = 0x0,
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QSPI_INSTR_CMD = 0x1,
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QSPI_INSTR_ADDR = 0x2,
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QSPI_INSTR_DUMMY = 0x3,
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QSPI_INSTR_MODE = 0x4,
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QSPI_INSTR_MODE2 = 0x5,
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QSPI_INSTR_MODE4 = 0x6,
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QSPI_INSTR_READ = 0x7,
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QSPI_INSTR_WRITE = 0x8,
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QSPI_INSTR_JMP_ON_CS = 0x9,
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QSPI_INSTR_ADDR_DDR = 0xA,
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QSPI_INSTR_MODE_DDR = 0xB,
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QSPI_INSTR_MODE2_DDR = 0xC,
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QSPI_INSTR_MODE4_DDR = 0xD,
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QSPI_INSTR_READ_DDR = 0xE,
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QSPI_INSTR_WRITE_DDR = 0xF,
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QSPI_INSTR_DATA_LEARN = 0x10
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};
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enum QSPI_PAD_E {
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QSPI_PAD_1X = 0x0,
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QSPI_PAD_2X = 0x1,
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QSPI_PAD_4X = 0x2,
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QSPI_PAD_RSVD = 0x3
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};
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#define EIO 5 /* I/O error */
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#define EAGAIN 11 /* Try again */
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#define ENOMEM 12 /* Out of memory */
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#define ENODEV 19 /* No such device */
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#define EINVAL 22 /* Invalid argument */
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#define EBADMSG 74 /* Not a data message */
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#define ETIMEDOUT 110 /* Connection timed out */
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#define EUCLEAN 117 /* Chip needs cleaning */
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#define ENOTSUPP 524 /* Operation is not supported */
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#define QSPI_FLASH_A1 0 //external/internal qspi A1
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#define SPI_FLASH_INTERNAL 1 //internal spi
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#define QSPI_FLASH_A2 2 //external qspi A2
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#endif // QSPI_COMMON_H
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