171 lines
5.7 KiB
C
171 lines
5.7 KiB
C
#ifndef _CPU_H_
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#define _CPU_H_
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#include <stdint.h>
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#include <stdio.h>
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#include "reg.h"
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/* MFP */
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#define CRANE_MFPR_BASE 0xD401E000
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/* IRQ CONTROLLER */
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#define M_ICU_BASE 0xD4282000
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/* UART */
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#define CRANE_UART0_BASE 0xD4017000
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#define UART0_IRQ 27
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struct crane_uart_registers {
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union {
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uint32_t rbr; //0x0
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uint32_t thr;
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uint32_t dll;
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} uartx0;
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union {
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uint32_t dlh; //0x4
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uint32_t ier;
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} uartx4;
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union {
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uint32_t iir; //0x8
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uint32_t fcr;
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} uartx8;
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uint32_t lcr; //0xc
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uint32_t mcr; //0x10
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uint32_t lsr;
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uint32_t msr;
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uint32_t scr;
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uint32_t isr; //0x20
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uint32_t ffor;
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uint32_t abr;
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uint32_t acr;
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};
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#define IIR_NIP (1 << 0) /* no interrupt pending */
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#define IIR_ABL (1 << 4) /* Auto-band Lock */
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#define LSR_DR (1 << 0) /* Data Ready */
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#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
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#define FCR_RESETTF (1 << 2) /* reset transmit fifo */
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#define FCR_RESETRF (1 << 1) /* reset receive fifo*/
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#define LCR_WLS(x) (((x) & 0x3) << 0) /* word length select*/
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#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
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#define MCR_OUT2 (1 << 3) /* enable uart interrupt */
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#define FCR_TRFIFOE (1 << 0) /* transmit and receive fifo enable */
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#define FCR_TIL (1 << 3) /* interrupt/DMA request when FIFO empty */
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#define FCR_ITL(x) (((x) & 0x3) << 6) /* interrupt trigger threshold 8 bytes */
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#define IER_RAVIE (1 << 0) /* receiver data available */
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#define IER_TIE (1 << 1) /* transmit data request interrupt enable */
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#define IER_RLSE (1 << 2) /* receiver line status */
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#define IER_RTOIE (1 << 4) /* receiver timeout */
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#define IER_UUE (1 << 6) /* uart unit enable */
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#define IER_HSE (1 << 8) /* high speed uart enable */
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#define LSR_TEMT (1 << 6) /* transmitter empty */
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#define LSR_BI (1 << 4) /* break interrupt */
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#define LSR_FE (1 << 3) /* framing error */
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#define LSR_PE (1 << 2) /* parity error */
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#define LSR_OE (1 << 1) /* overrun error */
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#define ABR_ABT (1 << 3) /* table used to calc baud rates */
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#define ABR_ABUP (1 << 2) /* uart programs divisor latch reg */
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#define ABR_ABLIE (1 << 1) /* enable auto-baud-lock interrupt*/
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#define ABR_ABE (1 << 0) /* enable auto-baud */
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/* Timer */
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#define CRANE_APB_TIMER0_BASE 0xD4014000
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#define APB_TIMER0_MAX_DEV_NUM 3 /* counter */
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#define APB_TIMER0_MAX_CHAN_NUM 3 /* match */
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#define APB_TIMER0_DEV0_IRQ 13
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#define APB_TIMER0_DEV1_IRQ 14
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#define APB_TIMER0_DEV2_IRQ 14
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struct crane_timer_registers {
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uint32_t cer; /* 0x0 */
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uint32_t cmr; /* 0x4 */
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uint32_t crsr; /* 0x8 */
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uint32_t ccr; /* 0xc */
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uint32_t t0_match[3]; /* 0x10 */
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uint8_t pad0[0x20 - 0x18 - 4];
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uint32_t t1_match[3]; /* 0x20 */
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uint8_t pad1[0x30 - 0x28 - 4];
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uint32_t t2_match[3]; /* 0x30 */
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uint8_t pad2[0x40 - 0x38 - 4];
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uint32_t plvr[3]; /* 0x40 */
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uint8_t pad3[0x50 - 0x48 - 4];
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uint32_t plcr[3]; /* 0x50 */
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uint8_t pad4[0x60 - 0x58 - 4];
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uint32_t ier[3]; /* 0x60 */
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uint8_t pad5[0x70 - 0x68 - 4];
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uint32_t icr[3]; /* 0x70 */
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uint8_t pad6[0x80 - 0x78 - 4];
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uint32_t sr[3]; /* 0x80 */
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uint8_t pad7[0x90 - 0x88 - 4];
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uint32_t cr[3]; /* 0x90 */
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uint8_t pad8[0xb0 - 0x98 - 4];
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uint32_t wfar; /* 0xb0 */
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uint32_t wsar; /* 0xb4 */
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uint32_t wmer; /* 0xb8 */
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uint32_t wmr; /* 0xbc */
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uint32_t wsr; /* 0xc0 */
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uint32_t wicr; /* 0xc4 */
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uint32_t wcr; /* 0xc8 */
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uint32_t wvr; /* 0xcc */
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};
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#define HW_PLATFORM_TYPE_SILICON 0
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#define HW_PLATFORM_TYPE_FPGA 1
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#define HW_PLATFORM_TYPE_ZEBU_Z1 2
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#define HW_PLATFORM_TYPE_VDK 3
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#define APBC_BASE 0xD4015000
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#define PMU_MAIN_BASE 0xD4050000
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/* PMU AP */
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#define PMU_BASE 0xD4282800
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#define PMU_USB_CLK_RES_CTRL 0x5C
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#define USB_AXI_CLK_EN (1 << 3)
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#define USB_DONGLE_CLK_GATE_MASK (1 << 1)
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#define USB_AXI_RESET (1 << 0)
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/* USB dev */
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#define CRANE_USB_BASE 0xD4208000
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struct crane_udc {
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uint32_t pad0[80];
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uint32_t usbcmd; /* 0x140 */
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uint32_t usbsts; /* 0x144 */
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uint32_t usbintr; /* 0x148 */
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uint32_t frindex;
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uint32_t pad1[1];
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uint32_t devaddr; /* 0x154 */
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uint32_t epinitaddr; /* 0x158 */
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uint32_t pad2[10];
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uint32_t portsc; /* 0x184 */
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uint32_t pad3[8];
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uint32_t usbmode; /* 0x1a8 */
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uint32_t epstat; /* 0x1ac */
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uint32_t epprime; /* 0x1b0 */
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uint32_t epflush; /* 0x1b4 */
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uint32_t pad4;
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uint32_t epcomp; /* 0x1bc */
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uint32_t epctrl[16]; /* 0x1c0 */
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};
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#define EPCTRL_TX_ENABLE (1 << 23)
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#define EPCTRL_RX_ENABLE (1 << 7)
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#define EPCTRL_TX_EP_TYPE_SHIFT 18
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#define EPCTRL_RX_EP_TYPE_SHIFT 2
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/* USB phy */
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#define UTMI_BASE 0xD4207000
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#define UTMI_USB2_REG01 0x4
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#define UTMI_USB2_REG0D 0x34
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#define PLL_IS_READY (1 << 0)
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/* QSPI */
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#define QSPI_IPB_BASE 0xD420B000
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/* DMA */
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#define DMA_BASE 0xD4000000
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#endif /* _CPU_H_ */
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