379 lines
13 KiB
C
379 lines
13 KiB
C
/**
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******************************************************************************
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* @file quec_spi.h
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* @author
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* @version V1.0.0
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* @date 2022-4-6
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* @brief This file contains the common definitions, macros and functions to
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* be shared throughout the project.
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******************************************************************************
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*
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* The MIT License
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* Copyright (c) 2014 QUECTEL Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is furnished
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* to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
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* IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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******************************************************************************
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*/
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#ifndef _QUEC_SPI_H
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#define _QUEC_SPI_H
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#include "common.h"
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/*Read byte from register*/
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#define BU_REG_READ8(x) (*(volatile UINT8 *)(x) & 0xff)
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/*Write byte to register*/
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#define BU_REG_WRITE8(x,y) ((*(volatile UINT8 *)(x)) = (y & 0xff) )
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/* THE BIT DEFINES */
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#define BIT_0 (1 << 0)
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#define BIT_1 (1 << 1)
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#define BIT_2 (1 << 2)
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#define BIT_3 (1 << 3)
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#define BIT_4 (1 << 4)
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#define BIT_5 (1 << 5)
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#define BIT_6 (1 << 6)
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#define BIT_7 (1 << 7)
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#define BIT_8 (1 << 8)
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#define BIT_9 (1 << 9)
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#define BIT_10 (1 << 10)
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#define BIT_11 (1 << 11)
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#define BIT_12 (1 << 12)
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#define BIT_13 (1 << 13)
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#define BIT_14 (1 << 14)
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#define BIT_15 (1 << 15)
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#define BIT_16 (1 << 16)
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#define BIT_17 (1 << 17)
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#define BIT_18 (1 << 18)
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#define BIT_19 (1 << 19)
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#define BIT_20 (1 << 20)
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#define BIT_21 (1 << 21)
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#define BIT_22 (1 << 22)
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#define BIT_23 (1 << 23)
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#define BIT_24 (1 << 24)
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#define BIT_25 (1 << 25)
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#define BIT_26 (1 << 26)
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#define BIT_27 (1 << 27)
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#define BIT_28 (1 << 28)
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#define BIT_29 (1 << 29)
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#define BIT_30 (1 << 30)
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#define BIT_31 ((unsigned)1 << 31)
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#define SHIFT0(Val) (Val)
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#define SHIFT1(Val) ((Val) << 1)
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#define SHIFT2(Val) ((Val) << 2)
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#define SHIFT3(Val) ((Val) << 3)
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#define SHIFT4(Val) ((Val) << 4)
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#define SHIFT5(Val) ((Val) << 5)
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#define SHIFT6(Val) ((Val) << 6)
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#define SHIFT7(Val) ((Val) << 7)
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#define SHIFT8(Val) ((Val) << 8)
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#define SHIFT9(Val) ((Val) << 9)
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#define SHIFT10(Val) ((Val) << 10)
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#define SHIFT11(Val) ((Val) << 11)
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#define SHIFT12(Val) ((Val) << 12)
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#define SHIFT13(Val) ((Val) << 13)
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#define SHIFT14(Val) ((Val) << 14)
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#define SHIFT15(Val) ((Val) << 15)
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#define SHIFT16(Val) ((Val) << 16)
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#define SHIFT17(Val) ((Val) << 17)
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#define SHIFT18(Val) ((Val) << 18)
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#define SHIFT19(Val) ((Val) << 19)
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#define SHIFT20(Val) ((Val) << 20)
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#define SHIFT21(Val) ((Val) << 21)
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#define SHIFT22(Val) ((Val) << 22)
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#define SHIFT23(Val) ((Val) << 23)
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#define SHIFT24(Val) ((Val) << 24)
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#define SHIFT25(Val) ((Val) << 25)
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#define SHIFT26(Val) ((Val) << 26)
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#define SHIFT27(Val) ((Val) << 27)
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#define SHIFT28(Val) ((Val) << 28)
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#define SHIFT29(Val) ((Val) << 29)
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#define SHIFT30(Val) ((Val) << 30)
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#define SHIFT31(Val) ((Val) << 31)
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/* Motorola SPI SSPSCLK phase setting */
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#define SSP_TCR_SPH BIT_11
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/* Motorola SPI SSPSCLK Polarity Setting */
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#define SSP_TCR_SPO BIT_10
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/*SPI MODE*/
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#define SSP_SPI_MODE0 0x00
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#define SSP_SPI_MODE1 SSP_TCR_SPH
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#define SSP_SPI_MODE2 SSP_TCR_SPO
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#define SSP_SPI_MODE3 (SSP_TCR_SPO | SSP_TCR_SPH)
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#define APBC_SSP0_CLK_RST ((volatile UINT32 *)(0xD4015000 + 0x001C))
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#define APBC_SSP2_CLK_RST ((volatile UINT32 *)(0xD4015000 + 0x004C))
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#define SPI_SSP0_BASE 0xD401B000
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#define SPI_SSP2_BASE 0xD401C000
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#define SSP0_TCR ((volatile UINT32 *)(SPI_SSP0_BASE + 0x0000)) /* 32 bit SSP TOP Control Register 0 */
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#define SSP0_FCR ((volatile UINT32 *)(SPI_SSP0_BASE + 0x0004)) /* 32 bit SSP FIFO Control Register 1 */
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#define SSP0_IER ((volatile UINT32 *)(SPI_SSP0_BASE + 0x0008)) /* 32 bit SSP Interrupt Enable Register */
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#define SSP0_TOR ((volatile UINT32 *)(SPI_SSP0_BASE + 0x000C)) /* 32 bit SSP Time Out Register */
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#define SSP0_DR ((volatile UINT32 *)(SPI_SSP0_BASE + 0x0010)) /* 32 bit SSP Data Register */
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#define SSP0_SR ((volatile UINT32 *)(SPI_SSP0_BASE + 0x0014)) /* 32 bit SSP Status Register */
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#define SSP2_TCR ((volatile UINT32 *)(SPI_SSP2_BASE + 0x0000)) /* 32 bit SSP TOP Control Register 0 */
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#define SSP2_FCR ((volatile UINT32 *)(SPI_SSP2_BASE + 0x0004)) /* 32 bit SSP FIFO Control Register 1 */
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#define SSP2_IER ((volatile UINT32 *)(SPI_SSP2_BASE + 0x0008)) /* 32 bit SSP Interrupt Enable Register */
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#define SSP2_TOR ((volatile UINT32 *)(SPI_SSP2_BASE + 0x000C)) /* 32 bit SSP Time Out Register */
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#define SSP2_DR ((volatile UINT32 *)(SPI_SSP2_BASE + 0x0010)) /* 32 bit SSP Data Register */
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#define SSP2_SR ((volatile UINT32 *)(SPI_SSP2_BASE + 0x0014)) /* 32 bit SSP Status Register */
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/* Data Size Select */
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#define SSP_TCR_DSS_MASK SHIFT5(0x1f)
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#define SSP_TCR_DSS32 SHIFT5(0x1f)
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#define SSP_TCR_DSS24 SHIFT5(0x17)
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#define SSP_TCR_DSS16 SHIFT5(0xf)
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#define SSP_TCR_DSS8 SHIFT5(0x7)
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/* SSP Top Control Register */
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/* TXD Three-state Enable On Last Phase */
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#define SSP_TCR_TTELP BIT_18
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/* TXD Three-State Enable */
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#define SSP_TCR_TTE BIT_17
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/* Slave Clock Free Running */
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#define SSP_TCR_SCFR BIT_16
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/* Invert Frame Signal */
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#define SSP_TCR_IFS BIT_15
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/* Hold Frame Low Control */
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#define SSP_TCR_HFL BIT_14
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/* Trailing Byte */
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#define SSP_TCR_TRIAL BIT_13
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/* Loopback Mode */
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#define SSP_TCR_LBM BIT_12
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/* Motorola SPI SSPSCLK phase setting */
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#define SSP_TCR_SPH BIT_11
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/* Motorola SPI SSPSCLK Polarity Setting */
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#define SSP_TCR_SPO BIT_10
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/* Synchronous Serial Port Enable */
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#define SSP_TCR_SSE BIT_0
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/* SSP Interrupt Enable Register */
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/* Transmit FIFO Underrun Interrupt Mask */
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#define SSP_IER_TIM BIT_5
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/* Receive FIFO Overrun Interrupt Mask */
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#define SSP_IER_RIM BIT_4
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/* Transmit FIFO Interrupt Enable */
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#define SSP_IER_TIE BIT_3
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/* Receive FIFO Interrupt Enable */
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#define SSP_IER_RIE BIT_2
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/* Receiver Time-out Interrupt Enable */
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#define SSP_IER_RTOIE BIT_1
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/**/
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#define SSP0_TCR_INITIAL (SSP_TCR_TTELP | SSP_TCR_TTE | SSP_TCR_TRIAL | SSP_TCR_DSS8) // default set data size 8bits
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#define SSP0_FCR_INITIAL (0)
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#define SSP0_IER_INITIAL (SSP_IER_RIM|SSP_IER_TIM)
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#define SSP2_TCR_INITIAL (SSP_TCR_TTELP | SSP_TCR_TTE | SSP_TCR_TRIAL | SSP_TCR_DSS8) // default set data size 8bits
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#define SSP2_FCR_INITIAL (0)
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#define SSP2_IER_INITIAL (SSP_IER_RIM|SSP_IER_TIM)
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#define spi_reg_read(reg) *(volatile unsigned int *)(reg)
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#define spi_reg_write(reg, val) *(volatile unsigned int *)reg = val; *(volatile unsigned int *)reg;
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#define spi_reg_bit_set(reg, val) *(volatile unsigned int *)reg |= val; *(volatile unsigned int *)reg;
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#define spi_reg_bit_clr(reg, val) *(volatile unsigned int *)reg &= ~val; *(volatile unsigned int *)reg;
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/* Transmit FIFO Level: BIT 11:7, when it's 0x0, TXFIFO is emptry or full. */
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#define SSP_SR_TFL 0xF80
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/* Transmit FIFO Not Full: 0 = TXFIFO is ful, 1 = TXFIFO is not full */
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#define SSP_SR_TF_NF (1<<6)
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/* SSP Busy: 0 = SSPx port is idle or disabled, 1 = SSPx port is currently transmitting or receiving framed data */
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#define SSP_SR_BSY (1<<0)
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// Timer out error code 0x80 - 0x8F
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#define SSPWaitTxEmptyTimeOutError 0x80
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#define SSPRdStatusTimeOutError 0x81
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#define SSPWelWaitTxEmptyTimeOutError 0x82
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#define SSPWaitForWELTimeOutError 0x83
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#define SSPWaitCompleteTimeOutError 0x84
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#define SSPRxChannelTimeOutError 0x85
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#define SSPTxChannelTimeOutError 0x86
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// return error code
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#define NoError 0x0
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#define NotFoundError 0x1
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// SUCCESS code
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#define OS_SUCCESS 0x0
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/* Rx FIFO Auto Full Control */
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#define SSP_FCR_RAFC BIT_17
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/* Receive Service Request Enable */
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#define SSP_FCR_RSRE BIT_11
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/* Transmit Service Request Enable */
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#define SSP_FCR_TSRE BIT_10
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/* RXFIFO Trigger Threshold */
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/* MaxBurstSize(DMA)/Data Size Select(SSP) - 1 */
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#define SSP_FCR_RFT_MASK SHIFT5(0x1f)
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#define SSP_FCR_RFT(x) (x << 5)
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/* TXFIFO Trigger Threshold */
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/* MaxBurstSize(DMA)/Data Size Select(SSP) - 1 */
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#define SSP_FCR_TFT_MASK SHIFT0(0x1f)
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#define SSP_FCR_TFT(x) (x << 0)
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/* apb_prdata Read from Rx FIFO Endian */
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#define SSP_FCR_RRE_MASK SHIFT12(0x3)
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#define SSP_FCR_RRE(x) (x << 12)
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#define SSP0_RX_DMA_DEVICE DMAC_SSP_0_RX
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#define SSP0_TX_DMA_DEVICE DMAC_SSP_0_TX
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#define SSP2_RX_DMA_DEVICE DMAC_SSP_2_RX
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#define SSP2_TX_DMA_DEVICE DMAC_SSP_2_TX
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#define SSP0_TX_CHANNEL XLLP_DMAC_CHANNEL_16
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#define SSP0_RX_CHANNEL XLLP_DMAC_CHANNEL_17
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#define SSP2_TX_CHANNEL XLLP_DMAC_CHANNEL_23
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#define SSP2_RX_CHANNEL XLLP_DMAC_CHANNEL_24
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#define SSP0_FCR_DMA_READ (SSP_FCR_RFT(8) | SSP_FCR_TFT(7) | SSP_FCR_RSRE | SSP_FCR_TSRE)
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#define SSP0_FCR_DMA_WRITE (SSP_FCR_TFT(6) | SSP_FCR_RSRE | SSP_FCR_TSRE)
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#define SSP2_FCR_DMA_READ (SSP_FCR_RFT(8) | SSP_FCR_TFT(7) | SSP_FCR_RSRE | SSP_FCR_TSRE)
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#define SSP2_FCR_DMA_WRITE (SSP_FCR_TFT(6) | SSP_FCR_RSRE | SSP_FCR_TSRE)
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typedef enum QUEC_SPI_PORT_ENUM
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{
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QUEC_SPI_PORT_INVALID = -1,
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QUEC_SPI_PORT0 = 0, //GPIO16-GPIO19
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QUEC_SPI_PORT1 = 1, //GPIO33-GPIO36
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QUEC_SPI_PORT_MAX,
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}QUEC_SPI_PORT_E;
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typedef enum{
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SPI_MODE0,
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SPI_MODE1,
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SPI_MODE2,
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SPI_MODE3,
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SPI_MODE_MAX,
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}SPI_MODE_T;
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typedef enum {
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SPI_CLK_100KHZ,
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SPI_CLK_200KHZ,
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SPI_CLK_300KHZ,
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SPI_CLK_400KHZ,
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SPI_CLK_500KHZ,
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SPI_CLK_600KHZ,
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SPI_CLK_700KHZ,
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SPI_CLK_812_5KHZ,
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SPI_CLK_1_625MHZ,
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SPI_CLK_3_25MHZ,
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SPI_CLK_6_5MHZ,
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SPI_CLK_13MHZ,
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SPI_CLK_26MHZ,
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SPI_CLK_52MHZ,
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SPI_CLK_MAX,
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}SPI_CLK_T;
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#define APBC_SSP0_FNCLKSEL_6_5MHZ (0x00<<4)
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#define APBC_SSP0_FNCLKSEL_13MHZ (0x01<<4)
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#define APBC_SSP0_FNCLKSEL_26MHZ (0x02<<4)
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#define APBC_SSP0_FNCLKSEL_52MHZ (0x03<<4)
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#define APBC_SSP0_FNCLKSEL_3_25MHZ (0x04<<4)
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#define APBC_SSP0_FNCLKSEL_1_625MHZ (0x05<<4)
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#define APBC_SSP0_FNCLKSEL_812_5KHZ (0x06<<4)
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#define APBC_SSP0_RST (1<<2)
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#define APBC_SSP0_FNCLK_ENABLE (1<<1)
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#define APBC_SSP0_APBCLK_ENABLE (1<<0)
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#define APBC_SSP2_FNCLKSEL_6_5MHZ (0x00<<4)
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#define APBC_SSP2_FNCLKSEL_13MHZ (0x01<<4)
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#define APBC_SSP2_FNCLKSEL_26MHZ (0x02<<4)
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#define APBC_SSP2_FNCLKSEL_52MHZ (0x03<<4)
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#define APBC_SSP2_FNCLKSEL_3_25MHZ (0x04<<4)
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#define APBC_SSP2_FNCLKSEL_1_625MHZ (0x05<<4)
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#define APBC_SSP2_FNCLKSEL_812_5KHZ (0x06<<4)
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#define APBC_SSP2_RST (1<<2)
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#define APBC_SSP2_FNCLK_ENABLE (1<<1)
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#define APBC_SSP2_APBCLK_ENABLE (1<<0)
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#define APBC_GPIO_CLK_RST ((volatile UINT32 *)(0xD4015000 + 0x0008))
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#define APBC_GPIO_RST (1<<2)
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#define APBC_GPIO_FNCLK_ENABLE (1<<1)
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#define APBC_GPIO_APBCLK_ENABLE (0<<1)
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#define SPI0_CLK ((volatile UINT32 *)(0xD401E000 + 0x11C)) //GPIO16, /SSP0_CLK, AF2
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#define SPI0_FRM ((volatile UINT32 *)(0xD401E000 + 0x120)) //GPIO17, /SSP0_FRM, AF2
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#define SPI0_RXD ((volatile UINT32 *)(0xD401E000 + 0x124)) //GPIO18, /SSP0_RX, AF2
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#define SPI0_TXD ((volatile UINT32 *)(0xD401E000 + 0x128)) //GPIO19, /SSP0_TX, AF2
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#define SPI2_CLK ((volatile UINT32 *)(0xD401E000 + 0x160)) //GPIO33, 0xD401_E160 /SSP2_CLK, AF2
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#define SPI2_FRM ((volatile UINT32 *)(0xD401E000 + 0x164)) //GPIO34, 0xD401_E164 /SSP2_FRM, AF2
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#define SPI2_RXD ((volatile UINT32 *)(0xD401E000 + 0x168)) //GPIO35, 0xD401_E168 /SSP2_RX, AF2
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#define SPI2_TXD ((volatile UINT32 *)(0xD401E000 + 0x16C)) //GPIO36, 0xD401_E16C /SSP2_TX, AF2
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#define SSP_SR_TX_FIFO_NOT_FULL (1<<6)
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#define SSP_SR_RX_FIFO_NOT_EMPTY (1<<14)
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void SPI_SSP0_Initialize(SPI_MODE_T spimode, SPI_CLK_T spiclk);
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void SPI_SSP2_Initialize(SPI_MODE_T spimode, SPI_CLK_T spiclk);
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void QUEC_SPI_SSP0_PIO_transfer(unsigned char *buf_in,unsigned char *buf_out, unsigned int len);
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void QUEC_SPI_SSP2_PIO_transfer(unsigned char *buf_in,unsigned char *buf_out, unsigned int len);
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void QUEC_SPI_SSP0_PIO_Write(unsigned char *buf, unsigned int len);
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void QUEC_SPI_SSP2_PIO_Write(unsigned char *buf, unsigned int len);
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void QUEC_SPI_SSP0_PIO_Read(unsigned char *buf, unsigned int len, unsigned char mosi_status);
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void QUEC_SPI_SSP2_PIO_Read(unsigned char *buf, unsigned int len, unsigned char mosi_status);
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#endif
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